阅读说明：本技术 一种横向绝缘栅双极晶体管结构及其制备方法 (Transverse insulated gate bipolar transistor structure and preparation method thereof ) 是由 刘森 刘筱伟 刘盛富 李建平 史林森 于 2021-11-15 设计创作，主要内容包括：本发明提供一种横向绝缘栅双极晶体管结构及其制备方法,该晶体管结构包括基底、栅介质层、栅导电层、阴极电极层及阳极电极层,其中,基底包括Y方向上依次堆叠的第一半导体层、第一绝缘层、第二半导体层,所述第二半导体层包括在X方向上间隔设置的P型阱区、N型缓冲区及N型漂移区,P型阱区中设有第一P型埋层、位于第一P型埋层上的阴极接触区,N型缓冲区设有具有缺口的第二P型埋层、位于第二P型埋层上的间隔设置的阳极接触区。本发明通过于将阳极接触区间隙中连通的N型缓冲区的上表面设置阳极短路控制栅结构以控制器件进入正常工作状态时的阳极转折电压,且其制备工艺与SOI CMOS工艺兼容。(The invention provides a transverse insulated gate bipolar transistor structure and a preparation method thereof, wherein the transistor structure comprises a substrate, a gate dielectric layer, a gate conducting layer, a cathode electrode layer and an anode electrode layer, wherein the substrate comprises a first semiconductor layer, a first insulating layer and a second semiconductor layer which are sequentially stacked in the Y direction, the second semiconductor layer comprises a P-type well region, an N-type buffer region and an N-type drift region which are arranged at intervals in the X direction, a first P-type buried layer and a cathode contact region positioned on the first P-type buried layer are arranged in the P-type well region, and the N-type buffer region is provided with a second P-type buried layer with a notch and an anode contact region positioned on the second P-type buried layer at intervals. The invention sets anode short circuit control gate structure on the upper surface of the N-type buffer region communicated with the gap of the anode contact region to control the anode breakover voltage when the device enters into normal working state, and the preparation process is compatible with SOI CMOS process.)

1. A preparation method of a transverse insulated gate bipolar transistor structure is characterized by comprising the following steps:

providing a substrate, wherein the substrate comprises a first semiconductor layer, a first insulating layer and a second semiconductor layer which are sequentially stacked in the Y direction, and the conductivity type of the second semiconductor layer is N type;

forming a P-type well region and an N-type buffer region which are arranged at intervals in the X direction in the second semiconductor layer, wherein the part of the semiconductor layer outside the P-type well region and the N-type buffer region is used as an N-type drift region, and the X direction is vertical to the Y direction;

forming a first P-type buried layer in the P-type well region, and forming a second P-type buried layer with a notch in the N-type buffer region;

sequentially forming a gate dielectric layer and a gate conducting layer on the second semiconductor layer, and imaging the gate conducting layer and the gate dielectric layer to obtain a gate structure and an anode short circuit control gate structure, wherein the gate structure is positioned on the upper surface of the P-type well region, and the anode short circuit control gate structure is positioned on the upper surface of the N-type buffer region;

forming a cathode contact region in the P-type well region, and forming an anode contact region in the N-type buffer region, wherein the cathode contact region is located above the first P-type buried layer, and the anode contact region is located above the second P-type buried layer;

and forming a cathode electrode layer and an anode electrode layer on the second semiconductor layer, wherein the lower surface of the cathode electrode layer is in contact with the cathode contact region, and the lower surface of the anode electrode layer is in contact with the anode contact region.

2. The method of claim 1, wherein the step of forming the lateral insulated gate bipolar transistor structure comprises: the substrate further includes a second insulating layer under the first semiconductor layer and a third semiconductor layer under the second insulating layer.

3. The method of claim 1, further comprising the steps of: and forming an isolation groove in the second semiconductor layer at one side of the N-type buffer region, which is far away from the P-type well region, and filling an isolation layer in the isolation groove.

4. The method for manufacturing a lateral insulated gate bipolar transistor structure according to claim 3, further comprising the steps of: and forming a contact hole penetrating through the isolation layer and the first insulation layer, wherein the first semiconductor layer is exposed at the bottom of the contact hole, and a back grid is formed and is positioned on the isolation layer and filled in the contact hole.

5. The method of claim 1, wherein the step of forming the lateral insulated gate bipolar transistor structure comprises: the positive pole short circuit control gate structure includes first control gate structure, second control gate structure and third control gate structure, first control gate structure second control gate structure reaches the equal interval of third control gate structure sets up, third control gate structure reaches the second control gate structure sets gradually in the Z direction, just third control gate structure reaches the second control gate structure all is located in the X direction same one side of first control gate structure, second control gate structure with first control gate structure is less than in the ascending distance of X direction third control gate structure with first control gate structure is at the ascending distance of X direction, wherein, the Z direction perpendicular to the X direction reaches the Y direction.

6. The method of claim 1, wherein the step of forming the lateral insulated gate bipolar transistor structure comprises: the formed cathode contact region comprises a P-type cathode contact region and an N-type cathode contact region which are sequentially arranged in the X direction and are mutually contacted.

7. The method of claim 1, wherein the step of forming the lateral insulated gate bipolar transistor structure comprises: the anode contact area comprises a first anode contact area, a second anode contact area, a third anode contact area and a fourth anode contact area, the first anode contact area, the second anode contact area and the third anode contact area are sequentially arranged at intervals in the X direction, the conductive types of the first anode contact area, the second anode contact area and the third anode contact area are P-type, the fourth anode contact area is located between the first anode contact area and the second anode contact area and is in contact with the first anode contact area and the second anode contact area, and the fourth anode contact area is N-type.

8. A lateral insulated gate bipolar transistor structure, comprising:

the semiconductor device comprises a substrate, wherein the substrate comprises a first semiconductor layer, a first insulating layer and a second semiconductor layer which are sequentially stacked in the Y direction, the second semiconductor layer comprises a P-type well region, an N-type buffer region and an N-type drift region which are arranged at intervals in the X direction, a first P-type buried layer located in the P-type well region and a cathode contact region located on the first P-type buried layer are arranged in the P-type well region, and the N-type buffer region is provided with a second P-type buried layer located in the N-type buffer region and provided with a notch and an anode contact region located above the second P-type buried layer;

the gate dielectric layer is positioned on the P-type well region and the N-type buffer region;

the grid conducting layer is positioned on the grid dielectric layer;

the cathode electrode layer is positioned on the cathode contact area, and the anode electrode layer is positioned on the anode contact area.

9. The lateral insulated gate bipolar transistor structure of claim 8, wherein: the substrate further comprises a second insulating layer located below the first semiconductor layer and a third semiconductor layer located below the second insulating layer, the conductivity type of the second semiconductor layer is N type, and the conductivity type of the first semiconductor layer is P type.

10. The lateral insulated gate bipolar transistor structure of claim 8, wherein: an isolation layer is arranged on one side of the N-type buffer area in the X direction, and a back grid penetrating through the isolation layer and the first insulation layer in the Y direction is arranged in the isolation layer.

11. The lateral insulated gate bipolar transistor structure of claim 8, wherein: the cathode contact region comprises a P-type cathode contact region and an N-type cathode contact region which are located above the first P-type buried layer and are sequentially arranged in the X direction.

12. The lateral insulated gate bipolar transistor structure of claim 8, wherein: the anode contact area comprises a first anode contact area, a second anode contact area, a third anode contact area and a fourth anode contact area, the first anode contact area, the second anode contact area and the third anode contact area are sequentially arranged at intervals in the X direction, the conductive types of the first anode contact area, the second anode contact area and the third anode contact area are P-type, the fourth anode contact area is located between the first anode contact area and the second anode contact area and is in contact with the first anode contact area and the second anode contact area, and the fourth anode contact area is N-type.

13. The lateral insulated gate bipolar transistor structure of claim 8, wherein: the N-type buffer areas which are positioned above the second P-type buried layers and between the anode contact areas are communicated with each other and are communicated with the N-type buffer area which is positioned below the second P-type buried layers through the notches.

14. The lateral insulated gate bipolar transistor structure of claim 8, wherein: the gate dielectric layer and the gate conducting layer form a gate structure and an anode short circuit control gate structure, the gate structure is located on the upper surface of the P-type trap area, and the anode short circuit control gate structure is located on the upper surface of the N-type buffer area above the second P-type buried layer.

15. The lateral insulated gate bipolar transistor structure of claim 14, wherein: the positive pole short circuit control gate structure includes first control gate structure, second control gate structure and third control gate structure, first control gate structure second control gate structure reaches the equal interval of third control gate structure sets up, third control gate structure reaches the second control gate structure sets gradually in the Z direction, just third control gate structure reaches the second control gate structure all is located in the X direction same one side of first control gate structure, second control gate structure with first control gate structure is less than in the ascending distance of X direction third control gate structure with first control gate structure is at the ascending distance of X direction, wherein, the Z direction perpendicular to the X direction reaches the Y direction.

16. The lateral insulated gate bipolar transistor structure of claim 8, wherein: the transistor structure includes two operating states, a unipolar mode and a bipolar mode, when in operation.

17. The lateral insulated gate bipolar transistor structure of claim 16, wherein: when the working voltage of the transistor structure is smaller than a threshold value, the transistor structure works in a unipolar mode, and when the working voltage of the transistor structure is larger than the threshold value, the transistor structure is converted into a bipolar mode to work, and the transistor structure enters a normal working state.

18. The lateral insulated gate bipolar transistor structure of claim 17, wherein: the threshold is the PN junction breakover voltage between the anode contact region and the N-type buffer region which is located above the second P-type buried layer and in the gap of the anode contact region.

19. The lateral insulated gate bipolar transistor structure of claim 17, wherein: the anode short control gate structure controls an anode short condition to control a magnitude of voltage change of the anode when the device is switched from a unipolar mode to a bipolar mode.

Technical Field

The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and relates to a transverse insulated gate bipolar transistor structure and a preparation method thereof.

Background

With the rapid development of new energy vehicles, smart grids, mobile communication and other industries, power semiconductor devices are increasingly viewed. Insulated Gate Bipolar Transistor (IGBT) combines the advantages of Bipolar Transistor (Bipolar) and electrode oxide field effect Transistor (MOSFET), is easy to control, has low on-state voltage, large current density and high breakdown voltage, and is one of the most important power semiconductor devices at present. On the other hand, Silicon-on-Insulator (SOI) has the characteristics of high reliability, high temperature resistance, low power consumption, and the like, and a Lateral Insulated Gate Bipolar Transistor (LIGBT) is integrated on an SOI substrate, so that a micro-electronic system with higher integration level, lower power consumption, and better isolation performance can be realized, and the Silicon-on-Insulator (SOI) is widely applied in the fields of power management, driving of various electronic devices, intelligent switches, and the like, and is favored by industries such as automotive electronics and the internet of things.

However, the presence of large amounts of non-equilibrium carriers within the LIGBT drift region increases the turn-off time and turn-off power consumption. In order to increase the switching speed of the device, researchers have proposed a shorted anode structure. The structure has two working modes of a monopole and a bipolar, when the transistor works in the monopole mode, the device is equivalent to a MOSFET, but in the working mode, the working current is small, and the on-resistance is large; the device is in bipolar mode when operating normally. However, the device has a harmful negative resistance (Snapback) phenomenon in the process of switching from the unipolar mode to the bipolar mode, and the phenomenon is more obvious under a low-temperature condition, even the device cannot be normally started, and the stability of a system controlled by the device is greatly influenced.

Therefore, it is urgently required to develop a lateral insulated gate bipolar transistor structure capable of effectively suppressing the negative resistance phenomenon.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a lateral insulated gate bipolar transistor structure and a method for manufacturing the same, which are used to solve the problem that the negative resistance phenomenon of the lateral insulated gate bipolar transistor affects the system stability in the prior art.

To achieve the above and other related objects, the present invention provides a method for manufacturing a lateral insulated gate bipolar transistor structure, comprising:

providing a substrate, wherein the substrate comprises a first semiconductor layer, a first insulating layer and a second semiconductor layer which are sequentially stacked in the Y direction, and the conductivity type of the second semiconductor layer is N type;

forming a P-type well region and an N-type buffer region which are arranged at intervals in the X direction in the second semiconductor layer, wherein the part of the semiconductor layer outside the P-type well region and the N-type buffer region is used as an N-type drift region, and the X direction is vertical to the Y direction;

forming a first P-type buried layer in the P-type well region, and forming a second P-type buried layer with a notch in the N-type buffer region;

sequentially forming a gate dielectric layer and a gate conducting layer on the second semiconductor layer, and imaging the gate conducting layer and the gate dielectric layer to obtain a gate structure and an anode short circuit control gate structure, wherein the gate structure is positioned on the upper surface of the P-type well region, and the anode short circuit control gate structure is positioned on the upper surface of the N-type buffer region;

forming a cathode contact region in the P-type well region, and forming an anode contact region in the N-type buffer region, wherein the cathode contact region is located above the first P-type buried layer, and the anode contact region is located above the second P-type buried layer;

and forming a cathode electrode layer and an anode electrode layer on the second semiconductor layer, wherein the lower surface of the cathode electrode layer is in contact with the cathode contact region, and the lower surface of the anode electrode layer is in contact with the anode contact region.

Optionally, the substrate further includes a second insulating layer located below the first semiconductor layer and a third semiconductor layer located below the second insulating layer.

Optionally, an isolation trench is formed in the second semiconductor layer on a side of the N-type buffer region away from the P-type well region, and the isolation trench is filled with an isolation layer.

Optionally, a contact hole penetrating through the isolation layer and the first insulating layer is formed, the first semiconductor layer is exposed at the bottom of the contact hole, and a back gate is formed and located on the isolation layer and filled in the contact hole.

Optionally, the positive pole short circuit control gate structure includes first control gate structure, second control gate structure and third control gate structure, first control gate structure second control gate structure reaches the equal interval setting of third control gate structure, third control gate structure reaches the second control gate structure sets gradually in the Z direction, just third control gate structure reaches the second control gate structure all is located in the X direction same one side of first control gate structure, the second control gate structure with first control gate structure is less than in the ascending distance of X direction third control gate structure with first control gate structure is in the ascending distance of X direction, wherein, the Z direction perpendicular to the X direction reaches the Y direction.

Optionally, the cathode contact region is formed to include a P-type cathode contact region and an N-type cathode contact region, which are sequentially arranged in the X direction and are in contact with each other.

Optionally, the anode contact region that forms includes first anode contact region, second anode contact region, third anode contact region and fourth anode contact region, first anode contact region, second anode contact region and third anode contact region set up in order at intervals in the X direction and the conductivity type is the P type, fourth anode contact region is located between first anode contact region and the second anode contact region and with first anode contact region and second anode contact region contact, just fourth anode contact region is the N type.

The present invention also provides a lateral insulated gate bipolar transistor structure comprising:

the semiconductor device comprises a substrate, wherein the substrate comprises a first semiconductor layer, a first insulating layer and a second semiconductor layer which are sequentially stacked in the Y direction, the second semiconductor layer comprises a P-type well region, an N-type buffer region and an N-type drift region which are arranged at intervals in the X direction, a first P-type buried layer located in the P-type well region and a cathode contact region located on the first P-type buried layer are arranged in the P-type well region, and the N-type buffer region is provided with a second P-type buried layer located in the N-type buffer region and provided with a notch and an anode contact region located above the second P-type buried layer;

the gate dielectric layer is positioned on the P-type well region and the N-type buffer region;

the grid conducting layer is positioned on the grid dielectric layer;

the cathode electrode layer is positioned on the cathode contact area, and the anode electrode layer is positioned on the anode contact area.

Optionally, the substrate further includes a second insulating layer located below the first semiconductor layer and a third semiconductor layer located below the second insulating layer, where a conductivity type of the second semiconductor layer is N-type and a conductivity type of the first semiconductor layer is P-type.

Optionally, an isolation layer is disposed on one side of the N-type buffer region in the X direction, and a back gate penetrating through the isolation layer and the first insulation layer in the Y direction is disposed in the isolation layer.

Optionally, the cathode contact region includes a P-type cathode contact region and an N-type cathode contact region located above the first P-type buried layer and sequentially arranged in the X direction.

Optionally, the anode contact region includes a first anode contact region, a second anode contact region, a third anode contact region and a fourth anode contact region, the first anode contact region, the second anode contact region and the third anode contact region are sequentially arranged at intervals in the X direction, and the conductive types are P-type, the fourth anode contact region is located between the first anode contact region and the second anode contact region and is in contact with the first anode contact region and the second anode contact region, and the fourth anode contact region is N-type.

Optionally, the N-type buffer regions located above the second P-type buried layer and between the anode contact regions are communicated with each other and communicated with the N-type buffer region located below the second P-type buried layer through the notch.

Optionally, the gate dielectric layer and the gate conductive layer form a gate structure and an anode short circuit control gate structure, the gate structure is located on the upper surface of the P-type well region, and the anode short circuit control gate structure is located on the upper surface of the N-type buffer region above the second P-type buried layer.

Optionally, the positive pole short circuit control gate structure includes first control gate structure, second control gate structure and third control gate structure, first control gate structure second control gate structure reaches the equal interval setting of third control gate structure, third control gate structure reaches the second control gate structure sets gradually in the Z direction, just third control gate structure reaches the second control gate structure all is located in the X direction same one side of first control gate structure, the second control gate structure with first control gate structure is less than in the ascending distance of X direction third control gate structure with first control gate structure is in the ascending distance of X direction, wherein, the Z direction perpendicular to the X direction reaches the Y direction.

Optionally, the transistor structure comprises two operating states, a unipolar mode and a bipolar mode, when in operation.

Optionally, when the operating voltage of the transistor structure is less than a threshold value, the transistor structure operates in a unipolar mode, and when the operating voltage of the transistor structure is greater than the threshold value, the transistor structure switches to a bipolar mode operation, and the transistor structure enters a normal operating state.

Optionally, the threshold is a PN junction turn-on voltage between the anode contact region and an N-type buffer region located above the second P-type buried layer and in the gap of the anode contact region.

Optionally, the anode short control gate structure controls an anode short condition to control a magnitude of voltage change of the anode when the device is switched from a unipolar mode to a bipolar mode.

As described above, the lateral insulated gate bipolar transistor structure and the method for manufacturing the same according to the present invention are configured such that the first P-type buried layer and the second P-type buried layer having a notch are respectively disposed in the P-type well region and the N-type buffer region, the cathode contact region above the first P-type buried layer, the first anode contact region, the second anode contact region, and the third anode contact region are sequentially disposed at intervals in the X direction above the second P-type buried layer, the fourth anode contact region is disposed between the first anode contact region and the second anode contact region and in contact with the first anode contact region and the second anode contact region, the anode short circuit control gate structure is disposed on the interconnected N-type buffer region above the second P-type buried layer and between the anode contact regions to control the short circuit state of the anode, thereby effectively suppressing the negative resistance phenomenon occurring when the transistor is switched from the unipolar mode to the bipolar mode, the turning voltage value when the negative resistance phenomenon is generated can be controlled through design. In addition, the preparation process of the transistor is compatible with the SOI CMOS process, and has high industrial utilization value.

Drawings

Fig. 1 is a flow chart of a method for fabricating a lateral insulated gate bipolar transistor structure according to the present invention.

Fig. 2 is a schematic cross-sectional view of a first semiconductor layer, a first insulating layer and a second semiconductor layer formed by the method for manufacturing a lateral insulated gate bipolar transistor structure according to the present invention.

Fig. 3 is a schematic cross-sectional view of the lateral insulated gate bipolar transistor structure after the second insulating layer and the third semiconductor layer are formed according to the method of the present invention.

Fig. 4 is a schematic cross-sectional view of a P-well, an N-drift, and an N-buffer formed by the method of the present invention.

Fig. 5 is a schematic cross-sectional view of the first P-type buried layer, the second P-type buried layer with a notch, and the isolation trench formed according to the method for fabricating a lateral insulated gate bipolar transistor structure of the present invention.

Fig. 6 is a schematic perspective view of a lateral insulated gate bipolar transistor structure according to the present invention after forming a first P-type buried layer, a second P-type buried layer having a gap, and an isolation trench.

Fig. 7 is a schematic cross-sectional view of a gate dielectric layer formed by the method for manufacturing a lateral insulated gate bipolar transistor structure according to the present invention.

Fig. 8 is a schematic cross-sectional view of a gate conductive layer formed by the method for manufacturing a lateral insulated gate bipolar transistor structure according to the present invention.

Fig. 9 is a schematic cross-sectional structure diagram of a gate structure and an anode short-circuited control gate structure formed by the method for manufacturing a lateral insulated gate bipolar transistor structure according to the present invention.

Fig. 10 is a cross-sectional view of a lateral igbt structure formed according to the present invention.

Fig. 11 is a schematic cross-sectional view of the XZ plane at the top of the second semiconductor layer of the lateral insulated gate bipolar transistor structure according to the present invention.

Fig. 12 is a schematic perspective view of a lateral insulated gate bipolar transistor structure according to the present invention.

Fig. 13 is an equivalent circuit diagram of the lateral insulated gate bipolar transistor structure according to the present invention.

Fig. 14 is a schematic diagram showing the variation of anode voltage with anode current when different short-circuited anode control gate voltages of the lateral insulated gate bipolar transistor structure according to the present invention are applied.

Element number description: 1 a substrate, 11 a third semiconductor wafer, 111 a third semiconductor layer, 112 a second insulating layer, 2 a first semiconductor wafer, 21 a first semiconductor layer, 3 a second semiconductor wafer, 31 a first insulating layer, 32 a second semiconductor layer, 321P-well regions, 3211 a first P-type buried layer, 322N-type drift region, 323N-type buffer region, 3231 a second P-type buried layer, 3232 notch, 324 cathode contact region, 3241P-type cathode contact region, 3242N-type cathode contact region, 325 anode contact region, 3251 a first anode contact region, 3252 a second anode contact region, 3253 a third anode contact region, 3254 a fourth anode contact region, 4 an isolation trench, 41 an isolation layer, 42 contact holes, 5 a gate dielectric layer, 6 a first conductive layer, 61 a gate structure, 62 an anode short-circuited control gate structure, 621 a first control gate structure, 622 second control gate structure, 623 third control gate structure, 71 cathode electrode layer, 72 anode electrode layer, 73 back gate, 8 equivalent circuit diagram, 81 anode, 82 drift region resistor, 83 anode region resistor, 84 anode short circuit control gate voltage is an I-V curve of 0, 85 anode short circuit control gate voltage is less than an I-V curve of 0, and 86 anode short circuit control gate voltage is greater than an I-V curve of 0.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 14. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

Example one

The present embodiment provides a method for manufacturing a lateral insulated gate bipolar transistor structure, referring to fig. 1, which is a flowchart of the method for manufacturing the lateral insulated gate bipolar transistor structure, and the method includes the following steps:

s1: providing a substrate, wherein the substrate comprises a first semiconductor layer, a first insulating layer and a second semiconductor layer which are sequentially stacked in the Y direction, and the conductivity type of the second semiconductor layer is N type;

s2: forming a P-type well region and an N-type buffer region which are arranged at intervals in the X direction in the second semiconductor layer, wherein the part of the semiconductor layer outside the P-type well region and the N-type buffer region is used as an N-type drift region, and the X direction is vertical to the Y direction;

s3: forming a first P-type buried layer in the P-type well region, and forming a second P-type buried layer with a notch in the N-type buffer region;

s4: sequentially forming a gate dielectric layer and a gate conducting layer on the second semiconductor layer, and imaging the gate conducting layer and the gate dielectric layer to obtain a gate structure and an anode short circuit control gate structure, wherein the gate structure is positioned on the upper surface of the P-type well region, and the anode short circuit control gate structure is positioned on the upper surface of the N-type buffer region;

s5: forming a cathode contact region in the P-type well region, and forming an anode contact region in the N-type buffer region, wherein the cathode contact region is located above the first P-type buried layer, and the anode contact region is located above the second P-type buried layer;

s6: and forming a cathode electrode layer and an anode electrode layer on the second semiconductor layer, wherein the lower surface of the cathode electrode layer is in contact with the cathode contact region, and the lower surface of the anode electrode layer is in contact with the anode contact region.

Referring to fig. 2 and fig. 3, the step S1 is executed: providing a substrate 1, wherein the substrate 1 includes a first semiconductor layer 21, a first insulating layer 31 and a second semiconductor layer 32 stacked in sequence in a Y direction, and a conductivity type of the second semiconductor layer 32 is N type.

Specifically, the conductivity type of the first semiconductor layer 21 is opposite to that of the second semiconductor layer 32.

As an example, as shown in fig. 2, in the present embodiment, the forming the substrate by using a bonding method specifically includes selecting a first semiconductor wafer 2 and a second semiconductor wafer 3, where a conductivity type of the second semiconductor wafer 3 is N-type, a conductivity type of the first semiconductor wafer 2 is opposite to a conductivity type of the second semiconductor wafer 3, forming oxide layers on an upper surface of the first semiconductor wafer 2 and a lower surface of the second semiconductor wafer 3, respectively, aligning and attaching an upper surface of an oxidized portion of the first semiconductor wafer 2 and a lower surface of an oxidized portion of the second semiconductor wafer 3, bonding the first semiconductor wafer 2 and the second semiconductor wafer 3 to form the first insulating layer 31, thinning a lower surface of the first semiconductor wafer 2 and an upper surface of the second semiconductor wafer 3 by using an intelligent lift-off technique, and polishing the thinned lower surface of the first semiconductor wafer 2 and the thinned upper surface of the second semiconductor wafer 3 by a chemical mechanical polishing method to form the first semiconductor layer 21 and the second semiconductor layer 32.

As an example, in another embodiment, the first insulating layer 31 may also be formed by an oxygen implantation method.

As an example, as shown in fig. 3, the substrate 1 further includes a second insulating layer 112 located below the first semiconductor layer 21 and a third semiconductor layer 111 located below the second insulating layer 112. In this embodiment, the forming of the second insulating layer 112 and the third semiconductor layer 111 by using a bonding method specifically includes selecting a third semiconductor wafer 11, forming oxide layers on the lower surface of the first semiconductor wafer 2 and the upper surface of the third semiconductor wafer 11, respectively, aligning and bonding the lower surface of the oxidized portion of the first semiconductor wafer 2 and the upper surface of the oxidized portion of the third semiconductor wafer 11, and bonding the first semiconductor wafer 2 and the second semiconductor wafer 11 to form the third semiconductor layer 111 and the second insulating layer 112.

As an example, in another embodiment, the second insulating layer 112 may also be formed using an oxygen implantation method.

Specifically, the thickness range of the first insulating layer 31 is 2 to 5 μm, and the thickness range of the second insulating layer 112 is 2 to 5 μm. The thickness of the first semiconductor layer 21 may be 6 μm or other suitable thickness, and the thickness of the second semiconductor layer 32 may be 6 μm or other suitable thickness.

Then, referring to fig. 4, the step S2 is executed: p-well 321 and N-buffer 323 spaced apart in the X direction are formed in the second semiconductor layer 32, and the semiconductor layer portion outside the P-well 321 and the N-buffer 323 is used as an N-drift region 322, and the X direction is perpendicular to the Y direction.

As an example, the method of forming the P-well 321 includes ion implantation or other suitable methods, and the method of forming the N-buffer 323 includes ion implantation or other suitable methods, wherein the doping concentration of the P-well 321 is 2 × 10¹⁷/cm^-3Or other suitable concentration, the doping concentration of the N-buffer 323 is 1 x 10¹⁷/cm^-3Or other suitable concentration, the depth of the N-buffer 323 is 2.5 μm or other suitable depth, the length of the N-buffer 323 in the Z direction is 5 μm or other suitable length, and the doping concentration of the N-drift region 34 is 2 x 10¹⁵/cm^-3Or other suitable concentration, the length of the N-drift region 322 in the X direction is 30 μm or other suitable length.

Specifically, after the ion implantation process is performed on the second semiconductor layer 32, a drive-in process is also performed to diffuse the impurity ion distribution.

Referring to fig. 5 to 9, the steps S3 and S4 are executed: forming a first P-type buried layer 3211 in the P-well 321, and forming a second P-type buried layer 3231 having a notch 3232 in the N-buffer 323; sequentially forming a gate dielectric layer 5 and a gate conductive layer 6 on the second semiconductor layer 32, and patterning the gate conductive layer 6 and the gate dielectric layer 5 to obtain the gate structure 61 and the anode short circuit control gate structure 62, wherein the gate structure 61 is located on the upper surface of the P-type well region 321, and the anode short circuit control gate structure 62 is located on the upper surface of the N-type buffer region 323.

For example, an isolation trench 4 is formed in the second semiconductor layer 32 on a side of the N-type buffer region 323 away from the P-type well region 321, and the isolation trench 4 is filled with an isolation layer.

Specifically, as shown in fig. 5 and fig. 6, a cross-sectional structure schematic view and a three-dimensional structure schematic view are respectively shown after the first P-type buried layer 3211, the second P-type buried layer 3231 and the isolation trench 4 are formed.

As an example, forming the first and second P-type buried layers 3211 and 3231 includes:

step S3-1: forming a mask layer on the upper surface of the second semiconductor layer, and patterning the mask layer;

step S3-2: and performing ion implantation on the second semiconductor layer based on the patterned mask layer to form the first P-type buried layer and the second P-type buried layer with the notch, and removing the mask layer.

Specifically, the length of the notch 3232 in the X direction is 0.5 μm or other suitable length, and the length of the notch 3232 in the Z direction is 0.3 μm or other suitable length.

As an example, the isolation trench 4 is adjacent to the N-buffer region 323 and penetrates the second semiconductor layer 32.

Specifically, the second semiconductor layer 32 is etched by at least one of wet etching and dry etching or other suitable methods until the first insulating layer 31 is exposed.

As an example, the method of filling the isolation trench 4 to form the isolation layer includes chemical vapor deposition or other suitable methods.

As an example, as shown in fig. 7, a gate dielectric layer 5 is formed on the upper surface of the second semiconductor layer 32, and a method for forming the gate dielectric layer 5 includes one of a thermal oxidation method and a chemical vapor deposition method, or other suitable methods.

Specifically, the gate dielectric layer 5 is made of silicon oxide or other suitable materials.

As an example, as shown in fig. 8, the first conductive layer 6 is formed on the upper surface of the gate dielectric layer 5 by chemical vapor deposition or other suitable methods.

Specifically, the material of the first conductive layer 6 includes polysilicon or other suitable materials.

As an example, as shown in fig. 9, the gate conductive layer 6 and the gate dielectric layer 5 are patterned to form the gate structure 61 and the anode short control gate structure 62 on the upper surfaces of the P-well 321 and the N-buffer 323, respectively.

Specifically, the anode short circuit control gate structure 62 includes a first control gate structure 621, a second control gate structure 622 and a third control gate structure 623, the first control gate structure 621, the second control gate structure 622 and the third control gate structure 623 are all arranged at an interval, the third control gate structure 623 and the second control gate structure 622 are sequentially arranged in the Z direction, the third control gate structure 623 and the second control gate structure 622 are both located on the same side of the first control gate structure 621 in the X direction, the distance between the second control gate structure 622 and the first control gate structure 621 in the X direction is smaller than the distance between the third control gate structure 623 and the first control gate structure 621 in the X direction, wherein the Z direction is perpendicular to the X direction and the Y direction.

Referring to fig. 10 to 12, the steps S5 and S6 are executed: forming a cathode contact region 324 in the P-well 321, and forming an anode contact region 325 in the N-buffer 323, wherein the cathode contact region 324 is located above the first P-buried layer 3211, and the anode contact region 325 is located above the second P-buried layer 3231; a cathode electrode layer 71 and an anode electrode layer 72 are formed on the second semiconductor layer 32, wherein a lower surface of the cathode electrode layer 71 contacts the cathode contact region 324, and a lower surface of the anode electrode layer 72 contacts the anode contact region 325.

As an example, as shown in fig. 10 and fig. 11, a schematic cross-sectional structure of the transistor structure and a schematic cross-sectional view of the XZ plane on top of the second semiconductor layer 32 are respectively shown.

The cathode contact region 324 is formed to include, as an example, a P-type cathode contact region 3241 and an N-type cathode contact region which are sequentially disposed in the X-direction and are formed to be in contact with each other.

As an example, the anode contact region 325 is formed to include a first anode contact region 3251, a second anode contact region 3252, a third anode contact region 3253 and a fourth anode contact region 3254, the first anode contact region 3251, the second anode contact region 3252 and the third anode contact region 3253 are sequentially spaced in the X direction and are all P-type in conductivity, the fourth anode contact region 3254 is located between the first anode contact region 3251 and the second anode contact region 3252 and is in contact with the first anode contact region 3251 and the second anode contact region 3252, and the fourth anode contact region 3254 is N-type.

Specifically, the P-type cathode contact region 3241, the first anode contact region 3251, the second anode region 3252 and the third anode region 3253 are formed simultaneously by an ion implantation method, and the N-type cathode contact region 3242 and the fourth anode contact region 3254 are formed simultaneously by an ion implantation method.

As an example, a contact hole 42 is formed through the isolation layer 41 and the first insulation layer 31, the bottom of the contact hole 42 exposes the first semiconductor layer 21, and a back gate 73 is formed, and the back gate 73 is located on the isolation layer 41 and filled in the contact hole 42.

Specifically, as shown in fig. 12, which is a schematic perspective view of the transistor structure, the notch 3232 is located at the top of the second P-type buried layer 3231 directly below the third anode contact region 3253 in the Z direction, and the length of the notch 3232 in the X direction is the same as the length of the third anode contact region 3253 in the X direction.

As an example, the anode electrode layer 72 is formed by one of electroplating, physical vapor deposition, and sputtering, or other suitable methods, and the cathode electrode layer 71 is formed by one of electroplating, physical vapor deposition, and sputtering, or other suitable methods.

Specifically, the cathode electrode layer 71 and the anode electrode layer 72 are formed simultaneously.

Specifically, the transistor structure is operated by applying appropriate voltages to the anode electrode layer 72, the cathode electrode layer 71, the gate structure 61 and the back gate 73, and then applying a voltage to the short anode control gate structure 62 to change the breakover voltage when the transistor structure enters normal operation.

In the method for manufacturing a lateral insulated gate bipolar transistor structure of this embodiment, the first anode contact region 3251, the second anode contact region 3252 and the third anode contact region are formed on the second P-type buried layer, the fourth anode contact region 3254 is formed between the first anode contact region 3251 and the second anode contact region 3252, the fourth anode contact region 3254 is in contact with the first anode contact region 3251 and the second anode contact region 3252, an anode short circuit control gate structure 62 is formed on an upper surface of a gap communicating among the first anode contact region 3251, the second anode contact region 3252 and the third anode contact region 3253, an anode electrode layer 72 is formed on an upper surface of the first anode contact region 3251, the second anode contact region 3252, the third anode contact region 3253 and the fourth anode contact region 3254, the breakover voltage of the transistor structure when the transistor structure enters normal operation is controlled by controlling the voltage on the anode short control gate structure 62; an isolation layer 41 is formed on a side of the N-type buffer region 323 away from the P-type well region 321, and a back gate 73 penetrating through the isolation layer 41 and the isolation layer is formed on the isolation layer 41, so that each electrode of the transistor structure is simply led out from above.

Example two

In the present embodiment, a lateral insulated gate bipolar transistor structure is provided, referring to fig. 12, which is a schematic perspective view of the lateral insulated gate bipolar transistor structure, including a substrate 1, a gate dielectric layer 5, a gate conductive layer 6, a cathode electrode layer 71 and an anode electrode layer 72, wherein the substrate 1 includes a first semiconductor layer 21, a first insulating layer 31, a second semiconductor layer 32 stacked in order in a Y direction, the second semiconductor layer 32 includes P-well 321, N-buffer 323 and N-drift 322 spaced apart in the X-direction, a first P-type buried layer 3211 located in the P-type well region 321, a cathode contact region 324 located on the first P-type buried layer 3211 are disposed in the P-type well region 321, the N-type buffer region 323 is provided with a second P-type buried layer 3231 which is positioned in the N-type buffer region 323 and is provided with a notch 3232, and an anode contact region 325 which is positioned on the second P-type buried layer 3231; the gate dielectric layer 5 is located on the P-type well region 321 and the N-type buffer region 323, the gate conductive layer 6 is located on the gate dielectric layer 5, the cathode electrode layer 71 is located on the cathode contact region 324, and the anode electrode layer 72 is located on the anode contact region 325.

As an example, the substrate 1 further includes a second insulating layer 112 located below the first semiconductor layer 21 and a third semiconductor layer 111 located below the second insulating layer 112, the conductivity type of the second semiconductor layer 32 is N-type, and the conductivity type of the first semiconductor layer 21 is P-type.

As an example, an isolation layer 41 is disposed on one side of the N-type buffer region 323 in the X direction, and a back gate 73 penetrating the isolation layer 41 and the first insulating layer 31 in the Y direction is disposed in the isolation layer 41.

As an example, the cathode contact region 324 includes a P-type cathode contact region 3241 and an N-type cathode contact region 3242 sequentially disposed in the X direction above the first P-type buried layer 3211.

As an example, the anode contact region 325 includes a first anode contact region 3251, a second anode contact region 3252, a third anode contact region 3253 and a fourth anode contact region 3254, the first anode contact region 3251, the second anode contact region 3252 and the third anode contact region 3253 are sequentially spaced in the X direction and are all P-type in conductivity, the fourth anode contact region 3254 is located between the first anode contact region 3251 and the second anode contact region 3252 and is in contact with the first anode, 3251 and the second anode contact region 3252, and the fourth anode contact region 3254 is N-type.

By way of example, the N-type buffer regions 323 located above the second P-type buried layers 3231 and between the anode contact regions 325 communicate with each other and with the N-type buffer regions 323 located below the second P-type buried layers 3231 through the notches 3232.

As an example, the gate dielectric layer 5 and the gate conductive layer 6 form a gate structure 61 and an anode short control gate structure 62, the gate structure 61 is located on the upper surface of the P-type well region 321, and the anode short control gate structure 62 is located on the upper surface of the N-type buffer region 323 above the second P-type buried layer 3231.

Specifically, the anode short circuit control gate structure 62 includes a first control gate structure 621, a second control gate structure 622 and a third control gate structure 623, the first control gate structure 621, the second control gate structure 622 and the third control gate structure 623 are all arranged at an interval, the third control gate structure 623 and the second control gate structure 622 are sequentially arranged in the Z direction, the third control gate structure 623 and the second control gate structure 622 are both located on the same side of the first control gate structure 621 in the X direction, the distance between the second control gate structure 622 and the first control gate structure 621 in the X direction is smaller than the distance between the third control gate structure 623 and the first control gate structure 621 in the X direction, wherein the Z direction is perpendicular to the X direction and the Y direction.

As an example, the transistor structure includes two operating states, a unipolar mode and a bipolar mode, when in operation.

Specifically, as shown in fig. 13, which is an equivalent circuit diagram 8 of the lateral igbt structure, when the operating voltage of the transistor structure is smaller than the threshold, the transistor structure operates in the unipolar mode, and when the operating voltage of the transistor structure is larger than the threshold, the transistor structure changes to the bipolar mode to operate, and the transistor structure enters the normal operating state.

As an example, the threshold is a PN junction turn-on voltage between the anode contact region 325 and the N-type buffer region 323 located above the second P-type buried layer 3231 and in the gap of the anode contact region 325. In this embodiment, the threshold is 0.7V, when the transistor structure just enters into forward conduction, it operates in unipolar mode, and as the electron current increases, when the voltage drop on the extraction path of the connected N-type buffer 323 under the first anode short control gate structure 62 reaches 0.7V (diode typical turn-on voltage), the P-type anode contact region and the PN junction of the N-type buffer layer are turned on, and the transistor structure enters into bipolar mode. When the transistor structure enters a bipolar mode from a unipolar modeNegative resistance type, transition voltage V_sbCan be expressed as:

wherein the content of the first and second substances,V _PN is the junction voltage drop of the PN junction (about 0.7V);R _ch 、R _dri andR _SA respectively, a channel resistance, a drift region resistance 82, and an anode region resistance 83.

Specifically, as shown in fig. 14, it is shown that the lateral igbt structure applies I-V curves of different control voltages to the anode short control gate structure 62, wherein an I-V curve 84 of an anode short control gate voltage of 0, an I-V curve 85 of an anode short control gate voltage less than 0, and an I-V curve 86 of an anode short control gate voltage greater than 0 are presented, when the device is switched from the unipolar mode to the bipolar mode, the anode short control gate structure 62 controls the short-circuit state of the anode contact region 325 to control the voltage variation amplitude of the anode 81, that is, when a positive or negative voltage is applied to the shorted anode control gate structure 62, depletion and hole inversion of electrons can be generated below the N-type buffer layer, so as to change R, thereby changing R_SAFinally controlling the breakover voltage V of the transistor structure_sb。

In the lateral insulated gate bipolar transistor structure of this embodiment, the anode contact regions 325 are disposed at intervals on the second P-type buried layer 3231, and the anode short control gate structure 62 is disposed on the upper surface of the N-type buffer region 323 in the communication gap of the anode contact regions 325, so as to control the conduction state of the PN junction between the anode contact regions 325 and the N-type buffer region 323, and further control the transition voltage value when the transistor structure enters the bipolar mode from the unipolar mode; an isolation layer 41 penetrating through the second semiconductor layer 32 and a back gate 73 penetrating through the isolation layer 41 and the first insulation layer 31 are disposed on a side of the N-type buffer region 323 away from the P-type well region 321, so that electrodes of the transistor structure are disposed on a same side, thereby facilitating an electrode lead of the transistor structure.

In summary, according to the lateral insulated gate bipolar transistor structure and the method for manufacturing the same of the present invention, the anode contact region is designed, the anode contact region is disposed on the second P-type buried layer with the notch at an interval, the anode short-circuit control gate structure is disposed on the upper surface of the N-type buffer region in the gap of the anode contact region to control the on-state of the PN junction between the anode contact region and the N-type buffer region, so as to control the voltage value of the anode when the transistor structure enters the bipolar mode, and the isolation layer penetrating the second semiconductor layer and the back gate penetrating the isolation layer and the first insulating layer are disposed on the side of the N-type buffer region away from the P-type well region, so that the electrodes of the transistor structure are disposed on the same side, thereby facilitating the electrode lead of the transistor structure. Therefore, the present invention effectively overcomes various disadvantages of the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.