阅读说明：本技术 升降压变换器及其斜坡补偿电路 (Buck-boost converter and slope compensation circuit thereof ) 是由 王发刚 罗强 于 2021-08-11 设计创作，主要内容包括：提供了升降压变换器及其斜坡补偿电路。用于升降压变换器的斜坡补偿电路,包括：斜坡电压生成电路,被配置为基于基准电压,生成第一和第二斜坡电压；以及补偿电流生成电路,被配置为基于基准电压、第一和第二斜坡电压、以及升降压变换器的输入和输出电压,生成第一和第二补偿电流,第一补偿电流的变化斜率随着第一斜坡电压的变化而变化,第二补偿电流的变化斜率随着第二斜坡电压的变化而变化。根据本发明实施例的用于升降压变换器的斜坡补偿电路可以生成变化斜率变化的第一和第二补偿电流,从而可以使升降压变换器同时满足宽输入/宽输出电压和高功率带载要求。(A buck-boost converter and a slope compensation circuit thereof are provided. A slope compensation circuit for a buck-boost converter, comprising: a ramp voltage generation circuit configured to generate first and second ramp voltages based on a reference voltage; and a compensation current generation circuit configured to generate first and second compensation currents based on the reference voltage, the first and second ramp voltages, and input and output voltages of the buck-boost converter, a change slope of the first compensation current varying with a change in the first ramp voltage, and a change slope of the second compensation current varying with a change in the second ramp voltage. The slope compensation circuit for the buck-boost converter can generate the first compensation current and the second compensation current with the changed slope, so that the buck-boost converter can meet the requirements of wide input/wide output voltage and high power on-load at the same time.)

1. A slope compensation circuit for a buck-boost converter, comprising:

a ramp voltage generation circuit configured to generate first and second ramp voltages based on a reference voltage; and

a compensation current generation circuit configured to generate first and second compensation currents based on the reference voltage, the first and second ramp voltages, and input and output voltages of the buck-boost converter, a change slope of the first compensation current varying with a change of the first ramp voltage, and a change slope of the second compensation current varying with a change of the second ramp voltage.

2. The slope compensation circuit of claim 1, wherein the slope voltage generation circuit is further configured to:

generating an oscillating clock signal based on the reference voltage;

generating first and second clock signals based on the oscillating clock signal;

generating the first ramp voltage based on the first clock signal; and

generating the second ramp voltage based on the second clock signal.

3. The slope compensation circuit of claim 2, wherein the slope voltage generation circuit is further configured to:

generating a ramp oscillation voltage using a first current source and a first capacitor based on the reference voltage; and

generating the oscillating clock signal with a voltage comparator based on the reference voltage and the ramped oscillating voltage.

4. The slope compensation circuit of claim 2, wherein the slope voltage generation circuit is further configured to:

generating the first ramp voltage with a second current source and a second capacitor based on the first clock signal.

5. The slope compensation circuit of claim 2, wherein the slope voltage generation circuit is further configured to:

generating the second ramp voltage with a third current source and a third capacitor based on the second clock signal.

6. The slope compensation circuit of claim 1, wherein the compensation current generation circuit is further configured to:

generating at least two threshold voltages based on the reference voltage;

generating the first compensation current based on the input and output voltages of the buck-boost converter according to the magnitude comparison relationship between the first ramp voltage and the at least two threshold voltages; and

and generating the second compensation current based on the input voltage and the output voltage of the buck-boost converter according to the magnitude comparison relation between the second ramp voltage and the at least two threshold voltages.

7. The slope compensation circuit of claim 6, wherein the compensation current generation circuit is further configured to:

generating the at least two threshold voltages with a resistive voltage divider network based on the reference voltage.

8. The slope compensation circuit of claim 6, wherein the at least two threshold voltages increase sequentially, the compensation current generation circuit further configured to:

generating first and second reference currents based on input and output voltages of the buck-boost converter;

generating a first set of mirror currents based on the first reference current, wherein the first set of mirror currents includes at least two mirror currents;

generating a second set of mirror currents based on the second reference current, wherein the second set of mirror currents includes at least two mirror currents;

generating the first compensation current based on at least one mirror current of the first set of mirror currents when the first ramp voltage is not less than a minimum threshold voltage of the at least two threshold voltages; and

generating the second compensation current based on at least one mirror current of the second set of mirror currents when the second ramp voltage is not less than a minimum threshold voltage of the at least two threshold voltages.

9. The slope compensation circuit of claim 8, wherein the compensation current generation circuit is further configured to:

generating the first and second reference currents with a transconductance amplifier based on input and output voltages of the buck-boost converter.

10. The slope compensation circuit of claim 9, wherein the first compensation current is zero when the first slope voltage is less than a minimum threshold voltage of the at least two threshold voltages, and the second compensation current is zero when the second slope voltage is less than the minimum threshold voltage of the at least two threshold voltages.

11. A buck-boost converter including the slope compensation circuit of any one of claims 1 to 10.

Technical Field

The invention relates to the field of circuits, in particular to a buck-boost converter and a slope compensation circuit thereof.

Background

Currently, power supply systems such as adapter power supplies, automotive power supplies, and portable mobile power supplies can produce output voltages that are higher, lower, or equal to the input voltage. The wide output voltage (5-48V) and high power on-load requirements (up to 240W) present significant challenges to the design of these power supply systems.

Disclosure of Invention

The slope compensation circuit for the buck-boost converter comprises the following components: a ramp voltage generation circuit configured to generate first and second ramp voltages based on a reference voltage; and a compensation current generation circuit configured to generate first and second compensation currents based on the reference voltage, the first and second ramp voltages, and input and output voltages of the buck-boost converter, a change slope of the first compensation current varying with a change in the first ramp voltage, and a change slope of the second compensation current varying with a change in the second ramp voltage.

The slope compensation circuit for the buck-boost converter can generate the first compensation current and the second compensation current with the changed slope, so that the buck-boost converter can meet the requirements of wide input/wide output voltage and high power on-load at the same time.

According to the embodiment of the invention, the buck-boost converter comprises the slope compensation circuit for the buck-boost converter.

The buck-boost converter provided by the embodiment of the invention can simultaneously meet the requirements of wide input/wide output voltage and high power on-load.

Drawings

The invention may be better understood from the following description of specific embodiments thereof taken in conjunction with the accompanying drawings, in which:

fig. 1 shows a schematic block diagram of a slope compensation circuit for a buck-boost converter according to an embodiment of the invention;

fig. 2 shows an example circuit diagram of the ramp voltage generating circuit shown in fig. 1;

FIG. 3 illustrates an example circuit diagram of the compensation current generation circuit shown in FIG. 1;

fig. 4 illustrates example waveform diagrams of a plurality of signals associated with the ramp voltage generating circuit shown in fig. 2 and the compensation current generating circuit shown in fig. 3.

Detailed Description

Features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is in no way limited to any specific configuration and algorithm set forth below, but rather covers any modification, replacement, and improvement of elements, components, and algorithms without departing from the spirit of the invention. In the drawings and the following description, well-known structures and techniques are not shown to avoid unnecessarily obscuring the present invention.

In order to meet the wide input/wide output voltage requirement, a power supply system is changed from a simple buck converter or a boost converter to a buck-boost converter. Fixed frequency current mode buck-boost converters require a slope compensation circuit to solve the subharmonic oscillation problem. However, the conventional fixed slope compensation technique cannot make the buck-boost converter satisfy both the wide input/wide output voltage and the high power on-load requirement.

In view of the above problems, the present invention provides a slope compensation circuit for a buck-boost converter, which can make the buck-boost converter satisfy both the wide input/wide output voltage and the high power on-load requirement.

Fig. 1 illustrates an example block diagram of a slope compensation circuit for a buck-boost converter in accordance with an embodiment of this disclosure. As shown in fig. 1, a slope compensation circuit 100 for a buck-boost converter includes a slope voltage generation circuit 102 and a compensation current generation circuit 104, wherein: the ramp voltage generation circuit 102 is configured to generate first and second ramp voltages based on the reference voltage; the compensation current generation circuit 104 is configured to generate first and second compensation currents based on the reference voltage, the first and second ramp voltages, and input and output voltages of the buck-boost converter. Here, the change slope of the first compensation current is changed with a change of the first ramp voltage, and the change slope of the second compensation current is changed with a change of the second ramp voltage.

The slope compensation circuit for the buck-boost converter can generate the first compensation current and the second compensation current with the changed slope, so that the buck-boost converter can meet the requirements of wide input/wide output voltage and high power on-load at the same time.

In some embodiments, the ramp voltage generation circuit 102 may be further configured to: generating an oscillating clock signal based on the reference voltage; generating first and second clock signals based on the oscillating clock signal; generating a first ramp voltage based on a first clock signal; and generating a second ramp voltage based on the second clock signal.

In some embodiments, the ramp voltage generation circuit 102 may be further configured to: generating a ramp oscillation voltage using a first current source and a first capacitor based on a reference voltage; and generating an oscillating clock signal with a voltage comparator based on the reference voltage and the ramp oscillating voltage.

In some embodiments, the ramp voltage generation circuit 102 may be further configured to: generating a first ramp voltage using a second current source and a second capacitor based on a first clock signal; a second ramp voltage is generated with a third current source and a third capacitor based on the second clock signal.

In some embodiments, the compensation current generation circuit 104 may be further configured to: generating at least two threshold voltages based on a reference voltage; generating a first compensation current based on the input voltage and the output voltage of the buck-boost converter according to the magnitude comparison relation between the first ramp voltage and at least two threshold voltages; and generating a second compensation current based on the input voltage and the output voltage of the buck-boost converter according to the magnitude comparison relation between the second ramp voltage and at least two threshold voltages.

In some embodiments, the compensation current generation circuit 104 may be further configured to: at least two threshold voltages are generated using a resistive voltage divider network based on a reference voltage.

In some embodiments, where the at least two threshold voltages are sequentially increased, the compensation current generation circuit 104 may be further configured to: generating first and second reference currents based on input and output voltages of the buck-boost converter; generating a first set of mirror currents based on the first reference current, wherein the first set of mirror currents includes at least two mirror currents; generating a second set of mirror currents based on the second reference current, wherein the second set of mirror currents includes at least two mirror currents; generating a first compensation current based on at least one mirror current of the first set of mirror currents when the first ramp voltage is not less than a minimum threshold voltage of the at least two threshold voltages; when the second ramp voltage is not less than the minimum threshold voltage of the at least two threshold voltages, a second compensation current is generated based on at least one mirror current of the second set of mirror currents.

In some embodiments, the compensation current generation circuit 104 may be further configured to: first and second reference currents are generated using a transconductance amplifier based on input and output voltages of the buck-boost converter.

In some embodiments, the first compensation current is zero when the first ramp voltage is less than the first threshold voltage, and the second compensation current is zero when the second ramp voltage is less than the first threshold voltage.

Fig. 2 shows an example circuit diagram of the ramp voltage generation circuit shown in fig. 1. In the example circuit shown in FIG. 2, CLK _ OSC represents the oscillating clock signal, CLK _ BUK represents the first clock signal, CLK _ BST represents the second clock signal, V_REFRepresents a reference voltage, V_{RMP_OSC}Representing a ramp oscillating voltage, V_{RMP_BUK}Representing a first ramp voltage, V_{RMP_BST}Represents a second ramp voltage, wherein: the oscillation clock signal CLK _ OSC controls the on and off of the switch tube M1; when the switch M1 is in the off state, the first current source I1 charges the first capacitor C1, generating a ramp oscillating voltage V across the first capacitor C1_{RMP_OSC}(ii) a Voltage comparator 1 for ramp oscillation voltage V_{RMP_OSC}And a reference voltage V_REFComparing to generate an oscillation clock signal CLK _ OSC; the frequency divider divides the frequency of the oscillation clock signal CLK _ OSC to generate a second clock signal CLK _ BST; the inverter inverts the second clock signal CLK _ BST to generate a first clock signal CLK _ BUK which has the phase opposite to that of the second clock signal CLK _ BST and has the same frequency; the one-shot circuit 1 is controlled on based on the first clock signal CLK _ BUKThe switch-on and switch-off of the switch-off pipe M2; when the switch transistor M2 is in an off state, the second current source I2 charges the second capacitor C2, and generates the first ramp voltage V across the second capacitor C2_{RMP_BUK}(ii) a The one-shot circuit 2 controls the switching tube M3 to be turned on and off based on the second clock signal CLK _ BST; when the switch M3 is in the off state, the third current source I3 charges the third capacitor C3, and generates the second ramp voltage V across the third capacitor C3_{RMP_BST}。

In some examples, the frequency of the oscillating clock signal CLK _ OSC may be twice the frequency of the first clock signal CLK _ BUK and the second clock signal CLK _ BST, when the first current I1 from the first current source I1, the second current I2 from the second current source I2, the third current I3 from the third current source I3, the capacitance C1 of the first capacitor C1, the capacitance C2 of the second capacitor C2, and the capacitance C3 of the third capacitor C3 satisfy the following equation (1):

I₁/C₁＝2*I₂/C₂＝2*I₃/C₃equation (1)

Fig. 3 shows an example circuit diagram of the compensation current generation circuit shown in fig. 1. In the example circuit shown in FIG. 3, I_SINKRepresents a first reference current, I_SOURCERepresents a second reference current, I_D2、I_D3、I_D4Respectively representing a first, a second and a third mirror current constituting a first set of mirror currents, I_D15、I_D16、I_D17Respectively representing a fourth, fifth and sixth mirror current, I, constituting a second set of mirror currents_{SLP_BUK}Represents the first compensation current, I_{SLP_BST}Representing a second compensation current, V_OUTRepresenting the output voltage, V, of a buck-boost converter_INRepresenting the input voltage, V, of a buck-boost converter_REFRepresents a reference voltage, V_T1、V_T2、V_T3Respectively, represent first, second and third threshold voltages, V_{RMP_BUK}Representing a first ramp voltage, V_{RMP_BST}Represents a second ramp voltage, wherein: reference voltage V_REFThe first, second, and third resistors are generated by a buffer OP and a resistor divider network (including resistors R1-R4)Threshold voltage V_T1、V_T2、V_T3，V_T1<V_T2<V_T3(ii) a k times (0)<k<1) Output voltage k V_OUTAnd k times (0)<k<1) Input voltage k V_INGenerating a first and a second reference current I by means of a transconductance amplifier Gm_SINKAnd I_SOURCE(ii) a When V is_OUT<V_INThe transconductance amplifier Gm generates a first reference current I_SINK(ii) a First reference current I_SINKGenerating a first, a second and a third mirror current I by means of a current mirror_D2、I_D3、I_D4(ii) a When V is_{RMP_BUK}<V_T1While a first compensating current I_{SLP_BUK}Equal to 0; when V is_T1<V_{RMP_BUK}<V_T2When, I_{SLP_BUK}＝I_D2(ii) a When V is_T2<V_{RMP_BUK}<V_T3When, I_{SLP_BUK}＝I_D2+I_D3(ii) a When V is_T3<V_{RMP_BUK}When, I_{SLP_BUK}＝I_D2+I_D3+I_D4(ii) a When V is_OUT>V_INThe transconductance amplifier Gm generates a second reference current I_SOURCE(ii) a Second reference current I_SOURCEGenerating a fourth, fifth and sixth mirrored current I by means of a current mirror_D15、I_D16、I_D17(ii) a When V is_{RMP_BST}<V_T1While the second compensating current I_{SLP_BST}Equal to 0; when V is_T1<V_{RMP_BST}<V_T2When, I_{SLP_BST}＝I_D15(ii) a When V is_T2<V_{RMP_BST}<V_T3When, I_{SLP_BST}＝I_D15+I_D16(ii) a When V is_T3<V_{RMP_BST}When, I_{SLP_BST}＝I_D15+I_D16+I_D17。

Fig. 4 illustrates example waveform diagrams of a plurality of signals associated with the ramp voltage generating circuit shown in fig. 2 and the compensation current generating circuit shown in fig. 3. As can be seen from FIG. 4, the ramp oscillating voltage V_{RAMP_OSC}Gradually increases from its minimum value and increases to a reference voltage V_REFRapidly decreases in time; oscillating voltage V at a ramp_{RAMP_OSC}From which it is possible toThe minimum value gradually increases to the reference voltage V_REFIn the process (2), the oscillation clock signal CLK _ OSC is at a high level; oscillating voltage V at a ramp_{RAMP_OSC}From a reference voltage V_REFIn the process of decreasing to its minimum value, the oscillating clock signal CLK _ OSC is at a low level; the first ramp voltage V is applied during each period of the first clock signal CLK _ BUK_{RAM_BUK}Increases from its minimum value to a first threshold voltage V_T1From a first threshold voltage V_T1Increase to a second threshold voltage V_T2From the second threshold voltage V_T2Increase to a third threshold voltage V_T3And then from the third threshold voltage V_T3Increase to its maximum value; first compensation current I_{SLP_BUK}At a first ramp voltage V_{RAM_BUK}Increases from its minimum value to a first threshold voltage V_T1Is kept constant at a first ramp voltage V_{RAM_BUK}From a first threshold voltage V_T1Increase to a second threshold voltage V_T2Decreases with a first slope at a first ramp voltage V_{RAM_BUK}From the second threshold voltage V_T2Increase to a third threshold voltage V_T3Decreases with a second slope and at a first ramp voltage V_{RAM_BUK}From the third threshold voltage V_T3Decreases at a third slope in increasing to its maximum; the second ramp voltage V is applied during each period of the second clock signal CLK _ BST_{RAM_BST}Increases from its minimum value to a first threshold voltage V_T1From a first threshold voltage V_T1Increase to a second threshold voltage V_T2From the second threshold voltage V_T2Increase to a third threshold voltage V_T3And then from the third threshold voltage V_T3Increase to its maximum value; second compensation current I_{SLP_BST}At a second ramp voltage V_{RAM_BST}Increases from its minimum value to a first threshold voltage V_T1Is kept constant at a second ramp voltage V_{RAM_BST}From a first threshold voltage V_T1Increase to a second threshold voltage V_T2Increases with a fourth slope at a second ramp voltage V_{RAM_BST}From the second threshold voltage V_T2Increase to a third threshold voltage V_T3In the course of (1) increases with a fifth slopeLarge and at a second ramp voltage V_{RAM_BST}From the third threshold voltage V_T3Increasing to its maximum with a sixth slope.

In a buck-boost converter comprising the ramp generating circuit shown in fig. 2 and the compensation current generating circuit shown in fig. 3, due to the first compensation current I_{SLP_BUK}And a second compensation current I_{SLP_BST}Respectively with a first ramp voltage V_{RAM_BUK}And a second ramp voltage V_{RAM_BST}Can meet the requirements of wide input/wide output voltage and high power band-load simultaneously.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. For example, the algorithms described in the specific embodiments may be modified without departing from the basic spirit of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.