阅读说明：本技术 一种基于ibis模型评估dac抗扰性能的测试方法 (Test method for evaluating DAC (digital-to-analog converter) interference rejection performance based on IBIS (intermediate bulk information system) model ) 是由 刘红侠 郭丹 于 2021-08-16 设计创作，主要内容包括：本发明提供的一种基于IBIS模型评估DAC抗扰性能的测试方法,通过获取数模转换DAC芯片IBIS电路模型；基于DAC芯片IBIS电路模型,建立在两种工作模式下测试DAC芯片的测试电路；当在两种工作模式下的测试电路分别测试DAC芯片时,获得加EFT信号干扰的测试结果和不加EFT信号干扰的测试结果；将加EFT信号干扰的测试结果与不加EFT信号干扰的测试结果进行对比,获得DAC芯片的抗干扰性能。因此本发明可以有效地对型号为AD5761R/AD5721R的DAC芯片抗EFT能力进行测试,有利于快速找到满足防护需求的芯片,进而减少设计成本和开发周期。(The invention provides a test method for evaluating DAC (digital-to-analog conversion) interference rejection performance based on an IBIS (intermediate bulk information system) model, which comprises the steps of obtaining an IBIS circuit model of a digital-to-analog conversion DAC chip; establishing a test circuit for testing the DAC chip in two working modes based on the DAC chip IBIS circuit model; when the DAC chip is respectively tested by the test circuit under two working modes, obtaining a test result with EFT signal interference and a test result without EFT signal interference; and comparing the test result with the EFT signal interference with the test result without the EFT signal interference to obtain the anti-interference performance of the DAC chip. Therefore, the invention can effectively test the EFT resistance of the DAC chip with the model number of AD5761R/AD5721R, is beneficial to quickly finding the chip meeting the protection requirement, and further reduces the design cost and the development period.)

1. A test method for evaluating DAC interference rejection performance based on an IBIS model is characterized by comprising the following steps:

acquiring an IBIS circuit model of a digital-to-analog conversion DAC chip;

establishing a test circuit for testing the DAC chip under two working modes based on the DAC chip IBIS circuit model;

the test circuits in the two working modes are a test circuit in an internal reference voltage source working mode and a test circuit in an external voltage source working mode;

when the DAC chip is respectively tested by the test circuits in the two working modes, obtaining a test result with EFT signal interference and a test result without EFT signal interference;

and comparing the test result with the EFT signal interference with the test result without the EFT signal interference to obtain the anti-interference performance of the DAC chip.

2. The method of claim 1, wherein the internal reference voltage source operating mode test circuit comprises: the device comprises a DAC chip IBIS circuit model, a resistor R2, a resistor R3 and a first capacitor (C1), wherein a first pin of the DAC chip IBIS circuit model is an active low-level alarm interface, the first pin (1) is connected with one end of R3, the other end of R3 is connected with a power ground, a fourth pin (4) of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin (4) is connected with a first capacitor (C1) to ensure that the noise in the circuit is minimum in an internal reference voltage source working mode, a seventh pin (7) of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin (7) is connected with one end of R2, the other end of R2 is connected with the power ground, a tenth pin (10) of the DAC chip IBIS circuit model is a serial data output interface, and a tenth pin (10) is connected with a display instrument and used for displaying an anti-interference performance curve, the device comprises a DAC chip IBIS circuit model, and is characterized in that a twelfth pin (12) of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin (12) is connected with a voltage digital signal pulse generator with the amplitude of 3v, the period of 60ns and the duty ratio of 50%, a thirteenth pin (13) of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin (13) is externally connected with the voltage digital signal pulse generator with the amplitude of 2v, the period of 50ns and the duty ratio of 50%, a fourteenth pin (14) of the DAC chip IBIS circuit model is a serial clock input interface, and the fourteenth pin (14) is externally connected with the clock signal pulse generator with the amplitude of 1v, the period of 40ns and the duty ratio of 50%.

3. The method of claim 1, wherein the internal reference voltage source operating mode test circuit comprises: the device comprises a DAC chip IBIS circuit model, a resistor R2, a resistor R3 and a first capacitor (C1), wherein a first pin of the DAC chip IBIS circuit model is an active low-level alarm interface, the first pin (1) is connected with one end of R3, the other end of R3 is connected with a power ground, a fourth pin (4) of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin (4) is connected with a first capacitor (C1) to ensure that the noise in the circuit is minimum in an internal reference voltage source working mode, a seventh pin (7) of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin (7) is connected with one end of R2, the other end of R2 is connected with the power ground, a tenth pin (10) of the DAC chip IBIS circuit model is a serial data output interface, and a tenth pin (10) is connected with a display instrument and used for displaying an anti-interference performance curve, the twelfth pin (12) of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin (12) is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse group (EFT) generator which are connected in series, the amplitude of the voltage digital signal pulse generator and the electric fast transient pulse group (EFT) generator are 3v, the period of the voltage digital signal pulse generator is 60ns and the duty ratio of the voltage digital signal pulse generator is 50%, the thirteenth pin (13) is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse group (EFT) generator which are connected in series, the amplitude of the voltage digital signal pulse generator and the electric fast transient pulse group (EFT) generator are 2v, the period of the voltage digital signal pulse generator and the electric fast transient pulse group (EFT) generator are connected in series, the fourteenth pin (14) of the DAC chip IBIS circuit model is a serial clock input interface, the fourteenth pin (14) is externally connected with a clock signal pulse generator and an electric fast transient pulse group (EFT) generator which are connected in series, the amplitude of 1v, the period of the fourteenth pin (14) and the duty ratio of the clock signal pulse group is 50%, and setting the range of variation of the amplitude of an electric fast transient pulse train (EFT) generator to be 1kv-4kv, the initial value to be 1kv, the final value to be 4kv, and the step length to be 1 kv.

4. The method of claim 1, wherein the external voltage source operating mode test circuit comprises: the device comprises a DAC chip IBIS circuit model, a resistor R4, a resistor R1 and a direct-current voltage source, wherein a first pin of the DAC chip IBIS circuit model is an active low-level alarm interface, the first pin (1) is connected with one end of R4, the other end of R4 is connected with a power ground, a fourth pin (4) of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin (4) is externally connected with the direct-current voltage source to ensure that a circuit normally supplies power in an external voltage source working mode, a seventh pin (7) of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin (7) is connected with one end of R1, the other end of R1 is connected with the power ground, a tenth pin (10) of the DAC chip IBIS circuit model is a serial data output interface, and the tenth pin (10) is connected with a display instrument and used for displaying an anti-interference performance curve, the device comprises a DAC chip IBIS circuit model, and is characterized in that a twelfth pin (12) of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin (12) is connected with a voltage digital signal pulse generator with the amplitude of 3v, the period of 60ns and the duty ratio of 50%, a thirteenth pin (13) of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin (13) is externally connected with the voltage digital signal pulse generator with the amplitude of 2v, the period of 50ns and the duty ratio of 50%, a fourteenth pin (14) of the DAC chip IBIS circuit model is a serial clock input interface, and the fourteenth pin (14) is externally connected with the clock signal pulse generator with the amplitude of 1v, the period of 40ns and the duty ratio of 50%.

5. The method of claim 1, wherein the external voltage source operating mode test circuit comprises: the device comprises a DAC chip IBIS circuit model, a resistor R4, a resistor R1 and a direct-current voltage source, wherein a first pin of the DAC chip IBIS circuit model is an active low-level alarm interface, the first pin (1) is connected with one end of R4, the other end of R4 is connected with a power ground, a fourth pin (4) of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin (4) is externally connected with the direct-current voltage source to ensure that a circuit normally supplies power in an external voltage source working mode, a seventh pin (7) of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin (7) is connected with one end of R1, the other end of R1 is connected with the power ground, a tenth pin (10) of the DAC chip IBIS circuit model is a serial data output interface, and the tenth pin (10) is connected with a display instrument and used for displaying an anti-interference performance curve, the device comprises a DAC chip IBIS circuit model, a serial data input interface, a voltage digital signal pulse generator, a low-level effective synchronous input interface, a voltage digital signal pulse generator and an electric fast transient pulse group (EFT) generator, wherein the voltage digital signal pulse generator is connected with the twelfth pin (12) in a serial data input interface, the voltage digital signal pulse generator is connected with the twelfth pin (12) in a 3v amplitude, the cycle is 60ns and the duty ratio is 50%, the thirteenth pin (13) is connected with the voltage digital signal pulse generator and the electric fast transient pulse group (EFT) generator in series, the voltage digital signal pulse generator and the electric fast transient pulse group (EFT) generator are connected with the thirteenth pin (13) in series, the fourteenth pin (14) is connected with the clock signal pulse generator and the electric fast transient pulse group (EFT) generator in series, the amplitude of the clock signal pulse generator and the electric fast transient pulse group (EFT) generator are connected with the cycle of 40ns and the duty ratio of 50%, and the amplitude of the DAC chip IBIS circuit model is set to be in a range of 1kv-4kv, The initial value is 1kv, the final value is 4kv, and the step length is 1 kv.

Technical Field

The invention belongs to the technical field of microelectronics, and particularly relates to a test method for evaluating DAC (digital-to-analog converter) interference rejection performance based on an IBIS (intermediate bulk interference system) model.

Background

In the field of reliability of power chips, along with improvement of working frequency and integration level of integrated circuits, thinning of insulating dielectric layers and shielding dielectric layers, shortening of distances between connecting lines, and reduction of breakdown voltage and working voltage, electromagnetic anti-interference capability of the power chips can be continuously reduced. The damage or failure of the internal transistor of the integrated circuit caused by transient interferences such as electrostatic discharge (ESD) and electric fast transient pulse burst (EFT) accounts for about 20-50% of the total failure rate of the integrated circuit, and the safe and stable operation of the power chip is seriously influenced. With the use of next generation process technologies, the feature size is further reduced, the current density is increased, the voltage tolerance is reduced, and the stability problem of the integrated circuit is further aggravated due to these factors, so that the requirements on the effectiveness and stability of the protection circuit are higher and higher.

In order to obtain a high-reliability device with transient interference such as electrostatic discharge (ESD) resistance and electrical fast transient impulse burst (EFT), people study the performance of the device in a normal working area, can use a very mature simulation tool to perform computer aided design, already establishes very accurate circuit models for devices with different geometric shapes and sizes and different processes, and can use the models to design and simulate a core function circuit.

For example, xiamen excel high speed chip limited company proposed a high speed DAC test method in the applied patent document "a high speed DAC test system and method" (publication No. CN201710182502.4, application date 2017-03-24), which generates a DP-QPSK data stream by an emulation module, inputs it to a pattern generator and an arbitrary waveform generator to output a low speed digital signal and a clock signal, converts the low speed digital signal into a high speed digital signal, and converts the high speed digital signal into a high speed analog signal according to the clock signal; and then sending the high-speed analog signal to a simulation module, carrying out DP-QPSK coding modulation to obtain a DP-QPSK modulated optical signal, carrying out signal decoding and recovery through an optical receiver, comparing the recovered signal with a DP-QPSK data stream, calculating the error rate and the error vector amplitude EVM of the signal, and realizing the test and evaluation of the performance of the high-speed DAC.

However, because the method cannot specifically distinguish the electric fast transient pulse group capability of the DAC under interference and interference during the test process, the result of testing and evaluating the high-speed DAC is disadvantageous for quickly finding a chip meeting the protection requirement, reducing the design cost and shortening the development period. Meanwhile, due to the lack of commercial EFT circuit level models, the design process of most protection circuits and devices mainly depends on experience and experimental test research. For most companies, the design process of the protection circuit is an attempt and failure process: a series of candidate circuit and device structures are first designed, then manufactured, tested using new processes, and then evaluated for their protective performance. Combining and trying different dimensions and different process variations eventually finds a circuit that meets the protection requirements, which undoubtedly affects the design cost and development cycle.

One aspect that is less desirable is that existing protection circuits cannot be directly migrated to next generation processes, requiring re-fabrication and re-testing. Moreover, as pads shrink with process size, the size of the protection circuit has to shrink further, resulting in further performance degradation, and thus more money and time will be spent in I/O port re-development design.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a test method for evaluating the DAC interference resistance based on an IBIS model. The technical problem to be solved by the invention is realized by the following technical scheme:

the invention provides a test method for evaluating DAC (digital-to-analog converter) interference rejection performance based on an IBIS (intermediate bulk information system) model, which comprises the following steps:

acquiring an IBIS circuit model of a digital-to-analog conversion DAC chip;

establishing a test circuit for testing the DAC chip under two working modes based on the DAC chip IBIS circuit model;

the test circuits in the two working modes are a test circuit in an internal reference voltage source working mode and a test circuit in an external voltage source working mode;

when the DAC chip is respectively tested by the test circuits in the two working modes, obtaining a test result with EFT signal interference and a test result without EFT signal interference;

and comparing the test result with the EFT signal interference with the test result without the EFT signal interference to obtain the anti-interference performance of the DAC chip.

Optionally, the test circuit for the internal reference voltage source operating mode includes: the DAC chip IBIS circuit model comprises a DAC chip IBIS circuit model, a resistor R2, a resistor R3 and a first capacitor C1, wherein a first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin 1 is connected with one end of the R3, the other end of the R3 is connected with a power ground, a fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin 4 is connected with a first capacitor C1 to ensure that the noise in the circuit in an internal reference voltage source working mode is minimum, a seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin 7 is connected with one end of the R2, the other end of the R2 is connected with the power ground, a tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin 10 is connected with a display instrument for displaying an anti-interference curve of the DAC chip IBIS circuit model, and a twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin 12 is connected with a voltage digital signal pulse generator with an amplitude of 3v, a period of 60ns and a duty ratio of 50%, the thirteenth pin 13 of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin 13 is externally connected with the voltage digital signal pulse generator with an amplitude of 2v, a period of 50ns and a duty ratio of 50%, the fourteenth pin 14 of the DAC chip IBIS circuit model is a serial clock input interface, and the fourteenth pin 14 is externally connected with the clock signal pulse generator with an amplitude of 1v, a period of 40ns and a duty ratio of 50%.

Optionally, the test circuit for the internal reference voltage source operating mode includes: the DAC chip IBIS circuit model comprises a DAC chip IBIS circuit model, a resistor R2, a resistor R3 and a first capacitor C1, wherein a first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin 1 is connected with one end of the R3, the other end of the R3 is connected with a power ground, a fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin 4 is connected with a first capacitor C1 to ensure that the noise in the circuit in an internal reference voltage source working mode is minimum, a seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin 7 is connected with one end of the R2, the other end of the R2 is connected with the power ground, a tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin 10 is connected with a display instrument for displaying an anti-interference curve of the DAC chip IBIS circuit model, and a twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, a twelfth pin 12 is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse group EFT generator which are connected in series, wherein the amplitude of the voltage digital signal pulse generator and the electric fast transient pulse group EFT generator are 3v, the period of the voltage digital signal pulse generator is 60ns, the duty ratio of the voltage digital signal pulse generator is 50%, the amplitude of the voltage digital signal pulse generator and the electric fast transient pulse group EFT generator are connected in series, the voltage digital signal pulse generator and the electric fast transient pulse group EFT generator are 2v, the period of the voltage digital signal pulse generator is 50ns, the duty ratio of the voltage digital signal pulse generator is 50%, the fourteenth pin 14 of the DAC chip IBIS circuit model is a serial clock input interface, the amplitude of the fourteenth pin 14 is connected in series, the period of the clock signal pulse generator and the electric fast transient pulse group EFT generator are 40ns, the duty ratio of the voltage digital signal pulse generator is 50%, and the change range of the amplitude of the electric fast transient pulse group EFT generator is set to be 1kv-4kv, the initial value is 1kv, the final value is 4kv, and the step size is 1 kv.

Optionally, the test circuit for the external voltage source operating mode includes: the DAC chip IBIS circuit model comprises a DAC chip IBIS circuit model, a resistor R4, a resistor R1 and a direct-current voltage source, wherein a first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin 1 is connected with one end of R4, the other end of R4 is connected with a power ground, a fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output interface and an external voltage input interface, the fourth pin 4 is externally connected with the direct-current voltage source to ensure that a circuit normally supplies power under an external voltage source working mode, a seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin 7 is connected with one end of R1, the other end of R1 is connected with the power ground, a tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin 10 is connected with a display instrument and used for displaying an anti-interference performance curve, a twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin 12 is connected with a voltage digital signal pulse generator with an amplitude of 3v, a period of 60ns and a duty ratio of 50%, the thirteenth pin 13 of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin 13 is externally connected with the voltage digital signal pulse generator with an amplitude of 2v, a period of 50ns and a duty ratio of 50%, the fourteenth pin 14 of the DAC chip IBIS circuit model is a serial clock input interface, and the fourteenth pin 14 is externally connected with the clock signal pulse generator with an amplitude of 1v, a period of 40ns and a duty ratio of 50%.

Optionally, the test circuit for the external voltage source operating mode includes: the DAC chip IBIS circuit model comprises a DAC chip IBIS circuit model, a resistor R4, a resistor R1 and a direct-current voltage source, wherein a first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin 1 is connected with one end of R4, the other end of R4 is connected with a power ground, a fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output interface and an external voltage input interface, the fourth pin 4 is externally connected with the direct-current voltage source to ensure that a circuit normally supplies power under an external voltage source working mode, a seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin 7 is connected with one end of R1, the other end of R1 is connected with the power ground, a tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin 10 is connected with a display instrument and used for displaying an anti-interference performance curve, a twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin 12 is connected to a voltage digital signal pulse generator with an amplitude of 3v, a period of 60ns and a duty cycle of 50%, the thirteenth pin 13 of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin 13 is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse group EFT generator which are mutually connected in series, wherein the amplitude value of the voltage digital signal pulse generator is 2v, the period of the voltage digital signal pulse generator is 50ns, and the duty ratio of the voltage digital signal pulse generator is 50%, a fourteenth pin 14 of the DAC chip IBIS circuit model is a serial clock input interface, the fourteenth pin 14 is externally connected with a clock signal pulse generator and an electric fast transient pulse group EFT generator which are mutually connected in series, wherein the amplitude value of the clock signal pulse generator is 1v, the period of the clock signal pulse generator is 40ns, and the duty ratio of the clock signal pulse generator is 50%, and setting the range of variation of the amplitude of the electrical fast transient burst EFT generator to be 1kv-4kv, the initial value to be 1kv, the final value to be 4kv, and the step length to be 1 kv.

The invention provides a test method for evaluating DAC (digital-to-analog conversion) interference rejection performance based on an IBIS (intermediate bulk information system) model, which is characterized in that the IBIS circuit model of a DAC chip is obtained; establishing a test circuit for testing the DAC chip under two working modes based on the DAC chip IBIS circuit model; when the DAC chip is respectively tested by the test circuits in the two working modes, obtaining a test result with EFT signal interference and a test result without EFT signal interference; and comparing the test result with the EFT signal interference with the test result without the EFT signal interference to obtain the anti-interference performance of the DAC chip. Therefore, the invention can effectively test the capability of the DAC chip of AD5761R/AD5721R in resisting the electric fast transient pulse group, is beneficial to quickly finding the chip meeting the protection requirement, and further reduces the design cost and the development period.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

FIG. 1 is a flowchart of a testing method for evaluating DAC immunity performance based on IBIS model according to an embodiment of the present invention;

FIG. 2 is a circuit model diagram of the internal reference voltage source operating mode established by the IBIS model based on the model AD5761R/AD5721R DAC chip;

FIG. 3 is a schematic diagram of the circuit of the present invention with EFT added to the signal input under the operating mode of the internal reference voltage source;

FIG. 4 is a circuit model diagram of the present invention under an external voltage source operating mode established based on the IBIS model of the DAC chip model AD5761R/AD 5721R;

FIG. 5 is a schematic diagram of the signal input terminal with EFT interference added thereto in the external voltage source operating mode according to the present invention;

FIG. 6 is a waveform of the output of the serial data output pin in the internal reference voltage source operating mode according to the present invention;

FIG. 7 is a waveform diagram of the output of the serial data output pin in the external voltage source operation mode according to the present invention;

FIG. 8 is a waveform of serial input data without EFT interference and with inconsistent period and amplitude in accordance with the present invention;

FIG. 9 is a waveform diagram of the serial data input terminal when EFT interference is applied to the signal input terminal in the internal reference voltage source operating mode according to the present invention;

FIG. 10 is a waveform diagram of the serial data output port when EFT interference is applied to the signal input port in the internal reference voltage source operating mode according to the present invention;

FIG. 11 is a waveform diagram of a serial data input terminal with EFT interference applied to the signal input terminal in the external voltage source operating mode according to the present invention;

FIG. 12 is a waveform diagram of the serial data output terminal when EFT interference is applied to the signal input terminal in the external voltage source operating mode according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

As shown in fig. 1, the test method for evaluating DAC immunity performance based on the IBIS model provided by the present invention includes:

s1, acquiring an IBIS circuit model of the digital-to-analog conversion DAC chip;

s2, establishing a test circuit for testing the DAC chip in two working modes based on the DAC chip IBIS circuit model;

the test circuits in the two working modes are a test circuit in an internal reference voltage source working mode and a test circuit in an external voltage source working mode;

s3, when the DAC chip is tested by the test circuit under the two working modes, the test result with EFT signal interference and the test result without EFT signal interference are obtained;

and S4, comparing the test result with the EFT signal interference with the test result without the EFT signal interference to obtain the anti-interference performance of the DAC chip.

It can be understood that in the IBIS circuit model, the IBIS model of the digital-to-analog conversion DAC chip with the model number of AD5761R/AD5721R is called into ansys, and the power supply mode of each port of the IBIS model is set to be internal power supply internal under the internal reference voltage source working mode. And setting each port of the IBIS model to be in an external power supply mode external in the external voltage source working mode.

The invention provides a test method for evaluating DAC (digital-to-analog conversion) interference rejection performance based on an IBIS (intermediate bulk information system) model, which comprises the steps of obtaining an IBIS circuit model of a DAC chip; establishing a test circuit for testing the DAC chip under two working modes based on the DAC chip IBIS circuit model; when the DAC chip is tested by the test circuit under two working modes, obtaining a test result with EFT signal interference and a test result without EFT signal interference; and comparing the test result with the EFT signal interference with the test result without the EFT signal interference to obtain the anti-interference performance of the DAC chip. Therefore, the invention can effectively test the capability of the DAC chip of AD5761R/AD5721R in resisting the electric fast transient pulse group, is beneficial to quickly finding the chip meeting the protection requirement, and further reduces the design cost and the development period.

Example two

As an alternative embodiment of the present invention, as shown in fig. 2, the test circuit for the internal reference voltage source operation mode includes: the DAC chip IBIS circuit model comprises a DAC chip IBIS circuit model, a resistor R2, a resistor R3 and a first capacitor C1, wherein a first pin of the DAC chip IBIS circuit model is an effective low-level alarm interface, the first pin 1 is connected with one end of the R3, the other end of the R3 is connected with a power ground, a fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin 4 is connected with a first capacitor C1 to ensure the minimum noise in the circuit in an internal reference voltage source working mode, a seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin 7 is connected with one end of the R2, the other end of the R2 is connected with the power ground, a tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin 10 is connected with a display instrument for displaying an anti-interference curve of the DAC chip IBIS circuit model, and a twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin 12 is connected with a voltage digital signal pulse generator with an amplitude of 3v, a period of 60ns and a duty ratio of 50%, the thirteenth pin 13 of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin 13 is externally connected with the voltage digital signal pulse generator with an amplitude of 2v, a period of 50ns and a duty ratio of 50%, the fourteenth pin 14 of the DAC chip IBIS circuit model is a serial clock input interface, and the fourteenth pin 14 is externally connected with the clock signal pulse generator with an amplitude of 1v, a period of 40ns and a duty ratio of 50%.

It can be understood that the test circuit of the internal reference voltage source working mode can be built according to the following steps:

step 1, calling an IBIS model of an AD5761R/AD5721R digital-to-analog conversion DAC chip into ansys, and setting a power supply mode of each port of the model as internal power supply internal.

And step 2, the pin 1 is a low-level effective alarm interface, and the pin is externally connected with a resistor of 10 omega in the connection mode of the circuit.

And step 3, a pin 4 is an interface for outputting an internal reference voltage and inputting an external voltage, and the pin is externally connected with a capacitor of 10nF in the connection mode of the circuit so as to ensure that the noise in the circuit is minimum in the working mode of the internal reference voltage source.

And step 4, the pin 7 is an analog output voltage interface of the DAC, and the pin is externally connected with a resistor of 10 omega in the connection mode of the circuit.

And step 5, the pin 10 is a serial data output interface, and the pin is externally connected with a 10 omega resistor in the connection mode of the circuit.

And 6, the pin 12 is a serial data input interface, and in the connection mode of the circuit, the pin is externally connected with a voltage digital signal pulse generator with the amplitude of 3v, the period of 60ns and the duty ratio of 50%.

And 7, a pin 13 is a low-level effective synchronous input interface, and in the connection mode of the circuit, the pin is externally connected with a voltage digital signal pulse generator with the amplitude of 2v, the period of 50ns and the duty ratio of 50%.

And step 8, the pin 14 is a serial clock input interface, and in the connection mode of the circuit, the pin is externally connected with a clock signal pulse generator with the amplitude of 1v, the period of 40ns and the duty ratio of 50%.

EXAMPLE III

As an alternative embodiment of the present invention, as shown in fig. 3, the test circuit for the internal reference voltage source operation mode includes: the DAC chip IBIS circuit model comprises a DAC chip IBIS circuit model, a resistor R2, a resistor R3 and a first capacitor C1, wherein a first pin of the DAC chip IBIS circuit model is an effective low-level alarm interface, the first pin 1 is connected with one end of the R3, the other end of the R3 is connected with a power ground, a fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output and external voltage input interface, the fourth pin 4 is connected with a first capacitor C1 to ensure the minimum noise in the circuit in an internal reference voltage source working mode, a seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin 7 is connected with one end of the R2, the other end of the R2 is connected with the power ground, a tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin 10 is connected with a display instrument for displaying an anti-interference curve of the DAC chip IBIS circuit model, and a twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, a twelfth pin 12 is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse group (EFT) generator which are connected in series, wherein the amplitude of the voltage digital signal pulse generator and the period of the voltage digital signal pulse generator are 3v, the period of the voltage digital signal pulse generator are 60ns, the duty ratio of the voltage digital signal pulse generator is 50%, the voltage digital signal pulse generator and the electric fast transient pulse group (EFT) generator are connected in series, the thirteenth pin 13 is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse group (EFT) generator which are connected in series, the amplitude of the voltage digital signal pulse generator and the electric fast transient pulse group (EFT) generator are 2v, the period of the voltage digital signal pulse generator and the duty ratio of the 50%, the fourteenth pin 14 is connected with a serial clock input interface, the fourteenth pin 14 is externally connected with a clock signal pulse generator and an electric fast transient pulse group (EFT) generator which are connected in series, the amplitude of the clock signal pulse generator and the electric fast transient pulse group (EFT) generator are 1kv-4kv, the duty ratio of the electric fast transient pulse group (EFT) generator is set, The initial value is 1kv, the final value is 4kv, and the step length is 1 kv.

It can be understood that the test circuit of the signal input end plus the EFT interference circuit under the working mode of the internal reference voltage source can be set up according to the following steps:

step 1, based on the schematic diagram of fig. 2 that the signal input end has no EFT interference in the internal reference voltage source working mode, adding an interference excitation signal to the input signal port;

and 2, a pin 12 is a serial data input interface, and in the connection mode of the circuit, the pin is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse train (EFT) generator which are connected in series, wherein the amplitude of the voltage digital signal pulse generator is 3v, the period of the voltage digital signal pulse generator is 60ns, and the duty ratio of the voltage digital signal pulse generator is 50%.

And step 3, a pin 13 is a low-level effective synchronous input interface, and in the connection mode of the circuit, the pin is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse train (EFT) generator which are connected in series, wherein the amplitude of the voltage digital signal pulse generator is 2v, the period of the voltage digital signal pulse generator is 50ns, and the duty ratio of the voltage digital signal pulse generator is 50%.

And step 4, a pin 14 is a serial clock input interface, and in the connection mode of the circuit, the pin is externally connected with a clock signal pulse generator and an electric fast transient pulse train (EFT) generator which are connected in series, wherein the amplitude of the clock signal pulse generator is 1v, the period of the clock signal pulse generator is 40ns, and the duty ratio of the clock signal pulse generator is 50%.

And 5, aiming at the simulation of an electric fast transient pulse train (EFT) generator, setting the change range of the amplitude value to be 1kv-4kv, the initial value start to be 1kv, the final value stop to be 4kv and the step length step to be 1 kv.

This embodiment is based on the model is the IBIS model of AD5761R/AD5721R digital-to-analog conversion DAC chip, the circuit model under the internal reference voltage source mode has been built, EFT interference signal superposes at the input port of signal after that, finally through comparing the output result that observes under having/not having EFT interference signal two kinds of circumstances, thereby to DAC chip anti-electric fast transient pulse crowd ability under the internal reference voltage source mode have appraisal, be favorable to finding the chip that satisfies the protection demand fast, and then reduce design cost and development cycle.

Example four

As an alternative embodiment of the present invention, as shown in fig. 4, the test circuit for the external voltage source operation mode includes: the DAC chip IBIS circuit model comprises a DAC chip IBIS circuit model, a resistor R4, a resistor R1 and a direct-current voltage source, wherein a first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin 1 is connected with one end of R4, the other end of R4 is connected with a power ground, a fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output interface and an external voltage input interface, the fourth pin 4 is externally connected with the direct-current voltage source to ensure that a circuit normally supplies power under an external voltage source working mode, a seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin 7 is connected with one end of R1, the other end of R1 is connected with the power ground, a tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin 10 is connected with a display instrument and used for displaying an anti-interference performance curve, a twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, the twelfth pin 12 is connected with a voltage digital signal pulse generator with an amplitude of 3v, a period of 60ns and a duty ratio of 50%, the thirteenth pin 13 of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin 13 is externally connected with the voltage digital signal pulse generator with an amplitude of 2v, a period of 50ns and a duty ratio of 50%, the fourteenth pin 14 of the DAC chip IBIS circuit model is a serial clock input interface, and the fourteenth pin 14 is externally connected with the clock signal pulse generator with an amplitude of 1v, a period of 40ns and a duty ratio of 50%.

It will be appreciated that the test circuit for the external voltage source mode of operation may be set up as follows:

step 1, calling an IBIS model of an AD5761R/AD5721R digital-to-analog conversion DAC chip into ansys, and setting a power supply mode of each port of the model as external power supply.

And step 2, the pin 1 is a low-level effective alarm interface, and the pin is externally connected with a resistor of 10 omega in the connection mode of the circuit.

And step 3, a pin 4 is an internal reference voltage output interface and an external voltage input interface, and the pin is externally connected with a direct-current voltage source with the amplitude of 2.5v in the connection mode of the circuit so as to ensure that the circuit normally supplies power in an external voltage source working mode.

And step 4, the pin 7 is an analog output voltage interface of the DAC, and the pin is externally connected with a resistor of 10 omega in the connection mode of the circuit.

And step 5, the pin 10 is a serial data output interface, and the pin is externally connected with a 10 omega resistor in the connection mode of the circuit.

And 6, the pin 12 is a serial data input interface, and in the connection mode of the circuit, the pin is externally connected with a voltage digital signal pulse generator with the amplitude of 3v, the period of 60ns and the duty ratio of 50%.

And 7, a pin 13 is a low-level effective synchronous input interface, and in the connection mode of the circuit, the pin is externally connected with a voltage digital signal pulse generator with the amplitude of 2v, the period of 50ns and the duty ratio of 50%.

And step 8, the pin 14 is a serial clock input interface, and in the connection mode of the circuit, the pin is externally connected with a clock signal pulse generator with the amplitude of 1v, the period of 40ns and the duty ratio of 50%.

EXAMPLE five

As an alternative embodiment of the present invention, as shown in fig. 5, the test circuit for the external voltage source operation mode includes: the DAC chip IBIS circuit model comprises a DAC chip IBIS circuit model, a resistor R4, a resistor R1 and a direct-current voltage source, wherein a first pin of the DAC chip IBIS circuit model is a low-level effective alarm interface, the first pin 1 is connected with one end of R4, the other end of R4 is connected with a power ground, a fourth pin 4 of the DAC chip IBIS circuit model is an internal reference voltage output interface and an external voltage input interface, the fourth pin 4 is externally connected with the direct-current voltage source to ensure that a circuit normally supplies power under an external voltage source working mode, a seventh pin 7 of the DAC chip IBIS circuit model is an analog output voltage interface, the seventh pin 7 is connected with one end of R1, the other end of R1 is connected with the power ground, a tenth pin 10 of the DAC chip IBIS circuit model is a serial data output interface, the tenth pin 10 is connected with a display instrument and used for displaying an anti-interference performance curve, a twelfth pin 12 of the DAC chip IBIS circuit model is a serial data input interface, a twelfth pin 12 is connected with a voltage digital signal pulse generator with an amplitude of 3v, a period of 60ns and a duty ratio of 50%, a thirteenth pin 13 of the DAC chip IBIS circuit model is a low-level effective synchronous input interface, the thirteenth pin 13 is externally connected with the voltage digital signal pulse generator and an electric fast transient pulse group (EFT) generator which are connected in series, the amplitude of the voltage digital signal pulse generator and the electric fast transient pulse group are 2v, the period of the voltage digital signal pulse generator and the electric fast transient pulse group are 50%, the fourteenth pin 14 of the DAC chip IBIS circuit model is a serial clock input interface, the fourteenth pin 14 is externally connected with the clock signal pulse generator and the electric fast transient pulse group (EFT) generator which are connected in series, the amplitude of the clock signal pulse generator and the electric fast transient pulse group (EFT) generator are 1 v-4kv, the initial value of 1kv, the final value of 4kv and the electric fast transient pulse group (EFT) generator are set, and the amplitude of the electric fast transient pulse group (EFT) generator is changed in a range of 1kv-4kv, The step size is 1 kv.

It can be understood that the test circuit of the signal input end plus the EFT interference circuit under the external voltage source working mode can be set up according to the following steps:

step 1, based on the schematic diagram of fig. 4 that the signal input end has no EFT interference in the external voltage source working mode, adding an interference excitation signal to the input signal port;

and 2, a pin 12 is a serial data input interface, and in the connection mode of the circuit, the pin is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse train (EFT) generator which are connected in series, wherein the amplitude of the voltage digital signal pulse generator is 3v, the period of the voltage digital signal pulse generator is 60ns, and the duty ratio of the voltage digital signal pulse generator is 50%.

And step 3, a pin 13 is a low-level effective synchronous input interface, and in the connection mode of the circuit, the pin is externally connected with a voltage digital signal pulse generator and an electric fast transient pulse train (EFT) generator which are connected in series, wherein the amplitude of the voltage digital signal pulse generator is 2v, the period of the voltage digital signal pulse generator is 50ns, and the duty ratio of the voltage digital signal pulse generator is 50%.

And step 4, a pin 14 is a serial clock input interface, and in the connection mode of the circuit, the pin is externally connected with a clock signal pulse generator and an electric fast transient pulse train (EFT) generator which are connected in series, wherein the amplitude of the clock signal pulse generator is 1v, the period of the clock signal pulse generator is 40ns, and the duty ratio of the clock signal pulse generator is 50%.

And 5, aiming at the simulation of an electric fast transient pulse train (EFT) generator, setting the change range of the amplitude value to be 1kv-4kv, the initial value start to be 1kv, the final value stop to be 4kv and the step length step to be 1 kv.

The embodiment is based on the IBIS model of which the model is AD5761R/AD5721R digital-to-analog conversion DAC chip, a circuit model under an external voltage source working mode is built, then EFT interference signals are superposed on input ports of the signals, and finally output results under two conditions of the presence/absence of the EFT interference signals are observed through comparison, so that the capability of the DAC chip for resisting electric fast transient pulse groups under the external voltage source working mode is evaluated, the fast finding of the chip meeting the protection requirement is facilitated, and the design cost and the development period are reduced.

The following presents the interference performance parameters tested by the testing method provided by the invention by a simulation test, and explains the beneficial effects of the invention by comparison and analysis.

Simulation 1, the effect diagram is shown in fig. 6, and fig. 6 is an output waveform of a serial data output pin in the internal reference voltage source operation mode.

Simulation 2 shows the effect of fig. 7, and fig. 7 shows the output waveform of the serial data output pin in the external voltage source operation mode.

Simulation 3, the effect diagram is shown in fig. 8, and fig. 8 is a waveform diagram of serial input data when there is no EFT interference and the period and the amplitude are not consistent.

Simulation 4 shows the effect diagram of fig. 9, where fig. 9 is the waveform of the serial data input terminal when EFT interference is applied to the signal input terminal in the internal reference voltage source operation mode.

Simulation 5 shows the effect diagram of fig. 10, where fig. 10 shows the waveform of the serial data output terminal when EFT interference is applied to the signal input terminal in the internal reference voltage source operation mode.

Simulation 6 shows the effect of fig. 11, where fig. 11 shows the waveform of the serial data input terminal when EFT interference is applied to the signal input terminal in the external voltage source operation mode.

Simulation 7 shows the effect of fig. 12, where fig. 12 shows the waveform of the serial data output terminal when EFT interference is applied to the signal input terminal in the external voltage source operation mode.

According to the above effect graphs, the input and output conditions of the DAC in the internal reference voltage source power supply operation mode are compared, wherein the input comparison graphs are fig. 8 and 9, and the output comparison graphs are fig. 6 and 10. From the comparison graph, it can be seen that in the case that the EFT interference signal is added to the input terminal, the input signal in the circuit is affected, but the output signal is not affected, which indicates that the circuit has good EFT interference resistance in the internal reference voltage source power supply mode.

Comparing the input and output conditions of the DAC under the external voltage source power supply working mode and with/without EFT interference, wherein the input comparison graph is shown in the figure 8 and the figure 11, and the output comparison graph is shown in the figure 7 and the figure 12. From the comparison graph, it can be seen that when the EFT interference signal is added to the input terminal, both the input and output signals in the circuit are affected, which indicates that the circuit has poor performance against the EFT interference in the external voltage source power supply mode.

Therefore, the circuit model under two working modes of an internal reference voltage source and an external voltage source is built based on the IBIS model of the AD5761R/AD5721R digital-to-analog conversion DAC chip, EFT interference signals are superposed on the input port of the signals, and finally the performance evaluation of the anti-electric fast transient pulse group capability of the DAC chip can be realized by comparing and observing the output results under two conditions of the presence/absence of the EFT interference signals, so that the chip meeting the protection requirement can be found quickly, and the design cost and the development period are reduced.

It should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.

While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.