阅读说明：本技术 空中下载技术升级方法、系统及计算机可读存储介质 (Method and system for upgrading over-the-air technology and computer readable storage medium ) 是由 郑凯 黄泽洋 郑龙 李冬 姜豪 刘风雷 于 2021-08-11 设计创作，主要内容包括：本申请提供一种空中下载技术升级方法、系统及计算机可读存储介质,包括：通信模组接收服务器发送的升级固件,并根据各芯片的升级顺序,确定待升级的目标芯片；通信模组向第一芯片发送开始升级指令,以第一芯片为起始,各芯片依次向在后芯片发送开始升级指令,若接收到开始升级指令的芯片为目标芯片,则目标芯片将芯片模式调整为升级模式,目标芯片之外的其它芯片将芯片模式调整为透传模式或休眠模式；通信模组向第一芯片发送升级固件；以第一芯片为起始,各芯片依次接收升级固件,并根据当前各自的芯片模式执行升级操作或者数据透传。通过上述步骤,能够避免多芯片升级中,一侧芯片出现错误影响其它芯片升级,提高了设备进行OTA升级的可靠性。(The application provides an over-the-air technology upgrading method, a system and a computer readable storage medium, comprising: the communication module receives the upgrading firmware sent by the server and determines a target chip to be upgraded according to the upgrading sequence of each chip; the communication module sends an upgrade starting instruction to a first chip, the first chip is used as a starting point, each chip sends the upgrade starting instruction to a subsequent chip in sequence, if the chip receiving the upgrade starting instruction is a target chip, the target chip adjusts the mode of the chip to be an upgrade mode, and other chips except the target chip adjust the mode of the chip to be a transparent transmission mode or a sleep mode; the communication module sends upgrading firmware to the first chip; and starting with the first chip, sequentially receiving the upgrading firmware by each chip, and executing upgrading operation or data transparent transmission according to the current respective chip mode. Through the steps, the situation that other chips are upgraded due to the fact that errors occur in one side of the chips in the multi-chip upgrading process can be avoided, and the reliability of OTA upgrading of the equipment is improved.)

1. An over-the-air technology upgrading method is applied to an over-the-air technology upgrading system, the upgrading system comprises electronic equipment to be upgraded and a communication module, the electronic equipment comprises a plurality of chips, a first chip in each chip is connected with the communication module, and the method comprises the following steps:

the communication module receives upgrade firmware sent by a server and determines a target chip to be upgraded currently according to the upgrade sequence of each chip, wherein the upgrade sequence of each chip is determined according to the arrangement sequence of each chip;

the communication module sends an upgrade starting instruction to the first chip, wherein the upgrade starting instruction comprises an identifier of the target chip;

starting with the first chip, each chip sequentially sends the upgrading starting instruction to the following chips, if the chip receiving the upgrading starting instruction is the target chip, the current chip mode of the target chip is adjusted to be the upgrading mode, and the other chips except the target chip adjust the respective chip modes to be the transparent transmission mode or the sleep mode;

the communication module sends the upgrade firmware to the first chip;

and starting with the first chip, sequentially receiving the upgrading firmware by each chip, and executing upgrading operation or data transparent transmission according to the current respective chip mode.

2. The method of claim 1, wherein the other chips than the target chip adjust their respective chip modes to a pass-through mode or a sleep mode, comprising:

and if the upgrading state of a second chip in the other chips is upgraded, the second chip adjusts the chip mode to be a sleep mode, wherein the second chip is any one of the other chips.

3. The method of claim 1, wherein the other chips than the target chip adjust their respective chip modes to a pass-through mode or a sleep mode, comprising:

and if the upgrading state of a third chip in the other chips is not upgraded, the third chip adjusts the chip mode to be a transparent transmission mode, wherein the third chip is any one of the other chips.

4. The method of claim 1, wherein the performing of the upgrade operation or the data pass-through by each chip according to the current respective chip mode comprises:

the target chip uses the upgrading firmware to execute upgrading operation in the upgrading mode;

and each chip in the transparent transmission mode sends the upgrade firmware to the subsequent chip connected with the upgrade firmware.

5. The method of claim 4, further comprising:

and if the target chip finishes the upgrading operation, the target chip exits the upgrading mode and sends upgrading finishing responses to other chips except the target chip.

6. The method of claim 4, further comprising:

and after receiving the upgrade completion response, the third chip in the other chips adjusts the current chip mode to an initial state.

7. The method according to any one of claims 1 to 6, wherein the receiving, by the communication module, the upgraded firmware sent by the server comprises:

the communication module sends an upgrading preparation instruction to the first chip;

the first chip determines whether each chip meets a preset upgrading condition or not according to the upgrading preparation instruction, and if yes, an upgrading preparation completion response is sent to the communication module;

and the communication module reads the upgrading firmware from the server according to the upgrading preparation completion response.

8. The method according to any one of claims 1 to 6, wherein before determining a target chip to be upgraded currently according to an upgrade order of each chip, the method further comprises:

and reading the upgrading sequence of each chip from the server, wherein the upgrading sequence of each chip is obtained by the user through setting on the server in advance according to the arrangement sequence of each chip.

9. An over-the-air technology upgrade system, the system comprising:

electronic equipment and a communication module to be upgraded, wherein the electronic equipment comprises a plurality of chips, a first chip in each chip is connected with the communication module, and the electronic equipment and each chip in the electronic equipment respectively execute the steps of the over-the-air technology upgrading method according to any one of claims 1 to 8.

10. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, performs the steps of the over-the-air technology upgrade method according to any one of claims 1-8.

Technical Field

The present application relates to the field of chip technologies, and in particular, to an over-the-air technology upgrading method, system, and computer-readable storage medium.

Background

With the continuous development of computer communication technology and semiconductor technology, various electronic devices become more and more complex, and these electronic devices often integrate multiple chips, and generally need firmware upgrade to repair the problems and add new functions. In the prior art, an Over-the-Air Technology (OTA for short) is generally used to upgrade firmware, where OTA is a mode that can transmit and upgrade firmware through an Over-the-Air wireless network, that is, OTA is a mode of remote upgrade, specifically, a chip on an OTA remote upgrade device is used to download upgrade firmware from a server through a communication module and transmit the upgraded firmware to the chip, so as to complete a chip upgrade process.

In the prior art, when the equipment integrating a plurality of chips simultaneously upgrades a plurality of chips, the upgrading sequence of each chip is not formulated, and after errors occur in the upgrading process of one side chip, the upgrading of other side chips can be influenced, so that the upgraded equipment is abnormal.

Disclosure of Invention

In view of the above, an object of the present invention is to provide an over-the-air technology upgrading method, system and computer readable storage medium, so as to solve the problem in the prior art that when a device integrating multiple chips upgrades multiple chips simultaneously, the device is abnormal due to the disorder of chip upgrade.

In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:

in a first aspect, an embodiment of the present application provides an over-the-air technology upgrading method, which is applied to an over-the-air technology upgrading system, where the upgrading system includes an electronic device to be upgraded and a communication module, the electronic device includes a plurality of chips, a first chip of each chip is connected to the communication module, and the method includes:

the communication module receives upgrade firmware sent by a server and determines a target chip to be upgraded currently according to the upgrade sequence of each chip, wherein the upgrade sequence of each chip is determined according to the arrangement sequence of each chip;

the communication module sends an upgrade starting instruction to the first chip, wherein the upgrade starting instruction comprises an identifier of the target chip;

starting with the first chip, each chip sequentially sends the upgrading starting instruction to the following chips, if the chip receiving the upgrading starting instruction is the target chip, the current chip mode of the target chip is adjusted to be the upgrading mode, and the other chips except the target chip adjust the respective chip modes to be the transparent transmission mode or the sleep mode;

the communication module sends the upgrade firmware to the first chip;

and starting with the first chip, sequentially receiving the upgrading firmware by each chip, and executing upgrading operation or data transparent transmission according to the current respective chip mode.

As a possible implementation manner, the adjusting of the respective chip mode to the transparent transmission mode or the sleep mode by the other chips except the target chip includes:

and if the upgrading state of a second chip in the other chips is upgraded, the second chip adjusts the chip mode to be a sleep mode, wherein the second chip is any one of the other chips.

As a possible implementation manner, the adjusting of the respective chip mode to the transparent transmission mode or the sleep mode by the other chips except the target chip includes:

and if the upgrading state of a third chip in the other chips is not upgraded, the third chip adjusts the chip mode to be a transparent transmission mode, wherein the third chip is any one of the other chips.

As a possible implementation manner, the performing, by each chip, an upgrade operation or data transparent transmission according to a current respective chip mode includes:

the target chip uses the upgrading firmware to execute upgrading operation in the upgrading mode;

and each chip in the transparent transmission mode sends the upgrade firmware to the subsequent chip connected with the upgrade firmware.

As a possible implementation, the method further includes:

and if the target chip finishes the upgrading operation, the target chip exits the upgrading mode and sends upgrading finishing responses to other chips except the target chip.

As a possible implementation, the method further includes:

and after receiving the upgrade completion response, the third chip in the other chips adjusts the current chip mode to an initial state.

As a possible implementation manner, the receiving, by the communication module, the upgrade firmware sent by the server includes:

the communication module sends an upgrading preparation instruction to the first chip;

the first chip determines whether each chip meets a preset upgrading condition or not according to the upgrading preparation instruction, and if yes, an upgrading preparation completion response is sent to the communication module;

and the communication module reads the upgrading firmware from the server according to the upgrading preparation completion response.

As a possible implementation manner, before determining a target chip to be upgraded currently according to an upgrade order of each chip, the method further includes:

and reading the upgrading sequence of each chip from the server, wherein the upgrading sequence of each chip is obtained by the user through setting on the server in advance according to the arrangement sequence of each chip.

In a second aspect, an embodiment of the present application further provides an over-the-air technology upgrading system, where the system includes:

the method comprises the steps of obtaining a plurality of chips, connecting a first chip of each chip with a communication module, and executing the steps of the over-the-air technology upgrading method according to the first aspect.

In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the over-the-air technology upgrading method according to the first aspect are performed.

The beneficial effect of this application is:

according to the over-the-air technology upgrading method, system and computer readable storage medium provided by the embodiment of the application, the communication module receives upgrading firmware sent by the server, and determines the target chip to be upgraded currently according to the upgrading sequence of each chip, wherein the upgrading sequence of each chip is determined according to the arrangement sequence of each chip; the communication module sends an upgrading starting instruction to the first chip, wherein the upgrading starting instruction comprises an identifier of a target chip; starting with a first chip, sequentially sending an upgrading starting instruction to a subsequent chip by each chip, if the chip receiving the upgrading starting instruction is a target chip, adjusting the current chip mode of the target chip to be an upgrading mode by the target chip, and adjusting the respective chip modes of other chips except the target chip to be a transparent transmission mode or a sleep mode by the other chips except the target chip; the communication module sends upgrading firmware to the first chip; and starting with the first chip, sequentially receiving the upgrading firmware by each chip, and executing upgrading operation or data transparent transmission according to the current respective chip mode. In the above steps, since the upgrading sequence of each chip is preset according to the arrangement sequence of each chip before upgrading, the chips can be upgraded according to the preset upgrading sequence in the upgrading process, and each chip can enter the corresponding chip mode according to the state of the chip in the upgrading process, the upgrading of other side chips can be influenced after the chip on one side has errors in the upgrading process, and further the problem that the upgraded equipment is abnormal is solved, the reliability of OTA upgrading of the electronic equipment is improved, and the accuracy and the efficiency of firmware upgrading of the electronic equipment are improved.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic structural diagram of an OTA upgrade system according to an embodiment of the present disclosure;

fig. 2 is a schematic flowchart of an OTA upgrading method according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of another OTA upgrading system provided in an embodiment of the present application;

fig. 4 is a schematic flowchart of another OTA upgrading method according to an embodiment of the present application;

fig. 5 is a schematic flowchart of another OTA upgrading method according to an embodiment of the present application;

fig. 6 is a schematic flowchart of another OTA upgrading method according to an embodiment of the present application;

fig. 7 is a schematic flowchart of another OTA upgrading method according to an embodiment of the present application;

fig. 8 is a flowchart illustrating another OTA upgrading method according to an embodiment of the present application.

Icon: 101-an electronic device; 102-a communication module; 103-a plurality of chips; 104-first chip.

Detailed Description

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it should be understood that the drawings in the present application are for illustrative and descriptive purposes only and are not used to limit the scope of protection of the present application. Additionally, it should be understood that the schematic drawings are not necessarily drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be performed out of order, and steps without logical context may be performed in reverse order or simultaneously. One skilled in the art, under the guidance of this application, may add one or more other operations to, or remove one or more operations from, the flowchart.

In addition, the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that in the embodiments of the present application, the term "comprising" is used to indicate the presence of the features stated hereinafter, but does not exclude the addition of further features.

Along with OTA constantly develops and matures, many electronic equipment need carry out firmware upgrade when repairing the problem that exists, perhaps need increase new function, adopt OTA remote upgrade's mode usually, and is concrete, and equipment passes through communication module, for example WIFI module, downloads the upgrading firmware from the server to the chip in will upgrading firmware transmission equipment, in order to accomplish the upgrading of chip.

The existing electronic equipment is often integrated with a plurality of chips in a system, and in the prior art, when the equipment integrating the plurality of chips simultaneously upgrades the plurality of chips, the upgrading sequence is not customized, so that the problem that the upgrading of the chip on the lower side can be influenced after the chip on one side is upgraded is solved.

Generally, in an electronic device, a chip closer to a communication module may be referred to as a near-end chip, and a chip farther from the communication module may be referred to as a far-end chip. In the upgrading process, if the near-end chip is upgraded first and then the far-end chip is upgraded, the problem that if the near-end chip has an error in the upgrading process, the remaining chips cannot be upgraded normally may occur.

Suppose that 3 chips are arranged in a certain electronic device, namely chip 1, chip 2 and chip 3, and chip 1 is connected to a communication module, chip 2 is connected to chip 1, and chip 3 is connected to chip 2, then chip 1 can be called a near-end chip, and chip 2 and chip 3 are called a far-end chip. If the near-end chip 1 is upgraded first, and then the far-end chip 2 and the chip 3 are upgraded, if a program of the chip 1 is wrong in the upgrading process, the chip 1 cannot normally receive and process upgrading firmware data sent by the communication module subsequently, and then the chip 2 and the chip 3 cannot be normally upgraded.

In view of the above problems existing in the OTA upgrading process of the electronic equipment integrated with multiple chips, the application provides an OTA upgrading method based on which the upgrading sequence of the chips is preset before OTA upgrading, and in the upgrading process, each chip can enter a corresponding chip mode according to the state of the chip, so that the problem that if an error exists in the upgrading process of one side of the chip, the next side of the chip cannot be upgraded normally is solved.

The OTA upgrading method provided by the embodiment of the application is applied to an OTA upgrading system, and the OTA upgrading system will be explained first.

Please refer to fig. 1, which is a schematic structural diagram of an OTA upgrade system according to an embodiment of the present application, and as shown in fig. 1, the OTA upgrade system may include: the electronic device 101 to be upgraded and the communication module 102 may include a plurality of chips 103 in the electronic device 101 to be upgraded, and a first chip 104 of the plurality of chips is directly connected to the communication module 102. It should be noted that the number of chips in the plurality of chips 103 in fig. 1 is merely illustrative, and the embodiment of the present application is not limited in particular.

For example, in a scenario of upgrading a chip in an electronic device using an OTA, a data interaction process between the electronic device 101, the communication module 102, and the server may be: a user operates the electronic device 101 to initiate an upgrade request instruction, the electronic device 101 sends the upgrade request instruction to a server, the server sends the upgrade instruction to the communication module 102 after receiving the upgrade instruction, the communication module 102 downloads upgrade firmware from the server, the communication module 102 sends the upgrade firmware downloaded from the server to the plurality of chips 103, the plurality of chips 103 complete the upgrade of each chip after receiving the upgrade firmware, the plurality of chips 103 return an upgrade complete response to the communication module 102 after completing the upgrade of the chips, the communication module 102 returns an upgrade complete response to the server after receiving the upgrade complete response, the server returns an upgrade complete response to the electronic device 101 after receiving the upgrade complete response, and the electronic device 101 informs the upgrade complete response to the user.

Specifically, the interaction between the electronic device 101 and the server and the interaction between the communication module 102 and the server are completed through a Wireless Network, where the Wireless Network is a Network implemented by using a Wireless communication technology, and according to different Network coverage, transmission rate and usage, the Wireless Network may be divided into a Wireless Wide Area Network (WWAN), a Wireless Metropolitan Area Network (WMAN), a Wireless Local Area Network (WLAN), a Wireless Personal Area Network (WPAN), a Wireless Body Area Network (WBAN), and the like, or any combination thereof, and the Wireless networks are used to provide communication links between the electronic device 101 and the server, and between the communication module 102 and the server.

In some embodiments, the servers may be implemented on a cloud platform, which may include, by way of example only, private clouds, public clouds, hybrid clouds, community clouds (community clouds), distributed clouds, inter-clouds (inter-clouds), multi-clouds (multi-clouds), and the like, or any combination thereof.

For simplicity, in the following method embodiments, the description will be made using "device" when referring to the electronic device 101, using "communication module" when referring to the communication module 102, using "multiple chips" when referring to the multiple chips 103, and using "first chip" when referring to the first chip 104.

After the OTA upgrade system provided by the embodiment of the present application is described, the following embodiment will explain in detail the OTA upgrade method provided by the embodiment of the present application with reference to the accompanying drawings.

Please refer to fig. 2, which is a flowchart illustrating an OTA upgrading method according to an embodiment of the present disclosure, and as shown in fig. 2, the OTA upgrading method includes:

step S201, the communication module receives the upgrade firmware sent by the server, and determines the target chip to be upgraded currently according to the upgrade sequence of each chip.

Specifically, after receiving the upgrade firmware data of each chip sent by the server, the communication module needs to obtain the upgrade order of each chip from the server, and determines the chip to be upgraded currently according to the upgrade order of each chip, where the chip to be upgraded currently is the first chip in the upgrade order of each chip, and may refer to the chip to be upgraded currently as the target chip. Wherein, the communication module can be the communication module that has wireless communication function, and the WIFI module for example can make electronic equipment be connected to wireless network. The upgrading sequence of each chip is determined according to the arrangement sequence of each chip in the plurality of chips.

For example, please refer to fig. 1 continuously, assuming that the plurality of chips includes three chips, i.e., chip 1, chip 2 and chip 3, where chip 1 is directly connected to the communication module, chip 2 is connected to chip 1, and chip 3 is connected to chip 2, that is, the communication module, chip 1, chip 2 and chip 3 are connected in sequence, according to the arrangement sequence of the chips and the principle of determining the upgrade priority, the chip far from the communication module is upgraded first, and the upgrade sequence of the chips is to upgrade chip 3 first, then upgrade chip 2 and finally upgrade chip 1, and since the three chips are not upgraded before and the upgrade sequence of chip 3 is the first, it is determined that chip 3 is the current chip to be upgraded, i.e., the target chip. Please refer to fig. 3, which is a schematic structural diagram of another OTA upgrading system provided in this embodiment of the present application, as shown in fig. 3, since the chip 2 and the chip 3 are not connected in sequence, there is no specific limitation on the upgrading sequence of the chip 2 and the chip 3, the chip 2 may be upgraded first, or the chip 3 may be upgraded first, that is, the target chip may be the chip 2 or the chip 3.

Step S202, the communication module sends an upgrade starting instruction to the first chip.

Specifically, after receiving the upgrade firmware sent by the server and determining the target chip, the communication module sends an instruction to start upgrading to the first chip, where the first chip may refer to a chip connected to the communication module, and with continued reference to fig. 1 and 3, in fig. 1 and 3, because the chip 1 is connected to the communication module, in fig. 1 and 3, the first chip is the chip 1.

Further, the instruction for starting upgrading sent by the communication module to the first chip includes an identifier of the target chip, where the identifier of the target chip may be model information of a chip to be upgraded, and is used to represent which chip of the plurality of chips is upgraded in the current upgrading. Referring to fig. 1, in fig. 1, since the target chip is the chip 3, that is, the chip to be upgraded at this time is the chip 3, the instruction for starting the upgrade, which is sent by the communication module to the first chip, that is, the chip 1, includes the identifier of the target chip, that is, the model information of the chip 3.

Step S203, starting with the first chip, each chip sequentially sends an upgrade starting instruction to the following chips, if the chip receiving the upgrade starting instruction is the target chip, the target chip adjusts the current chip mode to be the upgrade mode, and other chips except the target chip adjust the respective chip modes to be the transparent transmission mode or the sleep mode.

Specifically, after receiving an upgrade start instruction sent by the communication module, the first chip starts with, and after each chip receives the upgrade start instruction, the first chip sends the upgrade start instruction to a subsequent chip, where the subsequent chip may refer to a chip connected to and subsequent to a certain chip. For example, please refer to fig. 1 again, where chip 1 is a first chip, a subsequent chip of chip 1 is chip 2, and a subsequent chip of chip 2 is chip 3, chip 1 sends an upgrade start instruction to chip 2 after receiving the upgrade start instruction sent by the communication module, and chip 2 sends the instruction to chip 3 after receiving the upgrade start instruction sent by chip 1.

Further, if the chip receiving the start upgrading instruction is the target chip, because the target chip is the chip to be upgraded at this time, the target chip adjusts its current chip mode to the upgrading mode, and the other chips except the target chip adjust their respective chip modes to the transparent transmission mode or the sleep mode. Referring to fig. 1, if the target chip to be upgraded is chip 3, chip 3 enters the upgrade mode, and chip 1 and chip 2 adjust their respective chip modes to the transparent transmission mode or the sleep mode.

Step S204, the communication module sends the upgrade firmware to the first chip.

Specifically, each chip in the plurality of chips receives an upgrade start instruction, and after receiving an instruction of completing upgrade preparation returned by each chip, the communication module sends upgrade firmware data to the first chip. For example, with continued reference to fig. 1, since chip 1 is the first chip, the communication module sends the upgrade firmware data to chip 1.

Step S205, starting with the first chip, each chip sequentially receives the upgrade firmware, and executes upgrade operation or data transparent transmission according to the current respective chip mode.

Specifically, starting with the first chip, each chip sequentially receives the upgrade firmware data, and executes upgrade operation or data transparent transmission for the upgrade firmware data according to the current chip mode.

For example, please refer to fig. 1 continuously, for example, after the chip 1 receives the upgrade firmware sent by the communication module, if the current chip mode is found to be data transparent transmission, the upgrade firmware is transmitted to the chip 2, and the chip 2 finds that the current chip mode is also data transparent transmission, the upgrade firmware is received by the chip 3 after being transmitted continuously, and after the chip 3 receives the upgrade firmware, the current chip mode is found to be the upgrade mode, and then the upgrade firmware is used to execute the upgrade operation to complete the upgrade.

For another example, after the chip 1 receives the upgrade firmware sent by the communication module, if the current chip mode is found to be the data transparent transmission, the upgrade firmware is transmitted to the chip 2, and if the chip 2 finds that the current chip mode is the upgrade mode, the upgrade firmware is used to execute the upgrade operation to complete the upgrade.

In a specific embodiment, the steps S201 to S205 may be executed in a plurality of cycles until each of the plurality of chips is upgraded.

To sum up, an embodiment of the present application provides an OTA upgrading method, including: the communication module receives the upgrading firmware sent by the server and determines a target chip to be upgraded currently according to the upgrading sequence of each chip, wherein the upgrading sequence of each chip is determined according to the arrangement sequence of each chip; the communication module sends an upgrading starting instruction to the first chip, wherein the upgrading starting instruction comprises an identifier of a target chip; starting with a first chip, sequentially sending an upgrading starting instruction to a subsequent chip by each chip, if the chip receiving the upgrading starting instruction is a target chip, adjusting the current chip mode of the target chip to be an upgrading mode by the target chip, and adjusting the respective chip modes of other chips except the target chip to be a transparent transmission mode or a sleep mode by the other chips except the target chip; the communication module sends the upgrade firmware to the first chip; and starting with the first chip, sequentially receiving the upgrading firmware by each chip, and executing upgrading operation or data transparent transmission according to the current respective chip mode. In the above steps, since the upgrading sequence of each chip is preset according to the arrangement sequence of each chip before upgrading, the chips can be upgraded according to the preset upgrading sequence in the upgrading process, and each chip can enter the corresponding chip mode according to the state of the chip in the upgrading process, the upgrading of other side chips can be influenced after the chip on one side has errors in the upgrading process, and further the problem that the upgraded equipment is abnormal is solved, the reliability of OTA upgrading of the electronic equipment is improved, and the accuracy and the efficiency of firmware upgrading of the electronic equipment are improved.

Optionally, the adjusting of the respective chip mode by other chips other than the target chip to the transparent transmission mode or the sleep mode includes:

and if the upgrading state of the second chip in the other chips is upgraded, the second chip adjusts the chip mode to be the sleep mode, wherein the second chip is any one of the other chips.

Specifically, any one of the chips other than the target chip determines its own upgrade status, and if the upgrade status is upgraded, the chip adjusts its chip mode to the sleep mode.

Optionally, the other chips except the target chip adjust their respective chip modes to the transparent transmission mode or the sleep mode, and further include:

and if the upgrading state of the third chip in the other chips is not upgraded, the third chip adjusts the chip mode to be a transparent transmission mode, wherein the third chip is any one of the other chips.

Specifically, any one of the other chips except the target chip judges its own upgrade state, and if the upgrade state is not upgraded, the chip adjusts its chip mode to the transparent transmission mode.

Referring to fig. 1, if the target chip to be upgraded is chip 3, chip 3 enters the upgrade mode, and chip 1 and chip 2 enter the transparent transmission mode because chip 1 and chip 2 are not upgraded yet. If the chip 3 is supposed to be upgraded, the next upgrade is performed, the chip 3 adjusts the chip mode to the sleep mode after receiving the upgrade start instruction, and the chip 2 adjusts the chip mode to the upgrade mode because the target chip of the upgrade is the chip 2, and the chip 1 adjusts the chip mode to the transparent transmission mode because the chip 1 is not upgraded.

The transparent transmission mode may mean that after receiving an instruction or data sent by the communication module or a preceding chip, a certain chip does not process the instruction or data and only forwards the instruction or data to a subsequent chip, and the sleep mode may mean that the certain chip is in a low power consumption mode and does not respond to or receive any instruction or data.

On the basis of predetermining the chip upgrading sequence, other chips except the target chip adjust the respective chip modes into a transparent transmission mode or a dormant mode according to the states of the other chips, so that the problem that the upgrading of the other chips is influenced after the chip on one side is wrong in the upgrading process in the multi-chip upgrading process can be solved, and the reliability of OTA upgrading of the equipment is improved.

Furthermore, when each chip is in the corresponding chip mode, if an abnormality occurs in the upgrading process, such as power failure, disconnection or network disconnection, due to the fact that each chip has the corresponding memory mark when the abnormality occurs, when various abnormal conditions are recovered to be normal, each chip enters the state before the abnormality occurs after reading the corresponding memory mark, and therefore reliability, accuracy and efficiency of OTA upgrading of the equipment are further improved.

Referring to fig. 4, which is a schematic flowchart of another OTA upgrading method provided in the embodiment of the present application, as shown in fig. 4, in step S305, the executing of the upgrading operation or the data transparent transmission according to the current respective chip mode includes:

in step S401, the target chip executes an upgrade operation in the upgrade mode using the upgrade firmware.

Specifically, the target chip is a chip to be upgraded at this time, and therefore, after receiving an instruction to start upgrading, the target chip adjusts the chip mode to the upgrading mode, and then, after receiving upgrading firmware sent by the communication module, in the upgrading mode, executes upgrading operation to complete upgrading.

Step S402, each chip in the transparent transmission mode sends the upgraded firmware to the following chips connected with the chip.

Specifically, each chip in the transparent transmission mode is not the chip to be upgraded of the upgrade, so that each chip in the transparent transmission mode only sends the upgrade firmware to the subsequent chip connected to the upgrade firmware, and each subsequent chip selects whether to upgrade or continue to send the upgrade firmware to the subsequent chip connected to the subsequent chip according to the chip mode of the subsequent chip.

Step S403, if the target chip completes the upgrade operation, the target chip exits the upgrade mode, and sends an upgrade completion response to other chips except the target chip.

Specifically, if the target chip completes the upgrade operation, the target chip exits the upgrade mode, returns to the initial state, and sends a response of the upgrade completion to other chips.

In step S404, after the third chip of the other chips receives the upgrade completion response, the current chip mode is adjusted to the initial state.

When other chips except the target chip receive the response of upgrading completion sent by the target chip, the current chip mode is exited, the respective chip modes are adjusted to be in the initial state, and the process of upgrading the target chip is completed.

Referring to fig. 1, if the target chip to be upgraded is chip 3, after the upgrade operation is completed, chip 3 exits the upgrade mode and sends a response indicating that the upgrade is completed to chip 1 and chip 2, and after chip 1 and chip 2 receive the response indicating that the upgrade is completed, chip mode is adjusted from the transparent transmission mode to the initial state, and the process of upgrading chip 3 is completed.

Please refer to fig. 5, which is a flowchart illustrating another OTA upgrading method according to an embodiment of the present application, as shown in fig. 5, in step S201, the receiving, by the communication module, the upgrade firmware sent by the server includes:

step S501, the communication module sends an upgrade preparation instruction to the first chip.

Step S502, the first chip determines whether each chip meets preset upgrading conditions or not according to the upgrading preparation instruction, and if yes, an upgrading preparation completion response is sent to the communication module.

Specifically, after receiving an instruction for preparing for upgrading sent by the communication module, the first chip needs to determine whether each chip in the plurality of chips meets a preset upgrading condition, and if each chip meets the preset upgrading condition, the first chip sends an upgrading preparation completion response to the communication module to inform the communication module that each chip is ready for upgrading, so that upgrading operation can be performed.

Wherein, satisfying predetermined upgrade condition, can indicating that the equipment body is in under the state of not operating, satisfy the upgrade condition promptly, further, a plurality of chips judge whether current equipment body is in the action state through the action state who obtains current equipment body to judge whether current equipment body can upgrade. And if the current equipment body is judged to be in a non-action state, the preset upgrading condition is met, and a response of upgrading preparation completion can be sent to the communication module.

Step S503, the communication module reads the upgrade firmware from the server according to the upgrade preparation completion response.

Specifically, after receiving an upgrade preparation completion response sent by the first chip, the communication module reads the upgrade firmware from the server so as to send the upgrade firmware to the plurality of chips in the following order to complete the upgrade operation.

Optionally, in step S201, before determining a target chip to be upgraded currently according to an upgrade order of each chip, the method further includes:

and reading the upgrading sequence of each chip from the server. The upgrading sequence of each chip is obtained by setting the upgrading sequence of each chip on the server in advance by a user according to the arrangement sequence of each chip.

With reference to fig. 1, the connection relationship between the chips and the communication module and the arrangement order of the chips can determine that the upgrading order of the chips is as follows: the chip 3, the chip 2, and the chip 1, that is, the far-end chip 3 is upgraded first, then the far-end chip 2 is upgraded, and finally the near-end chip 1 is upgraded, and the following three embodiments will explain the specific upgrading processes of the chip 3, the chip 2, and the chip 1.

Referring to fig. 6, it is a schematic flow chart of another OTA upgrading method provided in the embodiment of the present application, and as shown in fig. 6, the upgrading process of the chip 3 includes:

step S601, the user operates the device to initiate upgrading.

Step S602, the device sends an upgrade preparation instruction to the server.

Step S603, the server sends an update preparation instruction to the communication module.

In step S604, the communication module sends an upgrade preparation command to the chip 1.

In step S605, the chip 1 determines whether the current chips satisfy a preset upgrade condition.

As shown in fig. 6, since the chip 1 is connected to the communication module, the chip 1 may be referred to as a first chip in the foregoing step S502, and after the chip 1 receives an instruction for preparing upgrade, which is sent by the communication module, it needs to determine whether each chip of the plurality of chips currently meets a preset upgrade condition.

Step S606, if the plurality of chips meet the upgrade condition, the chip 1 returns an upgrade preparation completion response to the communication module.

And after judging that each chip meets the preset upgrading condition, the chip 1 serving as the first chip returns an upgrading preparation completion response to the communication module.

In step S607, the communication module downloads the upgrade firmware.

As described in the foregoing step S503, after receiving the upgrade preparation completion response returned by the chip 1 as the first chip, the communication module downloads the upgrade firmware from the server, so as to subsequently send the upgrade firmware data to the plurality of chips.

Step S608, the communication module acquires the upgrading sequence of each chip, and determines the target chip to be upgraded currently according to the upgrading sequence of each chip.

The communication module acquires the upgrading sequence of each chip from the server, wherein the upgrading sequence of each chip is set on the server in advance by a user according to the arrangement sequence of each chip, and the communication module only needs to be read from the server in the upgrading process.

As described in step S201, the communication module receives the upgrade firmware sent by the server, and after the upgrade sequence of each chip is obtained, the communication module needs to determine the target chip to be upgraded currently, where the target chip to be upgraded currently is the chip arranged at the first position in the upgrade sequence, please refer to fig. 6, and the upgrade sequence of each chip can be determined from the arrangement sequence of chip 1, chip 2, and chip 3: chip 3, chip 2, and chip 1, therefore, the target chip currently upgraded is chip 3.

Step S609, the communication module sends an upgrade start instruction to the chip 1, where the upgrade start instruction includes the model information of the chip 3.

Since the chip 1 is the first chip, as described in the foregoing step S202, the communication module sends the upgrade starting instruction to the first chip, that is, the communication module sends the upgrade starting instruction to the chip 1, and since the target chip to be upgraded currently is the chip 3, the upgrade starting instruction includes the model information of the chip 3, and after the chip 1, the chip 2, and the chip 3 receive the upgrade starting instruction, it is known that the chip to be upgraded currently is the chip 3.

In step S610, the chip 1 receives the upgrade start instruction sent by the communication module, and sends the upgrade start instruction to the chip 2.

In step S611, the chip 2 receives the upgrade start instruction sent by the chip 1, and sends the upgrade start instruction to the chip 3.

In step S612, the chip 3 receives the upgrade start instruction sent by the chip 2, and returns an upgrade start completion response to the chip 2.

In step S613, the chip 3 enters the upgrade mode.

After the above steps S610 and S611, the upgrade start instruction sent by the communication module is sent from the chip 1 to the chip 2, and then sent from the chip 2 to the chip 3, and after the chip 3 receives the upgrade start instruction, because the upgrade start instruction includes the model information of the chip 3, in this process, the chip 1, the chip 2, and the chip 3 can be determined, and the target chip to be upgraded is the chip 3 at present, therefore, as described in the foregoing step S203, the chip 3 firstly adjusts the chip mode thereof to the upgrade mode.

In step S614, the chip 2 receives the upgrade start completion response returned from the chip 3, and returns the upgrade start completion response to the chip 1.

After receiving the upgrade start completion response returned by the chip 3, the chip 2 further returns the upgrade start completion response to the chip 1.

In step S615, the chip 2 enters a data transparent transmission mode.

After the chip 2 returns the upgrade start completion response to the chip 1, since the chip 2 already knows from the upgrade start instruction that the target chip to be upgraded is the chip 3, the chip 2 adjusts its chip mode to the transparent transmission mode as described in step S203.

In step S616, the chip 1 receives the upgrade start completion response returned by the chip 2, and returns the upgrade start completion response to the communication module.

After receiving the upgrade start completion response returned by the chip 2, the chip 1 further returns the upgrade start completion response to the communication module.

In step S617, the chip 1 enters the data transparent transmission mode.

After the chip 1 returns the upgrade start completion response to the communication module, since the chip 1 already knows from the upgrade start instruction that the target chip to be upgraded is the chip 3, the chip 1 also adjusts its chip mode to the transparent transmission mode as described in step S203.

In step S618, the communication module sends the firmware upgrading data to the chip 1.

After the communication module receives the upgrade start completion responses returned from the plurality of chips, as described in step S204, the communication module sends the upgrade firmware data to the first chip, i.e., the chip 1.

Step S619, the chip 1 receives the upgrade firmware data and transmits the upgrade firmware data to the chip 2.

As described in step S402, since the chip mode of the chip 1 is the transparent transmission mode, the chip 1 sends the received upgrade firmware data to the chip 2.

In step S620, the chip 2 receives the upgrade firmware data and passes it to the chip 3.

Similarly, as described in step S402, since the chip mode of the chip 2 is also the transparent transmission mode, the chip 2 sends the received upgrade firmware data to the chip 3.

In step S621, the chip 3 receives the firmware upgrading data and upgrades the firmware.

As described in step S401, after receiving the firmware upgrade data, the chip 3 uses the firmware upgrade data to perform firmware upgrade in the upgrade mode.

In step S622, the chip 3 finishes upgrading, exits the upgrading mode, and returns to the initial state.

As described in step S403, after the chip 3 is upgraded, the upgrade mode is exited and the initial state is returned.

In step S623, the chip 3 returns an upgrade completion response to the chip 2.

In step S624, the chip 2 receives the upgrade complete response returned from the chip 3, and returns the upgrade complete response to the chip 1.

As described in step S403, after the chip 3 finishes upgrading, the upgrade mode is exited, and an upgrade completion response is sent to the chip 1 and the chip 2.

In step S625, the chip 2 exits the data transparent transmission mode and returns to the initial state.

As described in step S404, after receiving the response of completing the upgrade of the chip 3, the chip 2 exits from the transparent transmission mode, and adjusts the chip state to the initial state.

In step S626, the chip 1 receives the upgrade complete response returned from the chip 2, and returns the upgrade complete response to the communication module.

After receiving the upgrade completion response returned by the chip 2, the chip 1 needs to send the upgrade completion response to the communication module, so that the communication module enters the next operation process.

In step S627, the chip 1 exits the data transparent transmission mode and returns to the initial state.

Continuing to step S404, after receiving the upgrade completion response sent by the chip 2, the chip 1 exits the transparent transmission mode, and adjusts the chip state to the initial state.

After the upgrade of the chip 3 is completed, the chip 2 starts to be upgraded, please refer to fig. 7, which is a schematic flow diagram of another OTA upgrading method provided in the embodiment of the present application, and as shown in fig. 7, the upgrading process of the chip 2 includes:

step S701, the communication module sends an upgrade starting instruction to the chip 1, and the upgrade starting instruction comprises model information of the chip 2.

After the chip 3 finishes upgrading, the communication module continues to send an upgrading starting instruction to the plurality of chips to upgrade the next chip, and the target chip to be upgraded currently is the chip 2, so the upgrading starting instruction comprises the model information of the chip 2, and after the chip 1, the chip 2 and the chip 3 receive the upgrading starting instruction, the chip to be upgraded currently can be known as the chip 2.

Step S702, the chip 1 receives the upgrade start instruction sent by the communication module, and sends the upgrade start instruction to the chip 2.

In step S703, the chip 2 receives the upgrade start instruction sent by the chip 1, and sends the upgrade start instruction to the chip 3.

In step S704, the chip 3 receives the upgrade start instruction sent by the chip 2, and returns an upgrade start completion response to the chip 2.

In step S705, the chip 3 enters the sleep mode.

After the above steps S702 and S703, the upgrade start instruction sent by the communication module is sent from the chip 1 to the chip 2, and then sent from the chip 2 to the chip 3, and after the chip 3 receives the upgrade start instruction, because the upgrade start instruction includes the model information of the chip 2, in this process, the chip 1, the chip 2, and the chip 3 can be determined, and the target chip to be upgraded at present is the chip 2, so as to achieve the above step S203, and the chip 3 has been upgraded, the chip 3 first adjusts its chip mode to the sleep mode.

In step S706, the chip 2 receives the upgrade start completion response returned from the chip 3, and returns the upgrade start completion response to the chip 1.

In step S707, the chip 2 enters the upgrade mode.

After the chip 2 returns the upgrade start completion response to the chip 1, since the chip 2 already knows from the upgrade start instruction that the target chip to be upgraded is the chip 2, the chip 2 adjusts its chip mode to the upgrade mode as described in step S203.

In step S708, the chip 1 receives the upgrade start completion response returned from the chip 2, and returns the upgrade start completion response to the communication module.

In step S709, the chip 1 enters a data transparent mode.

After the chip 1 returns the upgrade start completion response to the communication module, since the chip 1 already knows from the upgrade start instruction that the target chip to be upgraded is the chip 2, the chip 1 adjusts its chip mode to the transparent transmission mode as described in step S203.

Step S710, the communication module sends the firmware upgrading data to the chip 1.

In step S711, the chip 1 receives the upgrade firmware data and passes it to the chip 2.

As described in step S402, since the chip mode of the chip 1 is the transparent transmission mode, the chip 1 sends the received upgrade firmware data to the chip 2.

In step S712, the chip 2 receives the firmware upgrading data to upgrade the firmware.

As described in step S401, after receiving the firmware upgrade data, the chip 2 uses the firmware upgrade data to perform firmware upgrade in the upgrade mode.

In step S713, the chip 2 finishes upgrading, exits the upgrade mode, and returns to the initial state.

As described in step S403, after the chip 2 is upgraded, the upgrade mode is exited and the initial state is returned.

In step S714, the chip 2 returns an upgrade completion response to the chip 3 and the chip 1, respectively.

As described in step S403, after the chip 2 finishes upgrading, the upgrade mode is exited, and an upgrade completion response is sent to the chip 1 and the chip 3.

In step S715, the chip 3 receives the upgrade completion response sent by the chip 2, exits the sleep mode, and returns to the initial state.

As described in step S404, after receiving the upgrade completion response sent by the chip 2, the chip 3 exits from the sleep mode, and adjusts the chip state to the initial state.

In step S716, the chip 1 receives the upgrade complete response sent by the chip 2, and returns the upgrade complete response to the communication module.

In step S717, the chip 1 exits the data transparent transmission mode and returns to the initial state.

Continuing to step S404, after receiving the upgrade completion response sent by the chip 2, the chip 1 exits the transparent transmission mode, and adjusts the chip state to the initial state.

After the upgrade of the chip 2 is completed, the chip 1 starts to be upgraded, please refer to fig. 8, which is a schematic flow diagram of another OTA upgrading method provided in the embodiment of the present application, and as shown in fig. 8, the upgrading process of the chip 1 includes:

step S801, the communication module sends an upgrade start instruction, where the upgrade start instruction includes model information of the chip 1.

After the chip 3 and the chip 2 are upgraded, the communication module continues to send an instruction for starting upgrading to the plurality of chips, and the next chip is upgraded, and the target chip to be upgraded which is upgraded at present is the chip 1, so that the instruction for starting upgrading comprises the model information of the chip 1, and after the chip 1, the chip 2 and the chip 3 receive the instruction for starting upgrading, the chip to be upgraded at present can be known to be the chip 1.

Step S802, the chip 1 receives the upgrade starting instruction sent by the communication module, and sends the upgrade starting instruction to the chip 2.

In step S803, the chip 2 receives the upgrade start instruction sent by the chip 1, and sends the upgrade start instruction to the chip 3.

Step S804, the chip 3 receives the upgrade start instruction sent by the chip 2, and returns an upgrade start completion response to the chip 2.

In step S805, the chip 3 enters the sleep mode.

After the above steps S802 and S803, the upgrade start instruction sent by the communication module is sent from the chip 1 to the chip 2, and then sent from the chip 2 to the chip 3, and after the chip 3 receives the upgrade start instruction, because the upgrade start instruction includes the model information of the chip 1, in this process, the chip 1, the chip 2, and the chip 3 can be determined, and the target chip to be upgraded at present is the chip 1, so as to achieve the above step S203, and the chip 3 has been upgraded, and the chip 3 first adjusts its chip mode to the sleep mode.

In step S806, the chip 2 receives the upgrade start completion response returned from the chip 3, and returns the upgrade start completion response to the chip 1.

In step S807, chip 2 enters sleep mode.

Similarly, as in step S805, the chip 2 also enters the sleep mode.

Step S808, the chip 1 receives the upgrade start completion response returned by the chip 2, and returns the upgrade start completion response to the communication module.

Step S809, the chip 1 enters the upgrade mode.

After the chip 1 returns the upgrade start completion response to the communication module, since the chip 1 already knows from the upgrade start instruction that the target chip to be upgraded is the chip 1, the chip 1 adjusts its chip mode to the upgrade mode as described in step S203.

Step S810, the communication module sends the firmware upgrading data to the chip 1.

In step S811, the chip 1 receives the firmware upgrade data and performs firmware upgrade.

As described in step S401, after receiving the firmware upgrade data, the chip 1 uses the firmware upgrade data to perform firmware upgrade in the upgrade mode.

In step S812, the chip 1 finishes upgrading, exits the upgrading mode, and returns to the initial state.

As described in step S403, after the chip 1 is upgraded, the upgrade mode is exited and the initial state is returned. And sends an upgrade complete response to the chip 2 and the communication module.

In step S813, the chip 1 returns an upgrade completion response to the chip 2 and the communication module, respectively.

And after the chip 1 is upgraded, exiting the upgrading mode, and sending an upgrading completion response to the chip 2 and the communication module.

In step S814, the chip 2 receives the upgrade complete response returned from the chip 1, and returns the upgrade complete response to the chip 3.

In step S815, the chip 2 exits the sleep mode and returns to the initial state.

Continuing as described in step S404, after the chip 2 receives the upgrade completion response sent by the chip 1, it exits from the sleep mode, and adjusts the chip state to the initial state.

In step S816, the chip 3 receives the upgrade completion response returned from the chip 2, exits from the sleep mode, and returns to the initial state.

Continuing as described in step S404, after the chip 3 receives the upgrade completion response sent by the chip 2, it exits from the sleep mode, and adjusts the chip state to the initial state.

And step S817, the communication module receives the upgrade completion response returned by the chip 1, and returns the upgrade completion response to the server.

Step S818, the server receives the upgrade complete response returned by the communication module, and returns the upgrade complete response to the device.

Step S819, the device receives the upgrade complete response returned by the server, and notifies the user that the upgrade is complete.

To this end, the whole upgrade process of the chip 1, the chip 2, and the chip 3 is completed among the plurality of chips shown in fig. 1.

The embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps in the above OTA upgrading method embodiment are performed.

In particular, the storage medium can be a general-purpose storage medium, such as a removable disk, a hard disk, etc., and when the computer program on the storage medium is executed, the OTA upgrading method embodiment can be executed.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to perform some steps of the methods according to the embodiments of the present application. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.