阅读说明：本技术 阵列基板和显示面板 (Array substrate and display panel ) 是由 张立志 郑浩旋 于 2021-07-15 设计创作，主要内容包括：本申请公开了一种阵列基板和显示面板,所述阵列基板,被划分为显示区和非显示区,所述阵列基板包括：衬底和对应所述非显示区设置在衬底上的外围走线层、外围色阻层和多个第一隔垫物,所述外围色阻层设置在所述衬底上,所述外围色阻层包括多个外围色阻,所述外围走线层包括多条外围走线,所述外围色阻与所述外围走线在所述衬底的投影上不重合,多个所述第一隔垫物对应设置在多个所述外围色阻上。本申请通过上述方案以减少自动光线检测检测过程中的误识别的可能性。(The application discloses array substrate and display panel, array substrate is divided into display area and non-display area, array substrate includes: the non-display color filter comprises a substrate, and a peripheral wiring layer, a peripheral color resistance layer and a plurality of first spacers which are arranged on the substrate corresponding to the non-display area, wherein the peripheral color resistance layer is arranged on the substrate, the peripheral color resistance layer comprises a plurality of peripheral color resistors, the peripheral wiring layer comprises a plurality of peripheral wires, the peripheral color resistors and the peripheral wires are not overlapped on the projection of the substrate, and the plurality of first spacers are correspondingly arranged on the plurality of peripheral color resistors. This application passes through above-mentioned scheme in order to reduce the possibility of the misidentification in the automatic light detection testing process.)

1. An array substrate is divided into a display area and a non-display area, and comprises a substrate, and a peripheral wiring layer, a peripheral color resistance layer and a plurality of first spacers which are arranged on the substrate corresponding to the non-display area, wherein the array substrate is characterized in that:

the peripheral color resistance layer is arranged on the substrate and comprises a plurality of peripheral color resistances, the peripheral wiring layer comprises a plurality of peripheral wirings, the peripheral color resistances and the peripheral wirings are not overlapped on the projection of the substrate, and the first spacers are correspondingly arranged on the peripheral color resistances.

2. The array substrate according to claim 1, wherein the non-display area comprises a peripheral wiring area and a non-peripheral wiring area, the array substrate further comprises a plurality of second spacers corresponding to the non-display area, the plurality of second spacers are disposed corresponding to the peripheral wiring area, and no peripheral color resist is disposed under the second spacers; the first spacer is only arranged on the peripheral color resistor.

3. The array substrate of claim 2, wherein the first spacer has a height equal to the height of the second spacer, and the top surface of the first spacer is higher than the top surface of the second spacer.

4. The array substrate of claim 3, wherein the peripheral color resists are not disposed in the peripheral routing area.

5. The array substrate of claim 3, wherein the array substrate corresponding to the display area comprises: a plurality of third spacers disposed on the substrate; the top surface of the first spacer and the top surface of the third spacer are on the same plane.

6. The array substrate of claim 5, wherein the array substrate corresponding to the display area comprises: the thin film transistor array layer is arranged on the substrate, the first passivation layer is arranged on the thin film transistor array layer, the display color resistance layer is arranged on the first passivation layer, and the third spacers are arranged on the display color resistance layer.

7. The array substrate of claim 6, wherein the first spacer, the second spacer and the third spacer are formed by the same process, and the first spacer, the second spacer and the third spacer have the same height.

8. The array substrate of any of claims 1-7, wherein the peripheral color resist layer comprises: one or more of a red color resist, a green color resist, a blue color resist, a yellow color resist, or a black color resist, the display color resist layer comprising: one or more of a red color resist, a green color resist, and a blue color resist.

9. A display panel comprising a cell-aligned substrate, a liquid crystal layer, and the array substrate according to any one of claims 1 to 7; the array substrate and the opposite box substrate are oppositely arranged, and the liquid crystal layer is arranged between the color film substrate and the array substrate.

10. The display panel according to claim 9, wherein a black matrix is disposed on the pair of cell substrate plates, the black matrix is disposed corresponding to the peripheral routing area, the black matrix of the pair of cell substrate plates abuts against the second spacer of the array substrate, and the pair of cell substrate plates directly abuts against the first spacer of the array substrate.

Technical Field

The application relates to the technical field of display, in particular to an array substrate and a display panel.

Background

The COA (color Filter on array) technology is a technology for preparing a color Filter layer on an array substrate, and a liquid crystal display panel of the existing COA technology is obtained by assembling the array substrate prepared with the color Filter layer and an opposite substrate having a common electrode and a spacer, and has the advantages of a high aperture ratio and a small coupling capacitance. On the basis of COA, a spacer is disposed on a color filter layer of an array substrate, which is called POA (ps on array), a display panel of the POA is often provided with a color filter layer in a non-display area, and in a manufacturing process of the array substrate, peripheral routing of the non-display area requires detection of peripheral automatic Optical inspection (aoi) (automatic Optical inspection), the automatic Optical inspection is performed by a gray scale comparison method, and the peripheral color filter layer affects the automatic Optical inspection, causes erroneous identification, generates a large amount of error reports, and affects normal detection of the automatic Optical inspection.

Disclosure of Invention

The application aims to provide an array substrate and a display panel, and the possibility of error identification in the automatic optical detection process is reduced by arranging peripheral color resistors not corresponding to peripheral wiring.

The application discloses array substrate is divided into display area and non-display area, array substrate includes: the non-display color filter comprises a substrate, and a peripheral wiring layer, a peripheral color resistance layer and a plurality of first spacers which are arranged on the substrate corresponding to the non-display area, wherein the peripheral color resistance layer is arranged on the substrate, the peripheral color resistance layer comprises a plurality of peripheral color resistors, the peripheral wiring layer comprises a plurality of peripheral wires, the peripheral color resistors and the peripheral wires are not overlapped on the projection of the substrate, and the plurality of first spacers are correspondingly arranged on the plurality of peripheral color resistors.

In an embodiment of the application, the non-display area includes a peripheral routing area and a non-peripheral routing area, the array substrate further includes a plurality of second spacers corresponding to the non-display area, the plurality of second spacers are disposed corresponding to the peripheral routing area, and no peripheral color resist is disposed below the second spacers; the first spacer is only arranged on the peripheral color resistor.

In an embodiment of the present application, the height of the first spacer is equal to the height of the second spacer, and the top surface of the first spacer is higher than the top surface of the second spacer.

In an embodiment of the present application, the peripheral color resists are not disposed in the peripheral routing area.

In an embodiment of the present application, the array substrate corresponding to the display area includes: a plurality of third spacers disposed on the substrate; the top surface of the first spacer and the top surface of the third spacer are on the same plane.

In an embodiment of the present application, the array substrate corresponding to the display area includes: the thin film transistor array layer is arranged on the substrate, the first passivation layer is arranged on the thin film transistor array layer, the display color resistance layer is arranged on the first passivation layer, and the third spacers are arranged on the display color resistance layer.

In an embodiment of the present application, the first spacer, the second spacer, and the third spacer are formed by a same process, and heights of the first spacer, the second spacer, and the third spacer are the same.

In an embodiment of the present application, the peripheral color resist layer includes: one or more of a red color resist, a green color resist, a blue color resist, a yellow color resist, or a black color resist, the display color resist layer comprising: one or more of a red color resist, a green color resist, and a blue color resist.

The application also discloses a display panel, includes: the liquid crystal display panel comprises a box aligning substrate, a liquid crystal layer and the array substrate, wherein the box aligning substrate and the array substrate are arranged oppositely, and the liquid crystal layer is arranged between the box aligning substrate and the array substrate.

An embodiment of this application, be provided with black matrix on to the box base plate, black matrix corresponds the regional setting of line is walked to the periphery, to the black matrix of box base plate with array substrate's second spacer butt, to the box base plate with array substrate's first spacer direct butt.

This application is through walking line dislocation set with peripheral colour resistance and periphery, and the projection on the substrate does not coincide promptly, makes not be provided with peripheral colour resistance on the peripheral line of walking, and then when carrying out peripheral line automated optical inspection and detection, can not have peripheral colour resistance to influence the detection of peripheral line of walking. The possibility of false recognition in the automatic optical detection process is reduced, the detection efficiency is improved, and the production efficiency, the yield and the like of the display panel are further improved. And the peripheral color resistor can also be subjected to POA design in the subsequent manufacturing process, thereby ensuring the consistent height inside and outside the box of the display panel.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

fig. 1 is a schematic view of a display panel according to a first embodiment of the present application;

fig. 2 is a schematic view of an array substrate according to a first embodiment of the present application;

FIG. 3 is a schematic top view of a first peripheral trace and a peripheral color resistor according to a first embodiment of the present application;

FIG. 4 is a schematic top view of a second peripheral trace and a peripheral color resistor according to the first embodiment of the present application;

fig. 5 is a schematic view of a cell formed by a pair of an array substrate and a cell-to-cell substrate according to a first embodiment of the present application;

FIG. 6 is a schematic view of a display panel according to a second embodiment of the present application;

fig. 7 is a schematic view of a second display panel of the second embodiment of the present application;

fig. 8 is a schematic diagram of a display panel according to a third embodiment of the present application.

10, a display panel; 100. an array substrate; 101. a display area; 102. a non-display area; 103. a non-peripheral routing area; 104. a peripheral routing area; 110. a substrate; 120. a peripheral wiring layer; 121. peripheral wiring; 130. a peripheral color resist layer; 131. peripheral color resistance; 140. a first spacer; 141. a second spacer; 142. a third spacer; 143. a fourth spacer; 145. a black matrix; 150. a thin film transistor array layer; 151. a thin film transistor; 160. displaying a color resist layer; 170. a first passivation layer; 200. a box aligning substrate; 300. and a liquid crystal layer.

Detailed Description

It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.

Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.

Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

The present application is described in detail below with reference to the figures and alternative embodiments.

The first embodiment is as follows:

as fig. 1 shows a first embodiment of the present application, a display panel is disclosed, the display panel 10 includes an array substrate 100, a pair of cell substrates 200, and a liquid crystal layer 300 disposed between the two substrates. The array substrate adopts a COA process, namely, the color filter layer is arranged on the array substrate. To improve the accuracy of peripheral wiring detection and reduce misjudgment, the main improvement of the method lies in the array substrate.

As shown in fig. 2, the array substrate 100 in the first embodiment, the array substrate 100 is divided into a display area 101 and a non-display area 102, and the array substrate 100 includes, corresponding to the non-display area 102: the color filter comprises a substrate 110, a peripheral routing layer 120 arranged on the substrate 110, a peripheral color resist layer 130 and a plurality of first spacers 140, wherein the peripheral color resist layer 130 is arranged on the peripheral routing layer 120, the peripheral color resist layer 130 comprises a plurality of peripheral color resists 131, the peripheral routing layer 120 comprises a plurality of peripheral routing wires 121, and the plurality of first spacers 140 are correspondingly arranged on the plurality of peripheral color resists 131. The peripheral color resists 131 and the peripheral traces 121 do not coincide in projection on the substrate 110.

According to the application, the peripheral color resistor 131 and the peripheral wiring 121 are arranged in a staggered manner, that is, the projections on the substrate 110 are not overlapped, so that the peripheral color resistor 131 is not arranged on the peripheral wiring 121, and further, when the automatic optical detection of the peripheral wiring 121 is carried out, the peripheral color resistor 131 does not influence the detection of the peripheral wiring 121. The possibility of false recognition in the AOI detection process is reduced, the detection efficiency is improved, and the production efficiency, the yield and the like of the display panel are further improved. The peripheral color resists 131 can be POA designed in subsequent processes, so that the heights of the display panel inside and outside the box are consistent, the box described herein generally uses the sealant disposed between the array substrate 100 and the opposite box substrate as a boundary, the inside of the sealant is the box, the corresponding liquid crystal layer is disposed inside the box, the outside of the box is the outside of the sealant, and the array substrate 100 and the opposite box substrate need to be supported by the spacers designed by the POA.

It should be noted that the peripheral traces generally include test traces and other signal traces, the peripheral traces in this case mainly take the test traces as an example, the staggered arrangement can avoid the arrangement of the corresponding peripheral color resistors 131 when the peripheral traces 121 are initially designed, the mask position of the peripheral color resistors 131 is selectively changed by the mask position of the peripheral traces 121, and the correspondingly formed peripheral color resistors 131 do not coincide with the projection of the peripheral traces 121 on the substrate 110. If the projection of the peripheral color resistor 131 and the peripheral trace 121 on the substrate 110 coincide, the peripheral color resistor 131 and the peripheral trace 121 may coincide during AOI detection, so that the shape, length, etc. of the peripheral trace 121 do not meet the preset requirements. Therefore, this method of the present embodiment can completely solve the problem.

Certainly, there is another mode, because the AOI detection uses a gray scale comparison method, and the non-display area 102 is divided into a plurality of exposure areas, the comparison logic uses the comparison between the exposure areas, if the gray scales of the exposure patterns of the two exposure areas are consistent, the detection is passed, and the same peripheral trace 121 and peripheral color resistor 131 are disposed in the corresponding different exposure areas, which can also be avoided.

As shown in fig. 2, a schematic diagram of the array substrate 100 corresponding to the display area 101 is further disclosed, where the array substrate 100 corresponding to the display area 101 includes: a thin film transistor array layer 150 disposed on the substrate 110, a first passivation layer 170 disposed on the thin film transistor array layer 150, a display color resist layer 160 disposed on the first passivation layer 170, and a plurality of third spacers 142 disposed on the display color resist layer 160.

The display color resists 160 and the peripheral color resists 130 can be formed in the same process, and the same mask process is used, so that compared with the scheme that the POA design is adopted to make the peripheral color resists 131 and the peripheral wires 121 correspondingly arranged, the present application only needs to improve the mask, i.e. the mask of the peripheral color resists 131 is improved corresponding to the positions of the peripheral wires 121, or the mask of the peripheral wires 121 is improved corresponding to the positions of the peripheral color resists 131. It should be noted that the display color resist layer 160 and the peripheral color resist layer 130 are made of the same material, and the difference is that a display color resist 161 is disposed in the display region 101 for emitting light, typically RGB. The peripheral color resist layer 130 includes: one or more of a red color resist, a green color resist, a blue color resist, a yellow color resist, or a black color resist, the display color resist layer 160 includes: one or more of a red color resist, a green color resist, and a blue color resist.

As fig. 3 discloses a schematic top view of the peripheral traces 121 and the peripheral color resists 131, the non-display area 102 includes a peripheral routing area 103 and a non-peripheral routing area 104, and the peripheral color resists 131 are not disposed in the peripheral routing area 103. For a general display panel, it is only necessary to dispose the peripheral color resist layer 130 and the first spacer 140 (not shown in fig. 3, refer to fig. 2) for supporting in the non-peripheral wiring region 104, it is also possible to dispose no spacer for supporting in the peripheral wiring region 103, and the number of the corresponding peripheral color resists 131 in the non-peripheral wiring region 104 is doubled.

For the variation of fig. 3, as shown in fig. 4, which is a schematic top view of the second peripheral trace 121 and the peripheral color resists 131, the peripheral color resists 131 may be disposed in the peripheral trace area 103, but the peripheral color resists 131 are disposed in the space between two adjacent peripheral traces, and the projection on the substrate 110 is not overlapped with the peripheral trace 121. The peripheral color resistor 131 is disposed in a blank area between two adjacent peripheral wires 121, the peripheral color resistor 131 does not affect the AOI detection of the peripheral wires 121, and a first spacer 140 (not shown in fig. 4, refer to fig. 2) may be disposed on the peripheral color resistor 131, and the first spacer 140 abuts against the box substrate to support the thickness of the box outside the display panel box. It should be noted that, in general, a flat layer may be further disposed on the peripheral wiring layer 120, that is, the first passivation layer is a flat layer, a flat layer may be disposed inside the display region 101, and the flat layers of the display region 101 and the non-display region 102 have the same plane, so that the heights of the display color resist layer 160 inside the box and the peripheral color resist layer 130 outside the box are the same, and further, the thicknesses of the box inside the box and the box outside the box are the same.

Fig. 5 is a schematic view illustrating the array substrate 100 and the pair of cell substrates of fig. 2 forming a cell, wherein the top surface of the first spacer 140 is on the same horizontal plane as the top surface of the third spacer 142. The first spacer 140 and the third spacer 142 are abutted to the opposing substrate for supporting the thickness of the display panel between the opposing substrate and the array substrate 100, so that the thickness of the display panel inside and outside the display panel is more consistent.

Example two:

as a second embodiment of the present application, as shown in fig. 6, a display panel is disclosed, the display panel includes an array substrate 100 and a pair of box substrates, the array substrate 100 includes, corresponding to the non-display area 102: the color filter comprises a substrate 110, a peripheral routing layer 120 arranged on the substrate 110, a peripheral color resist layer 130 and a plurality of first spacers 140, wherein the peripheral color resist layer 130 is arranged on the peripheral routing layer 120, the peripheral color resist layer 130 comprises a plurality of peripheral color resists 131, the peripheral routing layer 120 comprises a plurality of peripheral routing wires 121, and the plurality of first spacers 140 are correspondingly arranged on the plurality of peripheral color resists 131. The peripheral color resists 131 and the peripheral traces 121 do not coincide in projection on the substrate 110.

Specifically, the design of the spacers in the second embodiment is as shown in the schematic diagrams of the first spacer 140 and the second spacer 141 in fig. 6, the non-display area 102 includes a peripheral routing area 103 and a non-peripheral routing area 104, the array substrate 100 further includes a plurality of first spacers 140 and a plurality of second spacers 141 corresponding to the non-display area 102, the plurality of first spacers 140 are only disposed on the plurality of peripheral color resists 131, and the plurality of second spacers 141 are disposed corresponding to the plurality of peripheral routing areas; the peripheral color resistor 131 is not arranged below the second spacer 141.

If the peripheral wiring area 103 is not provided with a spacer for supporting, there may be a problem of insufficient support, which results in inconsistent thickness inside and outside the box, and further causes the problem of uneven box thickness, and may seriously cause mura phenomenon, therefore, in this embodiment, the second spacer 141 is further provided for the peripheral wiring area 103, but the peripheral color resistance 131 is not provided for the peripheral wiring area 103, because the second spacer 141 is provided, the AOI detection of the peripheral wiring by the array substrate 100 is not affected, and therefore, the second spacer 141 provided for the peripheral wiring area 103 may also support the box thickness there.

Specifically, the height of the first spacer 140 is equal to the height of the second spacer 141, and the top surface of the first spacer 140 is higher than the top surface of the second spacer 141. That is, the first spacer 140 and the second spacer 141 are formed by the same process, and the height of the first spacer 140 is equal to the height of the second spacer 141, but the top surface of the second spacer 141 is lower than the top surface of the first spacer 140 because the peripheral color resist 131 is not disposed under the second spacer 141, but the second spacer 141 can support although there is a height difference, and particularly, the second spacer 141 can support when the box thickness is changed.

As shown in fig. 6, a schematic diagram of the array substrate 100 corresponding to the display area 101 is further disclosed, where the array substrate 100 corresponding to the display area 101 includes: a thin film transistor array layer 150 disposed on the substrate 110, a first passivation layer 170 disposed on the thin film transistor array layer 150, a display color resist layer 160 disposed on the first passivation layer 170, and a plurality of third spacers 142 disposed on the display color resist layer 160.

Specifically, the first spacer 140, the second spacer 141, and the third spacer 142 are formed through the same process, and the first spacer 140, the second spacer 141, and the third spacer 142 have the same height.

In an optional embodiment, the array substrate 100 further includes, corresponding to the display area 101: and a fourth spacer 143 disposed on the display color resist layer 160, wherein the height of the fourth spacer 143 is smaller than the height of the third spacer 142, so that a certain height difference is formed between the third spacer 142 and the fourth spacer 143, which is beneficial for providing a strong support for the fourth spacer 143 when the box thickness in the box of the display panel changes. In the present application, the first spacer 140, the second spacer 141, the third spacer 142, and the fourth spacer 143 are made of the same material, such as organic resin.

Of course, as shown in fig. 7, in the second schematic view of the array substrate 100, the height of the first spacer 140 is not equal to the height of the second spacer 141, but the top surface of the first spacer 140 is equal to the top surface of the second spacer 141, i.e. directly abuts against the opposing substrate.

Example three:

as shown in fig. 8, as a third embodiment of the present application, the present application also discloses a display panel including: an array substrate 100, a pair of cell substrates and a liquid crystal layer; the opposite box substrate is opposite to the array substrate 100, and the liquid crystal layer is arranged between the opposite box substrate and the array substrate 100. The array substrate 100 may be selected from the different array substrates 100 in the above embodiments. In the array substrate 100 in the display panel shown in fig. 6, the present embodiment improves the pair of box substrates on the basis of the second embodiment, specifically as shown in fig. 8:

the pair of box substrates are provided with black matrixes 145, the black matrixes 145 of the pair of box substrates are arranged in the area, corresponding to the peripheral routing, of the black matrixes 145 and abutted against the second spacers 141 of the array substrate 100, and the pair of box substrates are directly abutted against the first spacers 140 of the array substrate 100.

It should be noted that, if other film layers are further disposed on the pair of box substrates, in the corresponding embodiment, only the sum of the heights of the second spacer and the black matrix is limited to be equal to the sum of the heights of the first spacer and the peripheral color resistor, so that the second spacer and the first spacer jointly play a supporting role.

It should be noted that the inventive concept of the present application can form many embodiments, but the present application has a limited space and cannot be listed one by one, so that, on the premise of no conflict, any combination between the above-described embodiments or technical features can form a new embodiment, and after the embodiments or technical features are combined, the original technical effect will be enhanced

The technical scheme of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, and MVA (Multi-Domain Vertical Alignment) display panel, and all of them can be applied to the above scheme.

The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.