阅读说明：本技术 内插电路以及马达驱动电路 (Interpolation circuit and motor drive circuit ) 是由 涂瑞玲 周锦荣 于 2020-12-21 设计创作，主要内容包括：本发明公开了一种内插电路,包括：相移电路,产生相移信号；第一多工器,接收该相移信号；第一比较器,包括第一正输入端和第一负输入端,用以接收该第一多工器输出的该相移信号；第二比较器,包括第二正输入端和第二负输入端,用以接收该第一多工器输出的该相移信号；第一状态控制电路,用以根据该第一正输入端和该第一负输入端接收的该相移信号的第一比较结果以及该第二正输入端和该第二负输入端接收的该相移位信号的第二比较结果,来控制该第一多工器切换到不同的状态；以及第一电压准位补偿电路,在该第一多工器的状态改变时上拉或下拉来自该第一输出端的第一输出信号或来自该第二输出端的第二输出信号。本发明可以改善比较器的磁滞问题。(The invention discloses an interpolation circuit, comprising: a phase shift circuit generating a phase shift signal; a first multiplexer for receiving the phase-shifted signal; a first comparator, including a first positive input terminal and a first negative input terminal, for receiving the phase-shifted signal output by the first multiplexer; a second comparator, including a second positive input terminal and a second negative input terminal, for receiving the phase-shifted signal output by the first multiplexer; a first state control circuit for controlling the first multiplexer to switch to different states according to a first comparison result of the phase shift signal received by the first positive input terminal and the first negative input terminal and a second comparison result of the phase shift signal received by the second positive input terminal and the second negative input terminal; and a first voltage level compensation circuit for pulling up or pulling down a first output signal from the first output terminal or a second output signal from the second output terminal when the state of the first multiplexer changes. The invention can improve the hysteresis problem of the comparator.)

1. An interpolation circuit, comprising:

a phase shift circuit for receiving an input signal to generate a phase-shifted signal of the input signal;

a first multiplexer for receiving at least a portion of the phase shifted signal;

a first comparator, including a first positive input terminal and a first negative input terminal, for receiving the phase-shifted signal output by the first multiplexer;

a second comparator, including a second positive input terminal and a second negative input terminal, for receiving the phase-shifted signal output by the first multiplexer, wherein the first comparator and the second comparator do not receive the same phase-shifted signal at the same time;

a first state control circuit, configured to control the first multiplexer to switch to different states according to a first comparison result of the phase shift signal received by the first positive input terminal and the first negative input terminal and a second comparison result of the phase shift signal received by the second positive input terminal and the second negative input terminal, where the first multiplexer outputs different phase shift signals in different states; and

a first voltage level compensation circuit coupled to the first output terminal of the first comparator and the second output terminal of the second comparator for pulling up a first output signal from the first output terminal or a second output signal from the second output terminal when the state of the first multiplexer changes, or pulling down the first output signal or the second output signal when the state of the first multiplexer changes.

2. The interpolation circuit of claim 1, wherein the first state control circuit controls the first multiplexer to switch to the different state when the value of the phase-shifted signal at the first positive input is greater than the value of the phase-shifted signal at the first negative input and the value of the phase-shifted signal at the second positive input is greater than the value of the phase-shifted signal at the second negative input.

3. The interpolation circuit of claim 1, wherein the first state control circuit controls the first multiplexer to switch to the different state when the value of the phase-shifted signal at the first positive input is less than the value of the phase-shifted signal and the value of the phase-shifted signal at the first negative input is less than the value of the phase-shifted signal at the second positive input.

4. The interpolation circuit of claim 1, wherein the output of the first comparator is pulled down or pulled up when the first multiplexer switches to a next state and the phase shifted signal input to the first comparator changes.

5. The interpolation circuit of claim 1, wherein the first voltage level compensation circuit pulls down the first output signal to a logic value 0 if the value of the phase shifted signal received by the first positive input terminal changes from greater than the value of the phase shifted signal received by the first negative input terminal to less than the value of the phase shifted signal received by the first negative input terminal.

6. The interpolation circuit of claim 1, wherein the first voltage level compensation circuit pulls the first output signal up to logic value 1 if the value of the phase shifted signal received by the first positive input changes from being less than the value of the phase shifted signal received by the first negative input to being greater than the value of the phase shifted signal received by the first negative input.

7. The interpolation circuit of claim 1, further comprising:

a second multiplexer for receiving at least a portion of the phase shifted signal, wherein the first multiplexer and the second multiplexer receive different ones of the phase shifted signals;

a third comparator, including a third positive input terminal and a third negative input terminal, for receiving the phase-shifted signal output by the second multiplexer;

a fourth comparator including a fourth positive input terminal and a fourth negative input terminal for receiving the phase-shifted signal output by the second multiplexer, wherein the third comparator and the fourth comparator do not receive the same phase-shifted signal at the same time;

a second state control circuit, configured to control the second multiplexer to switch to different states according to a third comparison result of the phase shift signal received by the third positive input terminal and the third negative input terminal and a fourth comparison result of the phase shift signal received by the fourth positive input terminal and the fourth negative input terminal, where the second multiplexer outputs different phase shift signals in different states; and

a second voltage level compensation circuit coupled to the third output terminal of the third comparator and the fourth output terminal of the fourth comparator for pulling up the third output signal from the third output terminal or the fourth output signal from the fourth output terminal when the state of the second multiplexer changes or pulling down the third output signal or the fourth output signal when the state of the second multiplexer changes.

8. The interpolation circuit of claim 7, wherein the first multiplexer receives the phase-shifted signal with a phase offset of sin (2nx1.8 °) from the input signal, and the second multiplexer receives the phase-shifted signal with a phase offset of sin [ (2N +1) x1.8 ° ] from the input signal, where N is 0 or a positive integer.

9. The interpolation circuit of claim 1, wherein the first voltage level compensation circuit is configured to compensate for hysteresis effects of the first comparator and the second comparator.

10. A motor drive circuit, comprising:

an interpolation circuit, comprising:

a phase shift circuit for receiving an input signal to generate a phase-shifted signal of the input signal;

a first multiplexer for receiving at least a portion of the phase shifted signal;

a first comparator, including a first positive input terminal and a first negative input terminal, for receiving the phase-shifted signal output by the first multiplexer;

a second comparator, including a second positive input terminal and a second negative input terminal, for receiving the phase-shifted signal output by the first multiplexer, wherein the first comparator and the second comparator do not receive the same phase-shifted signal at the same time;

a first state control circuit, configured to control the first multiplexer to switch to different states according to a first comparison result of the phase shift signal received by the first positive input terminal and the first negative input terminal and a second comparison result of the phase shift signal received by the second positive input terminal and the second negative input terminal, where the first multiplexer outputs different phase shift signals in different states; and

a first voltage level compensation circuit coupled to a first output terminal of the first comparator and a second output terminal of the second comparator to pull up a first output signal from the first output terminal or a second output signal from the second output terminal when a state of the first multiplexer changes, or pull down the first output signal or the second output signal when the state of the first multiplexer changes; and

a first clock generating circuit for generating a first clock signal according to the first output signal and the second output signal;

the first voltage level compensation circuit generates a first motor control signal according to the first output signal, the second output signal and the first clock signal.

11. The motor drive circuit of claim 10 wherein the first state control circuit controls the first multiplexer to switch to the different state when the value of the phase-shifted signal at the first positive input is greater than the value of the phase-shifted signal at the first negative input and the value of the phase-shifted signal at the second positive input is greater than the value of the phase-shifted signal at the second negative input.

12. The motor drive circuit of claim 10 wherein the first state control circuit controls the first multiplexer to switch to the different state when the value of the phase-shifted signal at the first positive input is less than the value of the phase-shifted signal and the value of the phase-shifted signal at the first negative input is less than the value of the phase-shifted signal at the second positive input.

13. The motor drive circuit of claim 10 wherein the output of the first comparator is pulled down or pulled up when the first multiplexer switches to a next state and the phase shifted signal input to the first comparator changes.

14. The motor driver circuit of claim 10, wherein the first voltage level compensation circuit pulls the first output signal down to a logic value 0 when the value of the phase-shifted signal received by the first positive input terminal changes from greater than the value of the phase-shifted signal received by the first negative input terminal to less than the value of the phase-shifted signal received by the first negative input terminal.

15. The motor driver circuit of claim 10, wherein the first voltage level compensation circuit pulls up the first output signal to logic 1 when the value of the phase-shifted signal received by the first positive input terminal changes from less than the value of the phase-shifted signal received by the first negative input terminal to greater than the value of the phase-shifted signal received by the first negative input terminal.

16. The motor drive circuit of claim 10, wherein the interpolation circuit further comprises: a second multiplexer for receiving at least a portion of the phase shifted signal, wherein the first multiplexer and the second multiplexer receive different ones of the phase shifted signals;

a third comparator, including a third positive input terminal and a third negative input terminal, for receiving the phase-shifted signal output by the second multiplexer;

a fourth comparator including a fourth positive input terminal and a fourth negative input terminal for receiving the phase-shifted signal output by the second multiplexer, wherein the third comparator and the fourth comparator do not receive the same phase-shifted signal at the same time;

a second state control circuit, configured to control the second multiplexer to switch to different states according to a third comparison result of the phase shift signal received by the third positive input terminal and the third negative input terminal and a fourth comparison result of the phase shift signal received by the fourth positive input terminal and the fourth negative input terminal, where the second multiplexer outputs different phase shift signals in different states; and

a second voltage level compensation circuit coupled to the third output terminal of the third comparator and the fourth output terminal of the fourth comparator for pulling up the third output signal from the third output terminal or the fourth output signal from the fourth output terminal when the state of the second multiplexer changes or pulling down the third output signal or the fourth output signal when the state of the second multiplexer changes.

17. The motor drive circuit of claim 16 wherein the first multiplexer receives the phase-shifted signal with a phase offset of sin (2nx1.8 °) from the input signal, and the second multiplexer receives the phase-shifted signal with a phase offset of sin [ (2N +1) x1.8 ° ] from the input signal, where N is 0 or a positive integer.

18. The motor drive circuit of claim 15 wherein the interpolation circuit further comprises:

a second clock generating circuit for generating a second clock signal according to the third output signal and the fourth output signal;

wherein the second voltage level compensation signal further generates a second motor control signal according to the third output signal, the fourth output signal and the second clock signal.

19. The motor driving circuit as claimed in claim 10, wherein the first voltage level compensation circuit is configured to compensate hysteresis effects of the first comparator and the second comparator.

Technical Field

The present invention relates to an interpolation circuit and a motor driving circuit, and more particularly, to an interpolation circuit and a motor driving circuit capable of improving hysteresis.

Background

Existing add-in circuits used in motors typically include multiplexers and comparators. The multiplexer is used to select different input signals for the comparator. Furthermore, the comparator compares the input signals and is triggered in dependence on the signal values of the input signals received at the different receiving terminals. The comparator may have hysteresis (hystersis) to have higher noise immunity. However, hysteresis may cause some problems.

Fig. 1 is a schematic diagram showing a hysteresis problem in the prior art. IN fig. 1, the output signal OS is the output signal of an ideal comparator without hysteresis, and the input signals IN _1, IN _2 are input to different receiving terminals of the comparator. The logical value of the output signal OS is switched at times t1 and t2, and the signal values of the input signals IN _1, IN _2 are equal at times t1 and t 2. However, due to hysteresis, the logical value of the output signal OS ' of the actual comparator transitions at time t1' and time t2', which lag behind time t1 and time t2, respectively, by a delay time D.

Such a delay may affect the accuracy of the comparison result of the comparator.

Disclosure of Invention

Therefore, an objective of the present invention is to disclose an interpolation circuit, which can improve the hysteresis of a comparator.

Another objective of the present invention is to disclose a motor control circuit, which can improve the hysteresis of the comparator.

An embodiment of the present invention discloses an interpolation circuit, including: a phase shift circuit for receiving an input signal to generate a phase-shifted signal of the input signal; a first multiplexer for receiving at least a portion of the phase shifted signal; a first comparator, including a first positive input terminal and a first negative input terminal, for receiving the phase-shifted signal output by the first multiplexer; a second comparator, including a second positive input terminal and a second negative input terminal, for receiving the phase-shifted signal output by the first multiplexer, wherein the first comparator and the second comparator do not receive the same phase-shifted signal at the same time; a first state control circuit, configured to control the first multiplexer to switch to different states according to a first comparison result of the phase shift signal received by the first positive input terminal and the first negative input terminal and a second comparison result of the phase shift signal received by the second positive input terminal and the second negative input terminal, where the first multiplexer outputs different phase shift signals in different states; and a first voltage level compensation circuit coupled to a first output terminal of the first comparator and a second output terminal of the second comparator to pull up a first output signal from the first output terminal or a second output signal from the second output terminal when a state of the first multiplexer changes, or pull down the first output signal or the second output signal when the state of the first multiplexer changes.

The embodiment of the invention discloses a motor driving circuit which comprises an interpolation circuit and a first clock generation circuit. The interpolation circuit includes: a phase shift circuit for receiving an input signal to generate a phase-shifted signal of the input signal; a first multiplexer for receiving at least a portion of the phase shifted signal; a first comparator, including a first positive input terminal and a first negative input terminal, for receiving the phase-shifted signal output by the first multiplexer; a second comparator, including a second positive input terminal and a second negative input terminal, for receiving the phase-shifted signal output by the first multiplexer, wherein the first comparator and the second comparator do not receive the same phase-shifted signal at the same time; a first state control circuit, configured to control the first multiplexer to switch to different states according to a first comparison result of the phase shift signal received by the first positive input terminal and the first negative input terminal and a second comparison result of the phase shift signal received by the second positive input terminal and the second negative input terminal, where the first multiplexer outputs different phase shift signals in different states; and a first voltage level compensation circuit coupled to a first output terminal of the first comparator and a second output terminal of the second comparator to pull up a first output signal from the first output terminal or a second output signal from the second output terminal when a state of the first multiplexer changes, or pull down the first output signal or the second output signal when the state of the first multiplexer changes. The first clock generating circuit is used for generating a first clock signal according to the first output signal and the second output signal. The first voltage level compensation circuit generates a first motor control signal according to the first output signal, the second output signal and the first clock signal.

According to the foregoing embodiment, the output of the comparator can be compensated to improve the hysteresis problem of the comparator, so that the comparison result of the comparator can be more accurate.

Drawings

Fig. 1 is a schematic diagram showing a hysteresis problem in the prior art.

FIG. 2 is a block diagram of an interpolation circuit according to an embodiment of the invention.

Fig. 3 shows an example of phase shift signals received by different comparators in different states.

FIG. 4 is a flowchart illustrating a state switching operation of the interpolation circuit shown in FIG. 2 according to an embodiment of the present invention.

Fig. 5 and 6 show waveforms of interpolation circuits according to different embodiments of the present invention.

FIG. 7 is a schematic diagram illustrating the operation of the interpolation circuit as a motor driving circuit.

Wherein the reference numerals are as follows:

200 interpolation circuit

201 phase shift circuit

MUX _1 first multiplexer

MUX _2 second multiplexer

SC _1 first state control circuit

SC _2 second state control circuit

CM _1 first comparator

CM _2 second comparator

CM _3 third comparator

CM _4 fourth comparator

VC _1 first voltage compensation circuit

CG _1 first clock generation circuit

CG _2 second clock generating circuit

Detailed Description

The present invention will be described in terms of various embodiments, and it should be further understood that elements in the various embodiments may be implemented by hardware (e.g., a device or a circuit) or firmware (e.g., at least one program written in a microprocessor). Furthermore, the terms "first," "second," and the like in the following description are used only to define different elements, parameters, data, signals, or steps. And are not intended to be limiting.

FIG. 2 is a block diagram of an interpolation circuit 200 according to an embodiment of the invention. As shown in fig. 2, the interpolation circuit 200 includes a phase shift circuit 201, a first multiplexer MUX _1, a second multiplexer MUX _2, a first state control circuit SC _1, a second state control circuit SC _2, a first comparator CM _1, a second comparator CM _2, a third comparator CM _3, a fourth comparator CM _4, and a first voltage compensation circuit VC _ 1. In an embodiment, the interpolation circuit 200 may further include a second voltage compensation circuit used in the second multiplexer MUX _2, a second state control circuit SC _2, a third comparator CM _3, and a fourth comparator CM _ 4. The second voltage compensation circuit may be a circuit independent of the first voltage compensation circuit VC _1, or may be integrated into the first voltage compensation circuit VC _ 1.

The phase shift circuit 201 is configured to receive at least one input signal IN _1 … IN _ k to generate a plurality of phase shift signals PS _11-PS _1n, PS _21-PS _2n of the input signal IN _1 … IN _ k. The first multiplexer Mux _1 is used for receiving at least a portion of the phase shifted signals PS _11-PS _1n, PS _21-PS _2 n. The first comparator CM _1, which includes a first positive input terminal and a first negative input terminal, is configured to receive the phase-shifted signal output by the first multiplexer MUX _ 1. The second comparator CM _2, which includes a second positive input terminal and a second negative input terminal, is used to receive the phase-shifted signals PS _11-PS _1n outputted by the first multiplexer MUX _ 1. The first state control circuit SC _1 is configured to control the first multiplexer MUX _1 to switch to different states according to a first comparison result of the phase-shifted signals received by the first positive input terminal and the first negative input terminal and a second comparison result of the phase-shifted signals received by the second positive input terminal and the second negative input terminal. The first comparator CM _1 and the second comparator CM _2 do not receive the same phase shifted signal at the same time.

The first multiplexer MUX _1 outputs different phase shifted signals in different states. The first voltage level compensation circuit VC _1 is coupled to the first output terminal of the first comparator CM _1 and the second output terminal of the second comparator CM _2 to pull down (pull down) or pull up (pull up) the first output signal from the first output terminal or the second output signal from the second output terminal when the state of the first multiplexer MUX _1 is changed. The first voltage level compensation circuit VC _1 can compensate for hysteresis effects of the first comparator CM _1 and the second comparator CM _ 2.

In one embodiment, the analog input signal and its inverse are input to the signal phase shift circuit 201. Also, the signal phase shift circuit 201 generates a phase-shifted signal having a different phase shift from the input signal. In this case, the first multiplexer MUX _1 receives a phase-shifted signal phase-shifted from the input signal by sin (2nx1.8 °), and the second multiplexer MUX _2 receives a phase-shifted signal phase-shifted from the input signal by sin [ (2N +1) x1.8 ° ], N being 0 or a positive integer. For example, the first multiplexer MUX _1 receives a phase shifted signal with a phase shift of sin0 °, sin3.6 ° … sin356.4 ° from the input signal, while the second multiplexer MUX _2 has a phase shifted signal with a phase shift of sin1.8 °, sin5.4 ° … sin358.2 ° from the input signal. For convenience of understanding, a signal having a phase shift sin (2nx1.8 °) from the input signal is referred to as a signal sin (2nx1.8 °), and a signal having a phase shift sin [ (2N +1) x1.8 ° ] from the input signal is referred to as a signal sin [ (2N +1) x1.8 ° ]. For example, the signal sin0 ° represents a phase signal that is phase shifted by sin0 ° from the input signal, and the signal sin5.4 ° represents a phase signal that is phase shifted by sin5.4 ° from the input signal.

In the following description, the operations of the second multiplexer MUX _2, the second state control circuit SC _2, the third comparator CM _3, and the fourth comparator CM _4 are the same as those of the first multiplexer MUX _1, the first state control circuit SC _1, the first comparator CM _1, and the second comparator CM _2, and thus the description will not be repeated. In addition, in one embodiment, the second state control circuit SC _2, the third comparator CM _3, the fourth comparator CM _4 and the second voltage level compensation circuit can be omitted from the interpolation circuit 200. The third comparator CM _3 has a third positive input terminal and a third negative input terminal, and the fourth comparator CM _4 has a fourth positive input terminal and a fourth negative input terminal. In addition, the third comparator CM _3 outputs a third output signal, and the fourth comparator CM _4 outputs a fourth output signal.

As described above, the first multiplexer MUX _1 outputs different ones of the phase-shifted signals having different states, and the first multiplexer MUX _1 may be switched based on the comparison results of the first comparator CM _1 and the second comparator CM _2 (i.e., according to the first output signal and the second output signal). In an embodiment, such as the embodiment of fig. 5, the first state control circuit SC _1 controls the first multiplexer MUX _1 to switch to a different state when the value of the phase shifted signal at the first positive input of the first comparator CM _1 is greater than the value of the phase shifted signal at the first negative input of the first comparator CM _1 and the value of the phase shifted signal at the second positive input of the second comparator CM _2 is greater than the value of the phase shifted signal at the second negative input of the second comparator CM _ 2. Moreover, in another embodiment, such as the embodiment of fig. 6, the first state control circuit SC _1 controls the first multiplexer MUX _1 to switch to a different state when the value of the phase shifted signal at the first positive input of the first comparator CM _1 is less than the value of the phase shifted signal at the first negative input of the first comparator CM _1 and the value of the phase shifted signal at the second positive input of the second comparator CM _2 is less than the value of the phase shifted signal at the second negative input of the second comparator CM _ 2. The embodiments of fig. 5 and 6 will be described in more detail later.

FIG. 4 is a flowchart illustrating a state switching operation of the interpolation circuit shown in FIG. 2 according to an embodiment of the present invention. In addition, fig. 5 is a waveform of the interpolation circuit shown in fig. 2 according to an embodiment of the present invention. Please refer to fig. 2, fig. 4 and fig. 5 together to understand the concept of the present invention.

Please refer to fig. 2 again. In one embodiment, the interpolation circuit is a 50 × interpolation circuit, so the first state control circuit SC _1 can control the 50 paths YA0, YA1, YA2 … YA49 of the first multiplexer MUX _1, so that the first comparator CM _1 or the second comparator CM _2 receives different phase-shifted signals under different states. For example, if the paths YA0, YA1 are in the active state in state 0, the first comparator CM _1 receives the signals sin0 °, sin180 ° (YA0), the second comparator CM _2 receives the signals sin3.6 °, sin183.6 ° (YA 1). Similarly, the second state control circuit SC _2 may control the 50 paths YB0, YB1, YB2 … YB49 of the second multiplexer MUX _2, and the third comparator CM _3, the fourth comparator CM _4 to receive different phase shift signals in different states. For example, if the paths YB0, YB1 are in the active state at state 0, the third comparator CM _3 receives sin1.8 °, sin181.8 ° (YB0), and the fourth comparator CM _2 receives sin5.4 °, sin185.4 ° (YB 1).

Further, in the next state (state 1), the paths YA0, YB0 are not activated, and the paths YA2, YA1, YB2, YB1 are activated. In this case, the first comparator CM _1 receives the signals sin7.2 °, sin187.2 ° (YA2), while the second comparator CM _2 still receives the phase signals sin3.6 °, sin183.6 ° (YA 1). Likewise, in this case, the third comparator CM _3 receives the signals sin9.0 °, sin189.0 ° (YB2), and the fourth comparator CM _2 receives the signals sin5.4 °, sin185.4 ° (YB 1). Fig. 3 shows some examples of phase shifted signals received by the first, second, third and fourth comparators CM _1, CM _2, CM _3 and CM _4 in different states, but is not meant to limit the scope of the invention.

As described above, the first control circuit SC _1 may switch the state of the first multiplexer MUX _1 according to the output a0 and the output a1 (i.e., the first comparison result and the second comparison result, or the first output signal and the second output signal of the first comparator CM _1 and the second comparator CM _ 2). Moreover, the voltage compensation circuit VC _1 pulls up or pulls down the output of the first comparator CM _1 or the second comparator CM _2 to improve the hysteresis problem. The detailed operation will be described in the following description. In one embodiment, the output of the first comparator CM _1 or the second comparator CM _2 is pulled up to a logic value 1 or pulled down to a logic value 0.

In fig. 2, the first comparator CM _1 comprises a first positive input terminal for receiving the positive input IMP and comprises a first negative input terminal for receiving the negative input IMM. Furthermore, the second comparator CM _1 comprises a second positive input terminal for receiving the positive input IMP and comprises a second negative input terminal for receiving the negative input IMM. The output a0 of the first comparator CM _1 becomes 1 when the signal value of its positive input INP is greater than that of its negative input INM, and becomes 0 when the signal value of its positive input INP is less than that of its negative input INM. In addition, the output a1 of the second comparator CM _2 becomes 1 when the signal value of its positive input INP is larger than that of its negative input INM, and becomes 0 when the signal value of its positive input INP is smaller than that of its negative input INM.

Therefore, as shown in fig. 5, it is assumed that the first comparator CM _1 and the second comparator CM _2 start from the state (state)0 (S0 in fig. 5, step 403 in fig. 4). In state 0, the first comparator CM _1 receives the phase-shifted signal corresponding to path YA0 and the second comparator CM _2 receives the phase-shifted signal corresponding to path YA 1. In addition, if the outputs a0, a1 are 10 or 01, the first multiplexer MUX _1 remains in the same state, and if the outputs a0, a1 are output 11, it switches to the pull-down interval 0, i.e. the pre-state (pre-state)1 of step 405 in fig. 4. In the pull-down interval 0, the output of the first comparator CM _1 is pulled down. Then, if the output a0, a1, is 10 or 01, the first multiplexer MUX _1 enters state 1 (S1 in fig. 5, step 407 in fig. 4). In state 1, the first comparator CM _1 receives the phase-shifted signal corresponding to path YA2 and the second comparator CM _2 receives the phase-shifted signal corresponding to path YA1, as described above in fig. 3.

In state 1, the first multiplexer MUX _1 remains in the same state if the outputs a0, a1 are 10 or 01, and switches to pull-down interval 1 if the outputs a0, a1 are 11 (pre-state 2, step 409). In this condition, the output of the second comparator CM _2 is pulled down. In the state 1, if the output a0, a1 is 10 or 01, the interpolation circuit 200 enters the state 2 (S2 in fig. 5, step 413 in fig. 4). In state 2, the first comparator CM _1 receives the phase-shifted signal corresponding to the path YA2, and the second comparator CM _2 receives the phase-shifted signal corresponding to the path YA3, as shown in fig. 3.

In addition, in state 2, the inputs of the first and second comparators CM _1 and CM _2 have changed once, and if the outputs a0 and a1 are 10 or 01, the first multiplexer MUX _1 remains in the same state (step 411 in fig. 4). Furthermore, if the outputs a0 and a1 are 11, the first multiplexer MUX _1 switches to the next state 3. If the outputs A0 and A1 are 00, the output of the first comparator CM _1 or the second comparator CM _2 is pulled up (step 413 in FIG. 4). In addition, if the output of the first comparator CM _1 or the second comparator CM _2 is pulled up so that the outputs a0 and a1 are 10 or 01, the flow returns to step 407. This step may prevent the first comparator CM _1 and the second comparator CM _2 from generating erroneous outputs due to the pull-down operation.

From the foregoing description, the steps 403-411 can be summarized as follows: if the comparison result (e.g., outputs a0, a1, B0, B1) represents that the signal value of the phase-shifted signal (e.g., INP) received by the positive terminal of the comparator is greater than the signal value of the phase-shifted signal (e.g., INM) received by the negative terminal of the comparator, the first multiplexer MUX _1 switches to the next state. In addition, when the first multiplexer MUX _1 is switched to the next state and the phase-shifted signal input to the comparator is changed, the output of the comparator is pulled down. For example, when switching from the state 1 to the state 2, the phase-shifted signal input to the second comparator CM _2 changes from the signal corresponding to YA1 to the signal corresponding to YA3, and thus the output of the second comparator CM _2 is pulled down from the state 1 to the state 2. Further, if the input of each comparator has been changed once, then the output of at least one comparator is pulled up if the outputs of both comparators are 0 (e.g., step 413 in FIG. 4).

Such rules may be applied in other states, such as steps 415, 417, 419, and 421, until all paths YA0-Y49 have been processed. It should also be noted that ideally, the pull-down timing should be the same as the timing when the positive input IMP of the first comparator CM _1 is greater than the negative input INM thereof. However, there may be some delay between these two timings. For example, as shown in FIG. 5, the timing of the first rising edge of output A0 is different from the timing of the first falling edge of output A1. The timing of the first falling edge of the output a1 is the same as the timing at which the second comparator CM _2 is pulled down for the first time.

In the embodiment of fig. 5, the first state control circuit VC _1 pulls down the output of the first comparator CM _1 or the second comparator CM _2 to improve the hysteresis problem. However, in another embodiment, the first state control circuit VC _1 may pull up the output of the first comparator CM _1 or the second comparator CM _2 to improve the hysteresis problem.

Referring to FIG. 6, waveforms of an interpolation circuit according to various embodiments of the invention are shown. Some rules for the waveforms in fig. 6 may be the opposite of those in fig. 5, for example: if the comparison result (e.g., outputs a0, a1, B0, B1) represents that the signal value of the phase-shifted signal (e.g., INP) received by the positive terminal of the comparator is less than the signal value of the phase-shifted signal (e.g., INM) received by the negative terminal of the comparator, the first multiplexer MUX _1 switches to the next state. Further, when the interpolation circuit 200 switches to the next state and the phase-shifted signal input to the comparator changes, the output of the comparator is pulled up. If the input of each comparator changes once and the outputs of both comparators are 1, the output of at least one comparator will be pulled down.

Ideally, the pull-up timing of the first comparator CM _1 should be the same as the timing when its positive input IMP is smaller than its negative input INM. However, there may be some delay between these two timings. For example, as shown in fig. 6, the timing of the first falling edge of the output a0 is different from the timing in the first rising edge of the output a1, and the timing in the first rising edge of the output a1 is the same as the first pull-up of the second comparator CM _ 2.

In other words, in the embodiment of fig. 5, if the value of the phase-shifted signal (INP) received at the first positive input terminal of the first comparator CM _1 changes from being greater than the value of the phase-shifted signal (INM) received at the first negative input terminal to being less than the value of the phase-shifted signal received at the first negative input terminal, the first voltage level compensation circuit VC _1 pulls down the output a0 to a logic value 0. In addition, if the value of the phase-shifted signal received by the first positive input terminal of the first comparator CM _1 changes from being smaller than the value of the phase-shifted signal (INM) received by the first negative input terminal to being larger than the value of the phase-shifted signal received by the first negative input terminal, the first voltage level compensation circuit VC _1 pulls up the output a0 to logic value 1. Such rules may be applied to the second comparator CM _2, the third comparator CM _3 and the fourth comparator CM _ 4.

The interpolation circuit described above may be applied to a motor control circuit. Please refer to fig. 2 again. In one embodiment, the outputs a0, a1, B0, B1 are input to the first clock generation circuit CG _1 and the second clock generation circuit CG _2, respectively, to generate the first clock signal CLKA and the second clock signal CLKB. In addition, the first clock signal CLKA and the second clock signal CLKB are input to the first state control circuit SC _1 and the second state control circuit SC _2, respectively, to generate the first control signal CHA and the second control signal CHB, respectively. The first control signal CHA and the second control signal CHB may be used to control the electric motor and may thus be regarded as first motor control signal and second motor control signal

Further, the first control signal CHA and the second control signal CHB correspond to the outputs a0, a1, B0 and B1. For example, in the embodiment of fig. 5, the rising edge of the first control signal CHA corresponds to the rising edge of the output a0, and the falling edge of the first control signal CHA corresponds to the rising edge of the output a 1. Further, in the embodiment of fig. 5, the rising edge of the second control signal CHB corresponds to the rising edge of the output B1 and the falling edge of the second control signal CHB corresponds to the rising edge of the output B0.

Further, in the embodiment of fig. 6, the rising edge of the first control signal CHA corresponds to the falling edge of the output a0, and the falling edge of the first control signal CHA corresponds to the falling edge of the output a 1. In addition, in the embodiment of fig. 6, the rising edge of the second control signal CHB corresponds to the falling edge of the output B1, and the falling edge of the second control signal CHB corresponds to the falling edge of the output B0.

FIG. 7 is a schematic diagram illustrating the operation of the interpolation circuit as a motor driving circuit. As shown in fig. 7, control signals CS _1 and CS _2 are input to the motor to control the motor. The control signals CS _1 and CS _2 are sampled at different sampling points to generate the phase shifted signals PS _11 … PS _1n, PS _21 … PS _2m and accordingly the first control signal CHA, the second control signal CHB. The first control signal CHA and the second control signal CHB correspond to sampled values of the control signals CS _1 and CS _ 2. Therefore, the interpolation circuit in the motor driving circuit disclosed in the present invention can be used to sample the control signal input to the motor and accordingly generate the first control signal CHA and the second control signal CHB for controlling the motor, so as to generate the control signals CS _1 and CS _2 by interpolation.

According to the foregoing embodiment, the output of the comparator can be compensated to improve the hysteresis problem of the comparator, so that the comparison result of the comparator can be more accurate.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.