阅读说明：本技术 半导体装置以及电力变换装置 (Semiconductor device and power conversion device ) 是由 海老原洪平 富永贵亮 于 2019-04-11 设计创作，主要内容包括：SBD(100)具备：末端阱区域(2),以包围活性区域(RI)的方式形成于漂移层(1)的表层部；场绝缘膜(3),形成为覆盖末端阱区域(2)的一部分；表面电极(5),形成于比场绝缘膜(3)靠内侧的漂移层(1)上,并与末端阱区域(2)电连接；表面保护膜(6),覆盖表面电极(5)的外侧的端部；以及背面电极(8),形成于单晶基板(31)的背面。以末端阱区域(2)的外侧的端部的位置为基准,末端区域(RO)的拐角部处的表面电极(5)的外侧的端部相比于末端区域(RO)的直线部处的表面电极(5)的外侧的端部而位于内侧。(The SBD (100) is provided with: a terminal well region (2) formed on the surface layer of the drift layer (1) so as to surround the active Region (RI); a field insulating film (3) formed so as to cover a part of the end well region (2); a surface electrode (5) formed on the drift layer (1) on the inner side of the field insulating film (3) and electrically connected to the end well region (2); a surface protection film (6) covering the outer end of the surface electrode (5); and a back surface electrode (8) formed on the back surface of the single crystal substrate (31). The outer end of the surface electrode (5) at the corner of the end Region (RO) is located more inward than the outer end of the surface electrode (5) at the straight line part of the end Region (RO) with reference to the position of the outer end of the end well region (2).)

1. A semiconductor device is characterized by comprising:

a semiconductor substrate (31);

a drift layer (1) of the 1 st conductivity type formed on the semiconductor substrate (31);

a 2 nd conductivity type end well region (2; 20) formed in an end Region (RO) outside an active Region (RI) at a surface layer portion of the drift layer (1) so as to surround the active Region (RI) in a plan view;

a field insulating film (3) formed on the drift layer (1) so as to cover a part of the end well region (2; 20);

a surface electrode (5; 50) formed on the drift layer (1) on the inner side of the field insulating film (3) and electrically connected to the end well region (2; 20);

an upper surface film (6) formed on the field insulating film (3) and the surface electrode (5; 50) and covering an outer end of the surface electrode (5; 50); and

a back surface electrode (8) formed on the back surface of the semiconductor substrate (31),

the end Region (RO) has a straight portion and a corner portion in a plan view,

the end portion on the outer side of the surface electrode (5; 50) at the corner portion of the end Region (RO) is located on the inner side than the end portion on the outer side of the surface electrode (5; 50) at the linear portion of the end Region (RO) with reference to the position of the end portion on the outer side of the end well region (2; 20).

2. The semiconductor device according to claim 1,

the outer end of the surface electrode (5; 50) is located inside the end well region (2; 20),

with respect to the distance from the end portion outside the end well region (2; 20) to the end portion outside the surface electrode (5; 50), the distance at the corner portion of the end Region (RO) is longer than the distance at the straight portion of the end Region (RO).

3. The semiconductor device according to claim 1,

the outer end of the surface electrode (5; 50) is located outside the end well region (2; 20),

as for the distance from the end portion outside the end well region (2; 20) to the end portion outside the surface electrode (5; 50), the distance at the corner portion of the end Region (RO) is shorter than the distance at the straight portion of the end Region (RO).

4. The semiconductor device according to any one of claims 1 to 3,

the semiconductor device further includes:

a well region (9) of the 2 nd conductivity type formed in a surface layer portion of the drift layer (1) of the active Region (RI);

a source region (11) of the 1 st conductivity type formed in a surface layer portion of the well region (9);

a gate insulating film (12) that covers a channel region, which is a region between the source region (11) and the drift layer (1), in the well region (9);

a gate electrode (13) formed on the gate insulating film (12); and

an interlayer insulating film (14) covering the gate electrode (13),

the surface electrode (50) comprises:

a source electrode (51) formed on the interlayer insulating film (14) and electrically connected to the source region (11) through a contact hole formed in the interlayer insulating film (14); and

and a gate wiring (52) formed on the interlayer insulating film (14) so as to surround the surface electrode (50) in a plan view, and electrically connected to the gate electrode (13) through a contact hole formed in the interlayer insulating film (14).

5. The semiconductor device according to any one of claims 1 to 4,

the semiconductor device is provided with a plurality of end well regions (2; 20) formed in a nested manner with a space therebetween.

6. The semiconductor device according to claim 5,

the surface electrode (5; 50) is electrically connected to at least one of the end well regions (2; 20).

7. The semiconductor device according to any one of claims 1 to 6,

the semiconductor substrate (31) is made of silicon carbide.

8. A power conversion device is provided with:

a main conversion circuit (2001) having the semiconductor device according to any one of claims 1 to 7, which converts and outputs input electric power;

a drive circuit (2002) that outputs a drive signal for driving the semiconductor device to the semiconductor device; and

and a control circuit (2003) for outputting a control signal for controlling the drive circuit (2002) to the drive circuit (2002).

Technical Field

The present invention relates to a semiconductor device and a power conversion device, and more particularly to a semiconductor device having a surface protective film and a power conversion device using the semiconductor device.

Background

In a vertical semiconductor device used for a power device or the like, in order to ensure a withstand voltage performance, a technique is known in which a p-type guard ring region (end well region) is provided in a so-called end region (terminal region) of an outer peripheral portion of an n-type semiconductor layer (for example, patent document 1 described below). In a semiconductor device having a guard ring region, an electric field generated when a reverse voltage is applied to a main electrode of the semiconductor device is relaxed by a depletion layer forming a pn junction between an n-type semiconductor layer and a p-type guard ring region.

In the Schottky Barrier Diode (SBD) of patent document 1, the surface electrode is covered with polyimide as a surface protective film except for a region where wire bonding is performed. Further, a sealing material such as gel may be used to seal the schottky barrier diode. Such a surface protective film and sealing material are not limited to SBDs, and can be applied to other Semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect transistors).

Documents of the prior art

Patent document 1: japanese patent laid-open publication No. 2013-211503

Disclosure of Invention

Surface protective films such as polyimide and sealing materials such as gel tend to contain moisture under high humidity. The moisture may adversely affect the surface electrode. Specifically, the surface electrode may be dissolved in water or the surface electrode may react with water to deposit an insulator. In such a case, the surface protective film is likely to be peeled off at the interface between the surface electrode and the surface protective film. The cavity below the surface protective film in the outer periphery of the surface electrode, which is generated by the peeling of the surface protective film, functions as a leakage path, and may destroy the insulation reliability of the semiconductor device.

The present invention has been made to solve the above-described problems, and an object thereof is to provide a semiconductor device with high insulation reliability.

The semiconductor device according to the present invention includes: a semiconductor substrate; a drift layer of a 1 st conductive type formed on the semiconductor substrate; a 2 nd conductivity type end well region formed in a surface layer portion of the drift layer so as to surround the active region in a plan view in an end region outside the active region; a field insulating film formed on the drift layer so as to cover a part of the end well region; a surface electrode formed on the drift layer on the inner side of the field insulating film and electrically connected to the end well region; an upper surface film formed on the field insulating film and the surface electrode, covering an outer end portion of the surface electrode; and a back surface electrode formed on the back surface of the semiconductor substrate, wherein the end region has a straight portion and a corner portion in a plan view, and the end portion of the outer side of the surface electrode at the corner portion of the end region is positioned more inside than the end portion of the outer side of the surface electrode (5; 50) at the straight portion of the end region with reference to the position of the end portion of the outer side of the end well region.

According to the semiconductor device of the present invention, it is possible to suppress the deposition of the insulator on the surface electrode at the corner portion of the end region and prevent the peeling of the upper surface film. This can contribute to improvement in insulation reliability of the semiconductor device.

The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

Drawings

Fig. 1 is a partial cross-sectional view showing the structure of a semiconductor device according to embodiment 1 of the present invention.

Fig. 2 is a plan view showing the structure of a semiconductor device according to embodiment 1 of the present invention.

Fig. 3 is a partial cross-sectional view showing the structure of a semiconductor device according to embodiment 1 of the present invention.

Fig. 4 is a plan view showing the structure of a semiconductor device according to embodiment 1 of the present invention.

Fig. 5 is a diagram illustrating an example of the shape of the surface electrode.

Fig. 6 is a diagram illustrating an example of the shape of the surface electrode.

Fig. 7 is a partial cross-sectional view showing the structure of a semiconductor device according to embodiment 1 of the present invention.

Fig. 8 is a partial cross-sectional view showing the structure of a modification of the semiconductor device according to embodiment 1 of the present invention.

Fig. 9 is a diagram for explaining an operation of the semiconductor device according to embodiment 1 of the present invention.

Fig. 10 is a partial cross-sectional view showing the structure of a semiconductor device according to embodiment 2 of the present invention.

Fig. 11 is a plan view showing the structure of a semiconductor device according to embodiment 2 of the present invention.

Fig. 12 is a partial cross-sectional view showing the structure of a unit cell of a semiconductor device according to embodiment 2 of the present invention.

Fig. 13 is a plan view showing a structure of a modification of the semiconductor device according to embodiment 2 of the present invention.

Fig. 14 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to embodiment 3 of the present invention is applied.

(symbol description)

1: a drift layer; 2: a terminal trap region; 3: a field insulating film; 5: a surface electrode; 5 a: a Schottky electrode; 5 b: an electrode pad; 6: a surface protective film; 8: a back electrode; 9: an element well region; 11: a source region; 12: a gate insulating film; 13: a gate electrode; 14: an interlayer insulating film; 19: a contact region; 20: a terminal trap region; 21: a boundary region; 21 a: a low-concentration section; 21 b: a high concentration section; 22: an extended area; 30: an epitaxial substrate; 31: a single crystal substrate (single crystal substrate); 32: an epitaxial layer; 50: a surface electrode; 51: a source electrode; 52: a gate wiring electrode; 52 p: a gate pad; 52 w: a gate wiring; s1: a back surface of the epitaxial substrate; s2: a surface of an epitaxial substrate; 100. 101: SBD; 200. 201: a MOSFET; UC: a unit cell; RI: an inner region; and (3) RO: an outer region; 1000: a power source; 2000: a power conversion device; 2001: a main conversion circuit; 2002: a drive circuit; 2003: a control circuit; 3000: and (4) loading.

Detailed Description

Hereinafter, embodiments of the present invention will be described. In this specification, an "active region" of a semiconductor device is defined as a region in which a main current flows when the semiconductor device is in an on state, and a "termination region" of the semiconductor device is defined as a region around the active region. The "outer side" of the semiconductor device means a direction from the central portion of the semiconductor device toward the outer peripheral portion, and the "inner side" of the semiconductor device means a direction opposite to the "outer side". In addition, although the description will be made assuming that the "1 st conductivity type" is an n-type and the "2 nd conductivity type" is a p-type as to the conductivity type of the impurity, the "1 st conductivity type" may be a p-type and the "2 nd conductivity type" may be an n-type, in contrast to this.

Here, the term "MOS" is used to indicate a Metal-Oxide-Semiconductor stacked structure and is obtained by using the initials of Metal-Oxide-Semiconductor. However, in a field effect transistor having a MOS structure (hereinafter, simply referred to as "MOS transistor"), in particular, from the viewpoint of recent integration, improvement in manufacturing processes, and the like, materials of a gate insulating film and a gate electrode have been improved. For example, in a MOS transistor, polysilicon is used as a material of a gate electrode instead of metal mainly from the viewpoint of forming a source and a drain in a self-aligned manner. In addition, a material having a high dielectric constant is used for the gate insulating film in order to improve electrical characteristics, but the material is not necessarily limited to an oxide.

Therefore, the term "MOS" is not necessarily used only for the metal-oxide-semiconductor stacked structure, and the same applies to the present specification. That is, in view of the common technical knowledge, "MOS" is defined as a term that includes not only a Metal-Oxide-Semiconductor abbreviation but also a conductor-insulator-Semiconductor laminate structure in a broad sense.

In the following description, even if the terms "up" and "covering" are used, the presence of an intervening object (intervening object) between the components is not prevented. For example, even if the description is "B provided on a" or "B covering a" or the like, there may be a case where another component is provided between a and B. In the following description, terms such as "upper", "lower", "side", "bottom", "front", and "back" may be used to indicate specific positions or directions, but these terms are used for convenience of description and do not relate to directions in actual use.

The drawings shown below are schematic drawings. Therefore, the sizes, positions, and mutual relationships of the elements shown in the drawings are not necessarily accurate, and can be appropriately changed. The mutual relationship between the sizes and positions of the elements shown in different drawings is not necessarily accurate, and can be appropriately changed.

In each drawing, the same reference numerals are given to components having the same names and functions as those of components shown in other drawings. Therefore, the same elements as those described with reference to other drawings may not be described in order to avoid redundant description.

< embodiment 1>

[ Structure of the device ]

Fig. 1 is a partial cross-sectional view of a Schottky Barrier Diode (SBD)100 as a semiconductor device according to embodiment 1 of the present invention. Fig. 2 is a plan view of the SBD100, and a cross-sectional view taken along the line a-a of fig. 2 in the direction of the arrow corresponds to fig. 1. The left part of fig. 1 is an active region through which a main current flows in the on state of the SBD100, and the right part of fig. 1 is an end region which is an area outside the active region of the SBD 100. Hereinafter, the region corresponding to the active region is referred to as "inner region RI", and the region corresponding to the end region is referred to as "outer region RO".

As shown in fig. 1, the SBD100 is formed using an epitaxial substrate 30 composed of a single crystal substrate 31 and an epitaxial layer 32 formed thereon. The single crystal substrate 31 is a semiconductor substrate made of n-type (1 st conductivity type) silicon carbide (SiC), and the epitaxial layer 32 is a semiconductor layer made of SiC epitaxially grown on the single crystal substrate 31. That is, SBD100 is a SiC-SBD. In the present embodiment, an epitaxial substrate 30 having a 4H polytype (4H polytype) is used. Here, the upper side of the epitaxial substrate 30 in fig. 1 is defined as the "front side", the lower side is defined as the "back side", the principal surface on the back side of the epitaxial substrate 30 is hereinafter referred to as the "back surface S1", and the principal surface on the front side is referred to as the "front surface S2".

In a surface layer portion on the surface side of the epitaxial layer 32 in the end region, an end well region 2 of p-type (2 nd conductivity type) is selectively formed. The n-type region of the epitaxial layer 32 other than the end well region 2 is a drift layer 1 through which current flows due to drift. The impurity concentration of the drift layer 1 is lower than that of the single crystal substrate 31. Therefore, the single crystal substrate 31 has a lower resistivity than the drift layer 1. Here, the impurity concentration of the drift layer 1 is 1 × 10¹⁴/cm³Above and 1 × 10¹⁷/cm³The following.

As shown by a broken line in fig. 2, the end well region 2 is a frame-shaped (ring-shaped) region surrounding the active region in a plan view, and functions as a so-called guard ring. As shown in fig. 1, the end portion on the inner side (inner peripheral side) of the end well region 2 is defined as an inner region RI which is an active region, and the outer side thereof is defined as an outer region RO which is an end region. The outer region RO is a frame-shaped region surrounding the inner region RI in plan view, and has linear portions, which are linear regions along each side of the semiconductor chip, and corner portions, which are curved regions connecting two linear portions extending in different directions.

The end well region 2 may include a plurality of regions having different impurity concentrations. The number of the end well regions 2 is not limited to 1, and a plurality of end well regions 2 arranged in a nested manner with a space therebetween may be provided in the outer region RO.

On the surface S2 of the epitaxial substrate 30, the field insulating film 3, the surface electrode 5, and the surface protective film 6 are provided. Further, the rear surface S1 of the epitaxial substrate 30 is provided with a rear surface electrode 8. In the plan view of fig. 2, the field insulating film 3 and the surface protective film 6 are not shown. The position of the end of the surface protective film 6, i.e., the outline of the surface protective film 6, is shown by a dotted line.

The field insulating film 3 covers a part of the end well region 2, and extends to the outside of the end well region 2 beyond the end portion (also referred to as "outer peripheral end") outside the end well region 2. The field insulating film 3 is made of, for example, SiO₂And SiN, and preferably has a thickness of 10nm or more. For example, SiO with a thickness of 1 μm can be used as the field insulating film 3₂And (3) a membrane.

The surface electrode 5 is provided on at least a part of the surface S2 of the epitaxial substrate 30 in the inner region RI. In the present embodiment, the front surface electrode 5 is composed of the schottky electrode 5a formed on the front surface S2 of the epitaxial substrate 30 and the electrode pad 5b formed on the schottky electrode 5a, and the end portions of the schottky electrode 5a and the electrode pad 5b are positioned on the field insulating film 3.

The schottky electrode 5a is in contact with the drift layer 1 of the inner region RI and the end well region 2 of the outer region RO. Thereby, the surface electrode 5 is electrically connected to the end well region 2. The material of the schottky electrode 5a may be any metal as long as it forms schottky junction with the drift layer 1 which is an n-type SiC semiconductor, and for example, Ti (titanium), Mo (molybdenum), Ni (nickel), Au (gold), W (tungsten), or the like may be used. The thickness of the schottky electrode 5a is preferably 30nm to 300 nm. For example, a Ti film having a thickness of 100nm can be used as the schottky electrode 5 a.

As a material of the electrode pad 5b, for example, a metal including one or more of Al (aluminum), Cu (copper), Mo, and Ni, or an Al alloy such as Al — Si (silicon) can be used. The thickness of the electrode pad 5b is preferably 300nm or more and 10 μm or less. For example, an Al film with a thickness of 3 μm can be used as the electrode pad 5 b.

The surface protective film 6 is an upper surface film provided on the field insulating film 3 and the surface electrode 5 so as to cover an end portion of the surface electrode 5. More specifically, the surface protection film 6 covers the upper surface end and end surfaces (side surfaces) of the electrode pad 5b and the end surfaces of the schottky electrode 5 a. Therefore, the outer peripheral portion of the upper surface of the electrode pad 5b is covered with the surface protective film 6. However, the central portion of the electrode pad 5b is not covered with the surface protection film 6 so as to function as an external terminal. That is, the surface protection film 6 has an opening in the inner region RI to expose the upper surface of the electrode pad 5b, as shown in fig. 1. In addition, the surface protection film 6 covers at least a part of the surface S2 of the epitaxial substrate 30 in the outside region RO.

As a material of the surface protective film 6, polyimide which is a resin insulator that relaxes stress from the outside, high-resistance silicon carbide (SiN) that can discharge external charges and the like generated in gel through an electrode, a multilayer film obtained by laminating these, and the like can be used.

As a material of the back electrode 8, a metal including one or more of Ti, Ni, Al, Cu, and Au, or the like can be used.

Here, in the SBD100 of the present embodiment, the outer end of the surface electrode 5 at the corner portion of the outer region RO is located more inward than the outer end of the surface electrode 5 at the linear portion of the outer region RO with reference to the position of the outer end (outer peripheral end) of the end well region 2. In other words, if the distance from the outer peripheral end of the end well region 2 to the outer peripheral end of the surface electrode 5 is L, when the outer peripheral end of the surface electrode 5 is located inside the outer peripheral end of the end well region 2 as shown in fig. 1, the distance L2 at the corner portion of the outer region RO is longer than the distance L1 at the linear portion of the end Region (RO) as shown in fig. 2. That is, the relationship of L2> L1 holds.

In the SBD100 of the present embodiment, as shown in fig. 3, the outer peripheral end of the surface electrode 5 may be located outside the outer peripheral end of the end well region 2. In this case, if the distance from the outer peripheral edge of the end well region 2 to the outer peripheral edge of the surface electrode 5 is L, the distance L2 at the corner portion of the outer region RO is shorter than the distance L1 at the straight portion of the outer region RO as shown in fig. 4. That is, the relationship of L1> L2 holds.

In fig. 2 and 4, the outer peripheral end of the surface electrode 5 at the corner portion of the outer region RO (end region) has a curved shape, but the shape may not be curved. For example, as shown in fig. 5, the outer peripheral end of the front surface electrode 5 may include a linear portion at the corner portion of the outer region RO. As shown in fig. 6, the outer peripheral end of the front surface electrode 5 may include a plurality of curved portions having different curved directions at the corner portions of the outer region RO.

As described above, the number of the end well regions 2 provided in the outer region RO is not limited to 1, and a plurality of end well regions 2 arranged in a nested manner with a space therebetween may be provided as shown in fig. 7, for example. The surface electrode 5 is electrically connected to at least one of the plurality of end well regions 2. In this case, the outer peripheral edge of the surface electrode 5 at the corner portion of the outer region RO is positioned more inward than the outer peripheral edge of the surface electrode 5 at the straight portion of the outer region RO with reference to the position of the outer peripheral edge of the end well region 2 electrically connected to the surface electrode 5 among the plurality of end well regions 2.

In the present embodiment, SiC is used as the material of the epitaxial substrate 30. The SiC semiconductor has a wider band gap than the Si semiconductor, and the SiC semiconductor device is superior in withstand voltage, has a higher allowable current density, and is also capable of high-temperature operation because of its high heat resistance, as compared with the Si semiconductor device. However, the material of the epitaxial substrate 30 is not limited to SiC, and may be Si or another wide band gap semiconductor such as gallium nitride (GaN).

The semiconductor device according to the present embodiment may be a diode other than the SBD, for example, a pn Junction diode or a Junction Barrier Schottky (JBS) diode.

[ modified examples ]

Fig. 8 is a cross-sectional view showing the structure of the SBD101 according to a modification of embodiment 1, and corresponds to fig. 1. In the outer region RO of the SBD101 in fig. 8, a plurality of end well regions 2 are provided in a nested manner with a space therebetween, as in fig. 7. Further, a plurality of surface electrodes 5 are provided in a nested manner so as to be connected to the plurality of end well regions 2, respectively.

In this case, in each of the plurality of surface electrodes 5 electrically connected to the end well region 2, the outer peripheral end of the surface electrode 5 at the corner portion of the outer region RO is positioned more inward than the outer peripheral end of the surface electrode 5 at the linear portion of the outer region RO with reference to the position of the outer peripheral end of the end well region 2.

[ actions ]

The operation of the SBD100 according to embodiment 1 will be described. When a negative voltage is applied to the back electrode 8 based on the potential of the front electrode 5, the SBD100 is in a state where a current flows from the front electrode 5 to the back electrode 8, that is, an on state (on state). Conversely, when a positive voltage is applied to the back electrode 8 with reference to the potential of the front electrode 5, the SBD100 is turned off (off).

When the SBD100 is in the off state, a large electric field is applied to the surface of the inner region RI (active region) of the drift layer 1 and the vicinity of the interface of the pn junction between the drift layer 1 and the end well region 2. The voltage to the back electrode 8 at which the electric field reaches the critical electric field to cause avalanche breakdown is defined as the maximum voltage (avalanche voltage) of the SBD 100. In general, the rated voltage is determined in such a manner that the SBD100 is used in a voltage range that does not cause avalanche breakdown.

In the off state of the SBD100, the depletion layer spreads from the surface of the drift layer 1 of the active region and the pn junction interface between the drift layer 1 and the end well region 2 in the direction toward the single crystal substrate 31 (downward direction) and in the direction toward the outer periphery of the drift layer 1 (right direction). Further, the depletion layer spreads from the pn junction interface between drift layer 1 and end well region 2 into end well region 2, and the spreading is largely dependent on the concentration of end well region 2. That is, if the concentration of the end well region 2 becomes high, the expansion of the depletion layer in the end well region 2 is suppressed, and the front end position of the depletion layer is a position close to the boundary between the end well region 2 and the drift layer 1. As for the front end position of the depletion layer, if the distance between the region where the surface electrode 5 and the end well region 2 are connected and the outer peripheral end of the end well region 2 is the same, the same position is obtained at both the straight portion and the corner portion of the end region.

In fig. 9, the positions of the front ends of the depletion layers that expand in the direction toward the single crystal substrate 31 (downward direction) and in the direction toward the outer periphery of the drift layer 1 (right direction) and the positions of the front ends of the depletion layers that expand into the end well region 2 in the off state of the SBD100 are shown by broken lines. That is, in the off state of the SBD100, the region between the two broken lines shown in fig. 9 is depleted. Further, the front end position of the depletion layer can be investigated by TCAD (Technology CAD, computer aided design Technology) simulation or the like. In the outer region RO, a potential difference is generated from the outer periphery side toward the center of the epitaxial layer 32 in the depleted region in the epitaxial layer 32. The undepleted region in the end well region 2 can be regarded as having substantially the same potential as the surface electrode 5.

Here, a case where the SBD100 is in an off state under high humidity is considered. The sealing resin provided in such a manner as to cover the semiconductor chip may contain moisture. For example, when the surface protection film 6 is made of a resin material having high water absorption such as polyimide, the surface protection film 6 contains a large amount of moisture under high humidity, and this moisture may reach the surfaces of the epitaxial layer 32 and the electrode pad 5 b. In the case where the surface protection film 6 is made of a material such as SiN having a high resistance, cracks are likely to occur in the surface protection film 6 around the end portions of the surface electrodes 5 due to stress or the like generated during the process, and the surface electrodes 5 may be exposed to moisture through the cracks. In this state, the edge of the drift layer 1 functions as an anode and the electrode pad 5b functions as a cathode due to the voltage applied to the SBD100 in the off state. In the vicinity of the electrode pad 5b serving as the cathode, a reduction reaction of oxygen represented by the following chemical formula (1) and a generation reaction of hydrogen represented by the following chemical formula (2) occur due to moisture.

O₂+2H₂O+4e^-→4OH^-…(1)

H₂O+e^-→OH^-+1/2H₂…(2)

Along with this, the concentration of hydroxide ions increases in the vicinity of the electrode pad 5 b. The hydroxide ions chemically react with the electrode pad 5 b. For example, when the electrode pad 5b is made of aluminum, the aluminum may be aluminum hydroxide due to the chemical reaction.

The reaction of aluminum and hydroxide ions is accelerated by the surrounding electric field strength. Since a potential gradient occurs in the depleted region in the semiconductor interior, in the SBD100 of embodiment 1, a potential gradient along the surface S2 occurs in the region where the depletion layer is exposed on the surface of the epitaxial substrate 30 (the region ER shown in fig. 9). This potential gradient continues to the field insulating film 3 and the surface protective film 6 on the surface S2 of the epitaxial layer 32, and thus an electric field occurs in the periphery of the end portion of the electrode pad 5 b. If the electric field strength at the end of the electrode pad 5b is made to be constant or higher, a reaction of aluminum hydroxide generation occurs, and the reaction is accelerated as the electric field strength increases. Further, by accurately setting the shapes, dielectric constants, resistivities, and the like of the surface electrode 5, the field insulating film 3, and the surface protective film 6, the electric field intensity at the end portion of the electrode pad 5b can be investigated by tcad (technology cad) simulation or the like.

The electric field intensity at the end of the electrode pad 5b increases as the position of the outer peripheral end of the front electrode 5 is closer to the outer periphery based on the position of the outer peripheral end of the end well region 2. Therefore, the generation of aluminum hydroxide is accelerated as the position of the outer peripheral edge of the front surface electrode 5 is closer to the outer periphery based on the position of the outer peripheral edge of the end well region 2.

In addition, since the electric field strength is generally high due to the occurrence of a two-dimensional potential gradient at the corner portion (curved portion) of the end region, aluminum hydroxide is significantly precipitated on the surface of the electrode pad 5 b. If the surface protective film 6 is pushed up by the precipitation of the aluminum hydroxide, the surface protective film 6 may be peeled off at the interface between the electrode pad 5b and the surface protective film 6.

In particular, when the epitaxial substrate 30 is made of SiC, the width of the end well region 2 and the width from the end well region 2 to the end edge of the drift layer 1 can be designed to be small by utilizing a high dielectric breakdown electric field of SiC flexibly. With such a design, the distance between the end edge portion of the drift layer 1, which becomes the anode in the off state, and the electrode pad 5b, which becomes the cathode, becomes shorter. Therefore, the electric field intensity at the end region further increases, and the generation of aluminum hydroxide at the end portion of the electrode pad 5b is promoted. As a result, the surface protective film 6 is more likely to be significantly peeled from the electrode pad 5 b.

The peeling of the surface protective film 6 may also spread over the field insulating film 3. In other words, peeling of the surface protective film 6 also occurs sometimes at the interface of the field insulating film 3 and the surface protective film 6. If a void is formed in the field insulating film 3 due to the peeling, an excessive leakage current flows due to moisture entering the void, or gas discharge is caused in the void, and thus the SBD100 may cause element destruction.

In contrast, in the SBD100 according to embodiment 1, the outer peripheral end of the surface electrode 5 at the corner portion of the end region is located inward of the outer peripheral end of the surface electrode 5 at the linear portion of the end region with reference to the position of the outer peripheral end of the end well region 2. Therefore, the electric field intensity of the end of the electrode pad 5b at the corner portion of the end region is smaller than the electric field intensity of the end of the electrode pad 5b at the linear portion of the end region. Thereby, the generation of aluminum hydroxide in the end portion of the electrode pad 5b at the corner portion of the end region is suppressed. As a result, an effect of preventing an increase in leakage current and gas discharge due to peeling of the surface protective film 6 can be obtained.

In addition, as shown in fig. 7, when a plurality of terminal well regions 2 are provided in a nested manner with a space therebetween, the electric field intensity at the end portions of the electrode pads 5b can be further reduced, and the effect of suppressing the generation of aluminum hydroxide can be further enhanced.

The effect of suppressing the generation of aluminum hydroxide at the corner portions of the end regions can also be obtained in the plurality of surface electrodes 5 included in the SBD101 according to the modification of embodiment 1 (fig. 8). In other words, in each of the plurality of surface electrodes 5 in fig. 8, with the position of the outer peripheral end of the end well region 2 as a reference, the outer peripheral end of the surface electrode 5 at the corner portion of the end region is located inward of the outer peripheral end of the surface electrode 5 at the straight portion of the end region, so that the electric field intensity at the end portion of each of the plurality of electrode pads 5b can be reduced at the corner portion. Therefore, generation of aluminum hydroxide at the end portion of the electrode pad 5b at the corner portion can be suppressed, and increase in leakage current and gas discharge due to peeling of the surface protective film 6 can be prevented.

[ production method ]

A method for manufacturing the SBD100 according to embodiment 1 will be described.

First, a low-resistance single crystal substrate 31 containing an n-type impurity at a relatively high concentration (n +) is prepared. In the present embodiment, the single crystal substrate 31 is a SiC substrate having a 4H polytype and an inclination angle of 4 degrees or 8 degrees.

Next, by performing epitaxial growth of SiC on the single crystal substrate 31, an n-type impurity concentration of 1 × 10 is formed on the single crystal substrate 31¹⁴/cm³Above and 1 × 10¹⁷/cm³The following epitaxial layer 32. Thus, an epitaxial substrate 30 composed of a single crystal substrate 31 and an epitaxial layer 32 is obtained.

Next, a resist mask having a pattern in which the formation region of the end well region 2 is opened is formed on the epitaxial layer 32 by a photolithography process. Then, p-type impurities (acceptors) such as Al or B (boron) are ion-implanted into the epitaxial layer 32 using the resist mask as an implantation mask, thereby forming a p-type termination well region 2 in the surface layer portion of the epitaxial layer 32. The dose of the end well region 2 is preferably 0.5 × 10¹³/cm²Above and 5 × 10¹³/cm²Hereinafter, for example, 1.0 × 10 can be set¹³/cm²。

The implantation energy for ion implantation is set to 100keV or more and 700keV or less when the p-type impurity is Al, for example. In this case, [ cm ] from the above dose^-2]The impurity concentration of the end well region 2 is 1 × 10¹⁷/cm³Above and 1 × 10¹⁹/cm³The following.

When a plurality of end well regions 2 are formed as shown in fig. 7 or 8, a plurality of nested openings may be formed in a resist mask as an implantation mask, and a plurality of end well regions 2 may be formed simultaneously by 1-time ion implantation. Alternatively, the plurality of end well regions 2 may be formed by repeating the formation of the implantation mask (patterning of the resist mask) and the ion implantation a plurality of times.

After the formation of the end well region 2, annealing is performed at a temperature of 1300 ℃ to 1900 ℃ in an inert gas atmosphere such as argon (Ar) gas for 30 seconds to 1 hour by using a heat treatment apparatus. By this annealing, the impurity added to the epitaxial layer 32 by ion implantation is activated.

Next, SiO with a thickness of 1 μm is formed on the surface S2 of the epitaxial substrate 30 by, for example, CVD method₂And (3) a membrane. Then, the SiO is etched by a photolithography process and an etching process₂The film is patterned to form a field insulating film 3. At this time, the field insulating film 3 is patterned into the following shape: covers a part of the end well region 2, and extends to the outer peripheral side of the end well region 2 beyond the end of the end well region 2.

Then, a material layer of the schottky electrode 5a and a material layer of the electrode pad 5b are sequentially stacked on the epitaxial layer 32 and the field insulating film 3 by, for example, a sputtering method. For example, a Ti film having a thickness of 100nm can be used as the material layer of the schottky electrode 5a, and an Al film having a thickness of 3 μm can be used as the material layer of the electrode pad 5 b.

Next, a resist mask having a pattern of the surface electrode 5 is formed on the material layer of the electrode pad 5b by a photolithography process. Then, the material layer of the electrode pad 5b and the material layer of the schottky electrode 5a are patterned using the resist mask as an etching mask, thereby obtaining the surface electrode 5 including the schottky electrode 5a and the electrode pad 5 b. At this time, the surface electrode 5 is patterned so that the outer peripheral end of the surface electrode 5 at the corner portion of the end region is located inward of the outer peripheral end of the surface electrode 5 at the linear portion of the end region with reference to the position of the outer peripheral end of the end well region 2.

In the case where a plurality of surface electrodes 5 are formed as shown in fig. 8, the material film of the schottky electrode 5a and the material film of the electrode pad 5b are patterned so as to be divided into a plurality of pieces.

Dry etching or wet etching can be used for etching the material layer of the electrode pad 5b and the material layer of the schottky electrode 5 a. In the case of wet etching, hydrofluoric acid (HF) or phosphoric acid-based etching solutions can be used as the etching solution.

Further, the schottky electrode 5a and the electrode pad 5b may be patterned separately. In this case, the position of the edge of the schottky electrode 5a and the position of the edge of the electrode pad 5b may be shifted from each other. For example, the edge of the electrode pad 5b may be protruded from the edge of the schottky electrode 5a so that the electrode pad 5b completely covers the schottky electrode 5 a. Alternatively, the edge of the schottky electrode 5a may be protruded from the edge of the electrode pad 5b so that a part of the schottky electrode 5a is not covered with the electrode pad 5 b.

Next, a resin layer as a material layer of the surface protective film 6 is formed on the surface S2 of the epitaxial substrate 30 so as to cover the field insulating film 3 and the surface electrode 5. The resin layer can be formed by, for example, applying a photosensitive polyimide. Next, the resin layer is patterned by a photolithography process, thereby forming the surface protective film 6. At this time, the surface protective film 6 on the central portion of the surface electrode 5 serving as the external connection terminal is removed. In the outer region RO, the surface protective film 6 is patterned so that the surface protective film 6 covers the edge of the surface electrode 5 and covers at least a part of the outer region RO.

Finally, the rear electrode 8 is formed on the rear surface S1 of the epitaxial substrate 30 by, for example, a sputtering method, thereby obtaining the SBD100 shown in fig. 1.

The formation of the back surface electrode 8 may be performed before or after the formation of the material layer of the schottky electrode 5a and the material layer of the electrode pad 5 b. As a material of the back electrode 8, a metal including one or more of Ti, Ni, Al, Cu, and Au, or the like can be used. The thickness of the back electrode 8 is preferably 50nm or more and 2 μm or less. For example, a double layer film of Ti/Au having a thickness of 1 μm can be used as the back electrode 8.

[ conclusion ]

As described above, according to the SBD100 according to embodiment 1 and the SBD101 according to the modification thereof, it is possible to prevent the surface protective film 6 from peeling off by suppressing the generation of aluminum hydroxide at the end portion of the electrode pad 5b at the corner portion of the end region. Therefore, an increase in leakage current and gas discharge due to peeling of the surface protective film 6 can be prevented, and the insulation reliability of the SBD can be improved.

< embodiment 2>

[ Structure of the device ]

Fig. 10 is a partial cross-sectional view showing the structure of a MOSFET200 as a semiconductor device according to embodiment 2 of the present invention. Fig. 11 is a plan view of the MOSFET200, and a cross-sectional view along the line B-B of fig. 11 corresponds to fig. 10. Fig. 12 is a cross-sectional view showing a structure of a unit cell UC which is a minimum unit structure of the MOSFET formed in the inner region RI which is the active region. In the inner region RI of the MOSFET200, a plurality of unit cells UC shown in fig. 12 are arranged (the outermost unit cell UC is shown in the left end portion of fig. 10). In fig. 10 to 12, elements having the same functions as those of the SBD100 according to embodiment 1 shown in fig. 1 and 2 are denoted by the same reference numerals, and therefore redundant description thereof with respect to embodiment 1 is omitted here.

As shown in fig. 10, a MOSFET200 is formed using an epitaxial substrate 30 composed of a single crystal substrate 31 and an epitaxial layer 32 formed thereon. The single crystal substrate 31 is a semiconductor substrate made of n-type (1 st conductivity type) silicon carbide (SiC), and the epitaxial layer 32 is a semiconductor layer made of SiC epitaxially grown on the single crystal substrate 31. That is, MOSFET200 is a SiC-MOSFET. In the present embodiment, an epitaxial substrate 30 having a 4H polytype is used.

A p-type (2 nd conductivity type) element well region 9 is selectively formed in the surface layer portion of the epitaxial layer 32 on the front side in the active region. In addition, an n-type source region 11 and a p-type contact region 19 having an impurity concentration higher than that of the element well region 9 are selectively formed in a surface layer portion of the element well region 9.

A p-type end well region 20 is selectively formed in the surface layer portion of the epitaxial layer 32 on the front side in the end region so as to surround the active region. The end well region 20 includes: a boundary region 21 that is in contact with the boundary between the inner region RI and the outer region RO, and an extended region 22 that extends outward from the boundary region 21 so as to surround the boundary region 21 and has a lower impurity concentration than the boundary region 21. The boundary area 21 further includes: a low-concentration portion 21a having a relatively low impurity concentration, and a high-concentration portion 21b having a relatively high impurity concentration and formed in a surface layer portion of the low-concentration portion 21 a. Here, the high concentration portion 21b is not limited to a p-type, but may be an n-type.

The n-type regions of the epitaxial layer 32 other than the above impurity regions (the element well region 9, the source region 11, the contact region 19, and the end well region 20) are the drift layer 1 through which current flows due to drift. The impurity concentration of the drift layer 1 may be lower than that of the single crystal substrate 31. Therefore, the single crystal substrate 31 has a lower resistivity than the drift layer 1. Here, the impurity concentration of the drift layer 1 is 1 × 10¹⁴/cm³Above and 1 × 10¹⁷/cm³The following.

As shown by the broken line in fig. 11, the end well region 20 is a frame-shaped (ring-shaped) region surrounding the active region in plan view, and functions as a so-called guard ring. As shown in fig. 10, the end portion on the inner side (inner peripheral side) of the end well region 20 is defined as an inner region RI as an active region, and the outer side thereof is defined as an outer region RO as an end region. The outer region RO is a frame-shaped region surrounding the inner region RI in plan view, and has linear portions, which are linear regions along each side of the semiconductor chip, and corner portions, which are curved regions between adjacent linear portions.

On the surface S2 of the epitaxial substrate 30 in the active region, the gate insulating film 12 is formed so as to straddle the source region 11, the element well region 9, and the drift layer 1, and the gate electrode 13 is formed thereon. The surface layer portion of the element well region 9 covered with the gate insulating film 12 and the gate electrode 13, that is, the portion between the source region 11 and the drift layer 1 in the element well region 9 is a channel region in which an inversion channel (inversion channel) is formed when the MOSFET200 is turned on.

In the active region, the gate electrode 13 is covered with the interlayer insulating film 14, and the source electrode 51 is formed on the interlayer insulating film 14. Therefore, the gate insulating film 12 and the gate electrode 13 are electrically insulated from each other by the interlayer insulating film 14.

The source electrode 51 is connected to the source region 11 and the contact region 19 through a contact hole formed in the interlayer insulating film 14. The source electrode 51 and the contact region 19 form an ohmic contact. Further, a rear surface electrode 8 functioning as a drain electrode is formed on the rear surface S1 of the epitaxial substrate 30.

As shown in fig. 10, a part of the gate insulating film 12, the gate electrode 13, the interlayer insulating film 14, and the source electrode 51 extends to the outer region RO beyond the boundary between the inner region RI and the outer region RO. The source electrode 51 drawn out to the outer region RO is connected to the high concentration portion 21b of the end well region 20 through a contact hole formed in the interlayer insulating film 14 so as to form an ohmic contact or a schottky contact. The gate electrode 13 drawn out to the outer region RO is disposed on the high-concentration portion 21b of the end well region 20 via the gate insulating film 12, and extends like a frame in a plan view like the high-concentration portion 21 b.

Further, on the surface S2 of the epitaxial substrate 30 in the end region, the field insulating film 3, the gate wiring electrode 52, and the surface protective film 6 are provided. In the plan view of fig. 11, the field insulating film 3 and the surface protective film 6 are not shown. The position of the end of the surface protective film 6, i.e., the outline of the surface protective film 6, is shown by a dotted line.

The field insulating film 3 covers a part of the boundary region 21 of the end well region 20 and the entire extension region 22, and extends to the outside of the end well region 20 beyond the outer peripheral end of the end well region 20. In addition, the field insulating film 3 is not provided in the inner region RI. In other words, the field insulating film 3 has an opening including the inside region RI.

The gate wiring electrode 52 is formed on the interlayer insulating film 14 covering the gate electrode 13 drawn out to the outer region RO, and is connected to the gate electrode 13 through a contact hole formed in the interlayer insulating film 14. The gate wiring electrode 52 functions as an electrode that receives a gate signal (control signal) for controlling an electrical path between the source electrode 51 and the back surface electrode 8. The gate wiring electrode 52 is electrically insulated from the source electrode 51 with a space between the gate wiring electrode and the source electrode 51.

The gate wiring electrode 52 extends like a frame in a plan view, similarly to the gate electrode 13 drawn out to the outer region RO. In the present embodiment, as shown in fig. 11, the gate wiring electrode 52 includes a gate wiring 52w provided so as to surround the source electrode 51 and a gate pad 52p provided so as to enter a recess provided on one side of the rectangular source electrode 51, and the gate wiring 52w and the gate pad 52p are connected to each other. The gate wiring electrode 52 shown in fig. 10 corresponds to the gate wiring 52w of fig. 11. The gate pad 52p functions as an external terminal for inputting a gate signal. In fig. 11, the gate pad 52p is provided at a straight portion of the end region, but may be provided at a corner portion.

In the present embodiment, the surface electrode 50 includes a source electrode 51 and a gate wiring electrode 52. The surface electrode 50 is provided so as to be in contact with at least a part of the surface S2 of the inner region RI of the epitaxial substrate 30. The surface electrode 50 is formed across the entire inner region RI, and a part of the surface electrode 50 extends to the outer region RO across the boundary between the inner region RI and the outer region RO. In addition, the surface electrode 50 is provided so as to be entirely located on the interlayer insulating film 14.

In fig. 10, the inner peripheral end of the field insulating film 3 is in contact with the end face of the interlayer insulating film 14, and the gate electrode 13 and the surface electrode 50 are formed inside the inner peripheral end of the field insulating film 3. However, the interlayer insulating film 14, the gate electrode 13, and the surface electrode 50 may be formed on the field insulating film 3. In this case, the source electrode 51 is connected to the high concentration portion 21b of the end well region 20 through a contact hole penetrating both the interlayer insulating film 14 and the field insulating film 3.

The surface protective film 6 covers the source electrode 51 and the gate wiring electrode 52 at the edge of the surface electrode 50, and covers at least a part of the outer region RO of the epitaxial substrate 30. As shown in fig. 11, the surface protective film 6 has openings in the center of the source electrode 51 and in the center of the gate pad 52p, respectively. Thereby, the source electrode 51 and the gate pad 52p function as external terminals, respectively.

In the MOSFET200 of embodiment 2, the outer peripheral end of the surface electrode 50 at the corner portion of the outer region RO is located inward of the outer peripheral end of the surface electrode 50 at the straight portion of the outer region RO with reference to the position of the outer peripheral end of the end well region 20. In other words, if the distance from the outer peripheral end of the end well region 20 to the outer peripheral end of the surface electrode 50, that is, the distance from the outer peripheral end of the end well region 20 to the outer peripheral end of the gate wiring 52w is L, when the outer peripheral end of the gate wiring 52w is located inward of the outer peripheral end of the end well region 20 as shown in fig. 10, the distance L2 at the corner portion of the outer region RO is longer than the distance L1 at the straight portion of the outer region RO as shown in fig. 11. That is, the relationship of L2> L1 holds.

Although not shown, if the distance from the outer peripheral end of the end well region 20 to the outer peripheral end of the surface electrode 50, that is, from the outer peripheral end of the end well region 20 to the outer peripheral end of the gate wiring 52w is L, the distance L2 at the corner portion of the outer region RO is shorter than the distance L1 at the straight portion of the outer region RO when the outer peripheral end of the gate wiring 52w is located inward of the outer peripheral end of the end well region 20. That is, the relationship of L1> L2 holds.

In embodiment 2, as in the end well region 2 shown in fig. 7 and 8, a plurality of end well regions 20 may be provided so as to be fitted with a space therebetween. The surface electrode 50 is electrically connected to at least one of the plurality of end well regions 20.

In the present embodiment, the material of the epitaxial substrate 30 is SiC, but the material of the epitaxial substrate 30 is not limited to SiC, and may be Si or another wide band gap semiconductor such as gallium nitride (GaN).

The semiconductor device according to the present embodiment may be a Transistor other than a MOSFET, for example, a JFET (Junction field effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). In addition, although a planar transistor is illustrated in this embodiment, the transistor may be a trench transistor.

[ modified examples ]

Fig. 13 is a plan view showing the structure of a MOSFET201 according to a modification of embodiment 2, and corresponds to fig. 11. In the MOSFET201 of fig. 13, a recess provided from one side of a rectangular source electrode 51 extends to extend deep into the source electrode 51, and a gate wiring electrode 52 extends to enter the recess. In other words, in the MOSFET200 of fig. 11, only the gate pad 52p enters the recess provided on one side of the source electrode 51, and the gate wiring 52w is provided so as to surround the source electrode 51, but in the MOSFET201 of fig. 13, the elongated gate wiring 52w enters the recess of the source electrode 51, and the gate pad 52p is provided at the entrance portion of the recess.

In the MOSFET201, the outer peripheral end of the surface electrode 50 at the corner portion of the outer region RO is located inward of the outer peripheral end of the surface electrode 50 at the straight portion of the outer region RO with respect to the position of the outer peripheral end of the end well region 20. In other words, if the distance from the outer peripheral end of the end well region 20 to the outer peripheral end of the surface electrode 50, that is, the distance from the outer peripheral end of the end well region 20 to the outer peripheral end of the source electrode 51 is L, when the outer peripheral end of the source electrode 51 is positioned inside the outer peripheral end of the end well region 20, as shown in fig. 13, the distance L2 at the corner portion of the outer region RO is longer than the distance L1 at the straight portion of the outer region RO. That is, the relationship of L2> L1 holds.

Although not shown, if the distance from the outer peripheral end of the end well region 20 to the outer peripheral end of the surface electrode 50, that is, from the outer peripheral end of the end well region 20 to the outer peripheral end of the source electrode 51 is L, the distance L2 at the corner portion of the outer region RO is shorter than the distance L1 at the straight portion of the outer region RO when the outer peripheral end of the source electrode 51 is located inward of the outer peripheral end of the end well region 20. That is, the relationship of L1> L2 holds.

[ actions ]

The operation of the MOSFET200 of embodiment 2 shown in fig. 10 will be described in two states.

The 1 st state is a state in which a positive voltage equal to or higher than a threshold value is applied to the gate electrode 13, and this state is hereinafter referred to as an "on state". When the MOSFET200 is in an on state, an inversion channel is formed in the channel region. The inversion channel is a path for electrons as carriers to flow between the source region 11 and the drift layer 1. In the on state, if a high voltage is applied to the back surface electrode 8 with reference to the potential of the source electrode 51, a current flows through the single crystal substrate 31 and the drift layer 1. At this time, the voltage between the source electrode 51 and the back surface electrode 8 is referred to as "on voltage", and the current flowing between the source electrode 51 and the back surface electrode 8 is referred to as "on current". The on current flows only through the active region where the channel exists, and does not flow through the end region.

The 2 nd state is a state in which a voltage smaller than a threshold value is applied to the gate electrode 13, and this state is hereinafter referred to as an "off state". When the MOSFET200 is in the off state, no inversion channel is formed in the channel region, and therefore no on current flows. Therefore, when a high voltage is applied between the source electrode 51 and the back surface electrode 8, the high voltage is maintained. At this time, since the voltage between the gate electrode 13 and the source electrode 51 is very small with respect to the voltage between the source electrode 51 and the back surface electrode 8, a high voltage is also applied between the gate electrode 13 and the back surface electrode 8.

In the off state, a high voltage is also applied between each of the gate wiring electrode 52 and the gate electrode 13 and the back surface electrode 8 in the end region. However, similarly to the case where the element well regions 9 are electrically contacted with the source electrodes 51 in the active regions, the boundary regions 21 where the end well regions 20 are formed in the end regions are electrically contacted with the source electrodes 51, and therefore, a high electric field is prevented from being applied to the gate insulating film 12 and the interlayer insulating film 14.

The end region of the MOSFET200 functions in the same manner as the off state of the SBD100 described in embodiment 1. In other words, a high electric field is applied near the interface of the pn junction between the drift layer 1 and the end well region 20, and avalanche breakdown is caused when a voltage exceeding the critical electric field is applied to the back electrode 8. In general, the rated voltage is determined in such a manner that the MOSFET200 is used in a range that does not cause avalanche breakdown.

In the off state, the depletion layer spreads from the pn junction interface between the drift layer 1 and the element well region 9 and the end well region 20 in the direction toward the single crystal substrate 31 (downward direction) and in the outer peripheral direction of the drift layer 1 (right direction).

Here, a case where the MOSFET200 is turned off under high humidity is considered. The sealing resin provided in such a manner as to cover the semiconductor chip may contain moisture. For example, when the surface protection film 6 is made of a resin material having high water absorption such as polyimide, the surface protection film 6 contains a large amount of moisture under high humidity, and this moisture may reach the surfaces of the field insulation film 3, the interlayer insulation film 14, and the surface electrode 50. In the case where the surface protection film 6 is made of a material such as SiN having a high resistance, cracks are likely to occur in the surface protection film 6 around the end portion of the surface electrode 5 due to stress or the like generated in the process, and the surface electrode 5 may be exposed to moisture through the cracks. In this state, the edge of the drift layer 1 functions as an anode and the surface electrode 50 functions as a cathode due to the voltage applied to the MOSFET200 in the off state. In the vicinity of the surface electrode 50 serving as a cathode, a reduction reaction of oxygen represented by chemical formula (1) and a generation reaction of hydrogen represented by chemical formula (2) shown in embodiment 1 occur.

Accordingly, the concentration of hydroxide ions increases in the vicinity of the surface electrode 50 (when a negative voltage is applied to the gate wiring electrode 52, the concentration of hydroxide ions further increases in the periphery of the gate wiring electrode 52). The hydroxide ions chemically react with the surface electrode 50, and thus, an insulator is deposited on the upper surface and the side surface of the surface electrode 50 at the outer edge portion (right end in fig. 10) of the surface electrode 50.

In addition, since the electric field strength is generally high due to the occurrence of a two-dimensional potential gradient at the corner portion (curved portion) of the end region, the deposition of an insulating material is significantly generated on the surface of the surface electrode 50. If the surface protective film 6 is pushed up by the precipitation of the aluminum hydroxide, the surface protective film 6 may be peeled off at the interface between the surface electrode 50 and the surface protective film 6.

The peeling of the surface protective film 6 may also spread over the interlayer insulating film 14 and the field insulating film 3. In other words, the surface protective film 6 may be peeled off at the interface between the interlayer insulating film 14 and the field insulating film 3 and the surface protective film 6. If a void is formed in the interlayer insulating film 14 and the field insulating film 3 due to the peeling, an excessive leakage current flows due to moisture entering the void, or gas discharge is caused in the void, and the MOSFET200 may cause element breakdown.

When a void is formed between the source electrode 51 and the gate wiring electrode 52 due to the peeling of the surface protective film 6, moisture may enter the void, and an excessive leakage current may flow between the source and the gate.

In particular, when the epitaxial substrate 30 is made of SiC, the width of the end well region 2 and the width from the end well region 20 to the end edge of the drift layer 1 can be designed to be small by utilizing a high dielectric breakdown electric field of SiC flexibly. With such a design, the distance between the end edge of the drift layer 1, which becomes the anode in the off state, and the surface electrode 50, which becomes the cathode, becomes shorter. Therefore, the electric field intensity at the end region further increases, and the generation of aluminum hydroxide at the end of the surface electrode 50 is promoted. As a result, the surface protective film 6 is more likely to be significantly peeled from the surface electrode 50.

In contrast, in the MOSFET200 of embodiment 2, the outer peripheral end of the surface electrode 50 at the corner portion of the end region is located inward of the outer peripheral end of the surface electrode 50 at the linear portion of the end region with reference to the position of the outer peripheral end of the end well region 20. Therefore, the electric field intensity of the end of the surface electrode 50 at the corner portion of the end region is smaller than the electric field intensity of the end of the surface electrode 50 at the linear portion of the end region. Thereby, the generation of aluminum hydroxide at the end of the surface electrode 50 at the corner portion of the tip region is suppressed. As a result, an effect of preventing an increase in leakage current and gas discharge due to peeling of the surface protective film 6 can be obtained.

The surface electrode 50 included in the MOSFET201 according to the modification (fig. 13) of embodiment 2 also has an effect of suppressing the generation of aluminum hydroxide at the corner portions of the end regions. In other words, the outer peripheral end of the source electrode 51 at the corner portion of the end region is positioned more inward than the outer peripheral end of the source electrode 51 at the linear portion of the end region with reference to the position of the outer peripheral end of the end well region 20, so that the electric field intensity at the end portion of the source electrode 51 at the corner portion of the end region can be made smaller than the electric field intensity at the end portion of the source electrode 51 at the linear portion of the end region. Therefore, generation of aluminum hydroxide at the end portion of the source electrode 51 at the corner portion can be suppressed, and increase in leakage current and gas discharge due to peeling of the surface protective film 6 can be prevented.

[ production method ]

Next, a method for manufacturing the MOSFET200 of embodiment 2 will be described.

First, a low-resistance single crystal substrate 31 containing n-type impurities at a high concentration (n +) is prepared. In the present embodiment, the single crystal substrate 31 is a SiC substrate having a 4H polytype and an inclination angle of 4 degrees or 8 degrees.

Next, SiC is epitaxially grown on the single crystal substrate 31, thereby forming an n-type impurity concentration of 1 × 10 on the single crystal substrate 31¹⁴/cm³Above and 1 × 10¹⁷/cm³The following epitaxial layer 32. This makes it possible to obtain an epitaxial substrate 30 composed of a single crystal substrate 31 and an epitaxial layer 32.

Next, a photolithography process for forming a resist mask and an ion implantation process for forming an impurity region in a surface layer portion of the epitaxial layer 32 by ion implantation using the resist mask as an implantation mask are repeatedly performed, thereby forming the end well region 20, the element well region 9, the contact region 19, and the source region 11 in the epitaxial layer 32.

In the ion implantation, N (nitrogen) or the like is used as an N-type impurity, and Al, B or the like is used as a p-type impurity. The low-concentration portions 21a of the element well regions 9 and the end well regions 20 can be collectively formed by the same ion implantation step. In addition, the high concentration portions 21b of the contact region 19 and the end well region 20 can be formed in a batch manner by the same ion implantation step.

The impurity concentrations of the low-concentration portions 21a of the element well region 9 and the end well region 20 are preferably 1.0 × 10¹⁸/cm³Above and 1.0X 10²⁰/cm³The following. The impurity concentration of the source region 11 is preferably 1.0 × 10 in a range higher than the impurity concentration of the element well region 9¹⁹/cm³Above and 1.0X 10²¹/cm³The following. The dose of the contact region 19 and the extension region 22 of the end well region 20 is preferably 0.5 × 10¹³/cm²Above and 5 × 10¹³/cm²The lower is, for example, 1.0X 10¹³/cm²。

The implantation energy for ion implantation is, for example, 100keV or more and 700keV or less when the impurity is Al. In this case, [ cm ] from the above dose^-2]The impurity concentration of the extended region 22 obtained by conversion is 1 × 10¹⁷/cm³Above and 1 × 10¹⁹/cm³The following. In addition, when the impurity is N, the implantation energy of the ion implantation is, for example, 20keV or more and 300keV or less.

Then, annealing at 1500 ℃ or higher is performed by a heat treatment apparatus. Thereby, the impurity added by the ion implantation is activated.

Next, SiO with a thickness of 0.5 μm or more and 2 μm or less is formed on the surface S2 of the epitaxial substrate 30 by, for example, a CVD method₂And (3) a membrane. Then, the SiO is etched by a photolithography process and an etching process₂The film is patterned to form a field insulating film 3. At this time, the field insulating film 3 is patterned into the following shape: the end well region 20 covers a part thereof and extends beyond the end of the end well region 20 to the outer periphery of the end well region 2.

Next, the surface of the epitaxial layer 32 not covered with the field insulating film 3 is thermally oxidized, thereby forming SiO as the gate insulating film 12₂And (3) a membrane. Then, a polysilicon film having conductivity is formed on the gate insulating film 12 by a reduced pressure CVD method, and the polysilicon film is patterned by a photolithography step and an etching step, thereby forming the gate electrode 13. At this time, the gate electrode 13 may be formed so as to be located on the field insulating film 3.

Thereafter, SiO as the interlayer insulating film 14 was formed by CVD₂And (3) a membrane. Then, through the photolithography step and the etching step, contact holes are formed which penetrate the gate insulating film 12 and the interlayer insulating film 14 and reach the contact region 19, the source region 11, and the high concentration portion 21b of the end region, respectively. In this step, a contact hole penetrating the interlayer insulating film 14 to reach the gate electrode 13 is formed in the end region, and the interlayer insulating film 14 on the field insulating film 3 and at the end edge portion of the epitaxial layer 32 is removed.

Next, a material layer of the surface electrode 50 is formed on the surface S2 of the epitaxial substrate 30 by a sputtering method, an evaporation method, or the like. In addition, a material layer of the back electrode 8 is formed on the back surface S1 of the epitaxial substrate 30 by the same method.

As a material of the surface electrode 50, for example, a metal containing one or more of Ti, Ni, Al, Cu, and Au, or an Al alloy such as Al — Si, or the like can be used. As a material of the back electrode 8, for example, a metal containing one or more of Ti, Ni, Al, Cu, and Au is used. In the epitaxial substrate 30, a silicide film may be formed in advance by heat treatment in a portion in contact with the front surface electrode 50 or the back surface electrode 8. The formation of the back electrode 8 may be performed at the end of all steps.

Next, the surface electrode 50 is patterned by a photolithography step and an etching step, and the surface electrode 50 is separated into a source electrode 51 and a gate wiring electrode 52. At this time, the surface electrode 50 is patterned so that the outer peripheral end of the surface electrode 50 at the corner portion of the end region is located inward of the outer peripheral end of the surface electrode 50 at the linear portion of the end region with reference to the position of the outer peripheral end of the end well region 20.

Finally, the surface protection film 6 is formed so as to cover the edge portion of the surface electrode 50 and at least a part of the outer region RO of the epitaxial substrate 30, thereby obtaining the MOSFET200 shown in fig. 10. The surface protective film 6 is processed into a desired shape by, for example, coating and exposure of photosensitive polyimide.

[ conclusion ]

As described above, according to the MOSFET200 according to embodiment 2 and the MOSFET201 according to the modification thereof, it is possible to suppress the generation of aluminum hydroxide at the end of the surface electrode 50 at the corner portion of the end region, thereby preventing the peeling of the surface protective film 6. Therefore, an increase in leakage current and gas discharge due to the peeling of the surface protective film 6 can be prevented, and the insulation reliability of the MOSFET can be improved.

< embodiment 3>

This embodiment is an embodiment in which the semiconductor devices according to embodiments 1 and 2 are applied to a power conversion device. Hereinafter, as embodiment 3, a case will be described in which the semiconductor devices according to embodiments 1 and 2 are applied to a three-phase inverter.

Fig. 14 is a block diagram schematically showing the configuration of a power conversion system to which the power conversion device 2000 according to the present embodiment is applied.

The power conversion system shown in fig. 14 includes a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a dc power supply and supplies dc power to the power conversion device 2000. The power supply 1000 may be configured by various power supplies, for example, a DC system, a solar cell, or a battery, or may be configured by a rectifier circuit or an AC/DC converter connected to an AC system. The power supply 1000 may be configured by a DC/DC converter that converts DC power output from the DC system into predetermined power.

The power conversion device 2000 is a three-phase inverter connected between the power supply 1000 and the load 3000, and converts dc power supplied from the power supply 1000 into ac power to supply ac power to the load 3000. As shown in fig. 14, the power conversion device 2000 includes: a main conversion circuit 2001 for converting dc power into ac power and outputting the ac power; a drive circuit 2002 that outputs a drive signal for driving each switching element of the main conversion circuit 2001; and a control circuit 2003 which outputs a control signal for controlling the drive circuit 2002 to the drive circuit 2002.

Load 3000 is a three-phase motor driven by ac power supplied from power conversion device 2000. The load 3000 is not limited to a specific application, and is used as a motor mounted on various electric devices, for example, a motor for a hybrid car, an electric car, a railway vehicle, an elevator, or an air conditioner.

Hereinafter, the power conversion device 2000 will be described in detail. Main conversion circuit 2001 includes a switching element and a flywheel diode (not shown), and the switching element converts dc power supplied from power supply 1000 into ac power by switching, and supplies the ac power to load 3000. The main conversion circuit 2001 has various specific circuit configurations, and the main conversion circuit 2001 according to the present embodiment is a 2-level three-phase full bridge circuit and can be configured by 6 switching elements and 6 freewheeling diodes connected in anti-parallel to the respective switching elements. The semiconductor device according to any of embodiments 1 and 2 is applied to at least any of the switching elements and the free wheel diodes of the main conversion circuit 2001. The 6 switching elements are connected in series for every two switching elements to form upper and lower arms, and each upper and lower arm forms each phase (U-phase, V-phase, W-phase) of the full bridge circuit. Then, the output terminals of the upper and lower arms, that is, 3 output terminals of the main conversion circuit 2001 are connected to the load 3000.

The drive circuit 2002 generates a drive signal for driving the switching elements of the main conversion circuit 2001, and supplies the drive signal to the control electrodes of the switching elements of the main conversion circuit 2001. Specifically, a drive signal for turning the switching element on and a drive signal for turning the switching element off are output to the control electrode of each switching element in accordance with a control signal from a control circuit 2003 described later. When the switching element is maintained in the on state, the drive signal is a voltage signal (on signal) larger than the threshold voltage of the switching element, and when the switching element is maintained in the off state, the drive signal is a voltage signal (off signal) smaller than the threshold voltage of the switching element.

The control circuit 2003 controls the switching elements of the main conversion circuit 2001 so as to supply a desired electric power to the load 3000. Specifically, the time (on time) for which each switching element of the main converter circuit 2001 should be turned on is calculated from the power supplied to the load 3000. For example, the main conversion circuit 2001 can be controlled by Pulse Width Modulation (PWM) control for modulating the on time of the switching element in accordance with a voltage to be output. Then, a control command (control signal) is output to the drive circuit 2002 so that the switching element that is turned on at each time point outputs an on signal and the switching element that is turned off outputs an off signal. The drive circuit 2002 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element in accordance with the control signal.

In the power conversion device according to the present embodiment, the semiconductor device according to embodiment 1 can be applied as the flywheel diode of the main conversion circuit 2001. In the power conversion device according to the present embodiment, the semiconductor device according to embodiment 2 can be applied as the switching element of the main conversion circuit 2001. In this way, when the semiconductor devices according to embodiments 1 and 2 are applied to the power conversion device 2000, they are usually embedded in gel, resin, or the like, but these materials are not able to completely isolate moisture, and the insulation protection of the semiconductor devices is maintained by the structures shown in embodiments 1 and 2. This can improve reliability.

In this embodiment, an example in which the semiconductor devices according to embodiments 1 and 2 are applied to a 2-level three-phase inverter is described, but the application of the semiconductor devices according to embodiments 1 and 2 is not limited thereto, and the semiconductor devices can be applied to various power conversion devices. In the present embodiment, a 2-level power converter is used, but a power converter may be a multi-level power converter such as a 3-level power converter. In addition, when power is supplied to a single-phase load, the semiconductor devices according to embodiments 1 and 2 may be applied to a single-phase inverter. In addition, the semiconductor devices according to embodiments 1 and 2 can be applied to a DC/DC converter or an AC/DC converter when power is supplied to a DC load or the like.

The power conversion device to which the semiconductor device according to embodiments 1 and 2 is applied is not limited to a power conversion device used when a load is a motor, and can be used as a power supply device for, for example, a discharge machine, a laser machine, an induction heating cooker, or a non-contactor power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, or the like.

In addition, the present invention can freely combine the respective embodiments within the scope of the invention, or appropriately modify or omit the respective embodiments.

Although the present invention has been described in detail, the above description is only exemplary in all aspects, and the present invention is not limited thereto. It is understood that numerous modifications not illustrated can be devised without departing from the scope of the invention. For example, it is also conceivable to modify, add or omit an arbitrary component, and extract at least one component in at least one embodiment and combine it with components in other embodiments.

In addition, as long as no contradiction occurs, the constituent elements described as having "1" in the above embodiments may be provided with "1 or more". The constituent elements constituting the invention are conceptual units, and 1 constituent element may include a plurality of structures, or 1 constituent element may be a part of a certain structure. The structural elements of the present invention include structures having other structures or shapes as long as they exhibit the same functions.