阅读说明：本技术 延迟锁相环及其延迟线锁定方法、装置、介质及系统 (Delay locked loop and method, device, medium and system for locking delay line thereof ) 是由 武金玉 王颀 付祥 杨诗洋 鲁岩 丁玲 于 2021-08-20 设计创作，主要内容包括：本申请提供了一种延迟锁相环及其延迟线锁定方法、装置、介质及系统,方法包括：获取包括延迟锁相环的系统的条件参数和预先存储的锁定值；在预先存储的锁定值中确定条件参数对应的初始锁定值；以及响应于根据初始锁定值确定出延迟锁相环的延迟线满足锁定条件,对当前的延迟线进行锁定。通过预先存储多个延迟线的锁定值,并结合系统的条件参数选择适合系统的锁定值开始调整延迟线,使得初始锁定值尽可能地接近系统最终的锁定值,大大减少延迟线的调整次数,从而减少延迟线的锁定时间,进而减少系统运行时时钟信号不同步的时间,尽可能地减小对系统运行的影响。(The application provides a delay locked loop and a method, a device, a medium and a system for locking a delay line thereof, wherein the method comprises the following steps: acquiring condition parameters and a pre-stored locking value of a system comprising a delay locked loop; determining an initial locking value corresponding to the condition parameter in the pre-stored locking values; and locking the current delay line in response to determining that the delay line of the delay locked loop meets the locking condition according to the initial locking value. The locking values of a plurality of delay lines are stored in advance, and the locking value suitable for the system is selected by combining the condition parameters of the system to start adjusting the delay lines, so that the initial locking value is as close to the final locking value of the system as possible, the adjusting times of the delay lines are greatly reduced, the locking time of the delay lines is reduced, the time of clock signal asynchronization during the operation of the system is further reduced, and the influence on the operation of the system is reduced as much as possible.)

1. A method for delay line locking in a delay locked loop, the method comprising:

acquiring condition parameters and a pre-stored locking value of a system comprising the delay-locked loop;

determining an initial locking value corresponding to the condition parameter from the pre-stored locking values; and

and locking the current delay line in response to determining that the delay line of the delay-locked loop meets the locking condition according to the initial locking value.

2. The method of claim 1, wherein the step of obtaining a condition parameter and a pre-stored lock value of a system including the delay locked loop comprises:

after the system is powered on, acquiring condition parameters of the system and locking values pre-stored in a nonvolatile memory of the system.

3. The method of claim 1, wherein the step of obtaining a condition parameter and a pre-stored lock value of a system including the delay locked loop comprises:

before the system is powered on, acquiring condition parameters of the system and locking values pre-stored in a non-volatile memory of the system.

4. A method according to any of claims 1-3, characterized in that the condition parameters comprise at least one of the following: operating frequency, process-voltage-temperature, path delay.

5. The method of claim 1, wherein locking the current delay line comprises:

carrying out delay adjustment on an input signal of the system according to a delay line corresponding to the initial locking value to obtain an output signal; and

and determining that the current delay line meets a locking condition and locking the current delay line in response to the phase difference between the input signal and the output signal being less than or equal to a preset value.

6. The method of claim 5, wherein locking the current delay line further comprises:

and responding to the fact that the phase difference between the input signal and the output signal is larger than the preset value, adjusting the initial locking value to an adjusted locking value, and continuing to perform delay adjustment on the input signal according to a delay line corresponding to the adjusted locking value.

7. The method of claim 5 or 6, further comprising:

acquiring a current locking value when the current delay line is locked; and

and updating the corresponding lock value in the nonvolatile memory of the system according to the current lock value.

8. The method of claim 7, wherein determining an initial lock value corresponding to the condition parameter among the pre-stored lock values comprises:

and acquiring the last updated locking value of the system as the initial locking value.

9. The method of claim 1, wherein determining an initial lock value corresponding to the condition parameter among the pre-stored lock values comprises:

and determining an initial locking value corresponding to the condition parameter of the system in the pre-stored locking values according to a preset corresponding table of the condition parameter of different systems and each locking value.

10. The method of any of claims 1-3, 5-6, and 8-9, wherein the pre-stored lock value comprises:

locking values corresponding to condition parameters of different systems, which are pre-stored by the system when the system leaves a factory, and/or,

lock values that are updated each time the system runs.

11. A delay line locking apparatus of a delay locked loop, the apparatus comprising:

the parameter acquisition module is used for acquiring condition parameters of a system comprising the delay-locked loop and a pre-stored locking value;

a locking value determining module, configured to determine an initial locking value corresponding to the condition parameter from the pre-stored locking values; and

and the delay line locking module is used for locking the current delay line in response to the fact that the delay line of the delay phase-locked loop meets the locking condition determined according to the initial locking value.

12. A delay locked loop comprising: phase detector, delay line and delay line controller, characterized in that, the delay locked loop still includes: a non-volatile memory and an initial value controller;

the non-volatile memory is used for storing a lock value sent by the delay line controller and used for the delay line and sending the stored lock value to the initial value controller;

the initial value controller is used for acquiring condition parameters of a system comprising the delay-locked loop and the stored locking values, selecting a matched initial locking value from the stored locking values according to an initial signal sent by the phase detector, and feeding back the initial locking value to the delay line controller;

and the delay line controller is used for locking the current delay line in response to the fact that the delay line of the delay phase-locked loop meets the locking condition according to the initial locking value.

13. The delay locked loop of claim 12, wherein the initial value controller is further configured to:

after the system is powered on, acquiring condition parameters of the system and locking values pre-stored in a nonvolatile memory of the system.

14. The delay locked loop of claim 12, wherein the initial value controller is further configured to:

before the system is powered on, acquiring condition parameters of the system and locking values pre-stored in a non-volatile memory of the system.

15. A delay locked loop according to any of claims 12-14, characterized in that said condition parameter comprises at least one of: operating frequency, process-voltage-temperature, path delay.

16. The delay locked loop of claim 12, wherein the delay line controller is further configured to:

carrying out delay adjustment on an input signal of the system according to a delay line corresponding to the initial locking value to obtain an output signal; and

and determining that the current delay line meets a locking condition and locking the current delay line in response to the phase difference between the input signal and the output signal being less than or equal to a preset value.

17. The delay locked loop of claim 16 wherein the delay line controller is further configured to:

and responding to the fact that the phase difference between the input signal and the output signal is larger than the preset value, adjusting the initial locking value to an adjusted locking value, and continuing to perform delay adjustment on the input signal according to a delay line corresponding to the adjusted locking value.

18. The delay locked loop of claim 16 or 17, wherein the delay line controller is further configured to:

acquiring a current locking value when the current delay line is locked; and

and updating the corresponding lock value in the nonvolatile memory of the system according to the current lock value.

19. The delay locked loop of claim 18 wherein the initial value controller is further configured to:

and acquiring the last updated locking value of the system as the initial locking value.

20. The delay locked loop of claim 12, wherein the initial value controller is further configured to:

and determining an initial locking value corresponding to the condition parameter of the system in the pre-stored locking values according to a preset corresponding table of the condition parameter of different systems and each locking value.

21. A delay locked loop according to any of claims 12-14, 16-17 and 19-20, wherein the pre-stored lock value comprises:

locking values corresponding to condition parameters of different systems, which are pre-stored by the system when the system leaves a factory, and/or,

lock values that are updated each time the system runs.

22. A non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the delay line locking method of a delay locked loop according to any one of claims 1 to 10.

23. A delay locked system comprising a controller, a non-volatile memory and a delay locked loop as claimed in any one of claims 12 to 21;

after receiving a delay line control signal sent by the nonvolatile memory, the controller forwards the delay line control signal to the delay locked loop;

and the delay phase-locked loop locks the delay line according to the delay line control signal and sends a locking value to the nonvolatile memory for storage through a new delay line control signal.

Technical Field

The present invention relates to the field of clock signal synchronization of digital systems, and more particularly, to a delay locked loop, and a method, an apparatus, a medium, and a system for locking a delay line thereof.

Background

With the rapid development of Complementary Metal Oxide Semiconductor (CMOS) processes, the sizes of devices used in various digital circuits using CMOS processes are continuously decreasing, the complexity of digital circuits is continuously increasing, and the operating speed of digital systems used in data circuits, such as a central processing unit (cpu) system or a digital signal processing system, is also several hundred mhz or even higher. High speed digital systems such as these place stringent requirements on the clock signal, however, due to manufacturing process and environmental constraints, the clock signal in the system tends to be difficult to meet the requirements of the high speed digital system.

In order to overcome the deviation of the clock signal after a period of time, the related art proposes a Delay-locked Loop (DLL) circuit for performing Delay adjustment on the clock signal to achieve synchronization of the clock signal in the system. The DLL circuit reduces the phase difference between an input clock signal and an output clock signal in the system by arranging the delay line, and enables the phase difference between the input clock signal and the output clock signal to be zero by continuously adjusting the delay line, and at the moment, the delay line is locked, so that the clock signals of the system in subsequent operation can be synchronized.

In the related art, in performing the delay line adjustment, the adjustment is usually started from a fixed initial value, for example, from a median of 10000 delay control words, and then the Phase difference between the input clock signal and the output clock signal is compared by a Phase Detector (PD) until the Phase difference between the input clock signal and the output clock signal is zero, the adjustment is stopped and the delay line is locked. The locking time (the time from the start of adjusting the delay line to the time of locking the delay line) used in this way is often longer, that is, the time when the clock signals are not synchronized when the system is running is longer, which often affects the normal running of the system.

Disclosure of Invention

The present application provides a delay locked loop and a method, an apparatus, a medium, and a system for locking a delay line thereof, which can solve or at least partially solve some of the above problems or other problems of the related art.

A first aspect of the present application provides a method for locking a delay line of a delay locked loop, including: acquiring condition parameters and a pre-stored locking value of a system comprising a delay locked loop; determining an initial locking value corresponding to the condition parameter in the pre-stored locking values; and locking the current delay line in response to determining that the delay line of the delay locked loop meets the locking condition according to the initial locking value.

A second aspect of the present application provides a delay line locking apparatus of a delay locked loop, including: the parameter acquisition module is used for acquiring condition parameters and pre-stored locking values of a system comprising a delay locked loop; the locking value determining module is used for determining an initial locking value corresponding to the condition parameter in the pre-stored locking values; and the delay line locking module is used for locking the current delay line in response to the fact that the delay line of the delay phase-locked loop meets the locking condition determined according to the initial locking value.

A third aspect of the present application provides a delay locked loop, comprising: phase detector, delay line and delay line controller, the delay locked loop still includes: a non-volatile memory and an initial value controller; the nonvolatile memory is used for storing the locking value of the delay line sent by the delay line controller and sending the stored locking value to the initial value controller; the initial value controller is used for acquiring condition parameters of a system comprising a delay phase-locked loop and stored locking values, selecting matched initial locking values from the stored locking values according to an initial signal sent by the phase detector, and feeding back the initial locking values to the delay line controller; and the delay line controller is used for locking the current delay line in response to the fact that the delay line of the delay phase-locked loop meets the locking condition according to the initial locking value.

A fourth aspect of the present application provides a storage medium having stored thereon a computer program that, when executed by a processor, implements the delay line locking method of a delay locked loop of any of the embodiments of the present application.

A fifth aspect of the present application provides a delay locked system comprising a controller, a non-volatile memory, and a delay locked loop as described in the third aspect above; after receiving a delay line control signal sent by a nonvolatile memory, the controller forwards the delay line control signal to a delay phase-locked loop; the delay locked loop locks the delay line according to the delay line control signal and sends a locking value to the nonvolatile memory for storage through a new delay line control signal.

According to the delay locked loop and the method, the device, the medium and the system for locking the delay line of the delay locked loop, the locking values of a plurality of delay lines are stored in advance, the locking value suitable for the system is selected by combining the condition parameters of the system, and the delay line is adjusted, so that the initial locking value is as close as possible to the final locking value of the system, the adjustment times of the delay line are greatly reduced, the locking time of the delay line is reduced, the time of clock signal asynchronization during the operation of the system is further reduced, and the influence on the operation of the system is reduced as much as possible.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:

FIG. 1 is a schematic diagram of a circuit configuration of a delay locked loop according to an embodiment of the present application;

fig. 2 is a schematic circuit diagram of a related art delay locked loop;

fig. 3 is a flowchart illustrating a delay line locking method of a related art delay locked loop;

FIG. 4 is a flow chart illustrating a method for locking a delay line of a delay locked loop according to an embodiment of the present application;

fig. 5 is a flowchart illustrating a method for locking a delay line of a delay locked loop according to another embodiment of the present application;

fig. 6 is a flowchart illustrating a method for locking a delay line of a delay locked loop according to another embodiment of the present application;

fig. 7 is a schematic diagram of an overall structure of a delay line locking method of a delay locked loop according to an embodiment of the present application;

fig. 8 is a schematic diagram of a delay line locking apparatus of a delay locked loop according to an embodiment of the present application;

FIG. 9 is a block diagram of an electronic device for implementing the electronic device or for supporting the operation of a readable storage medium and a computer program product according to one embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in the present description, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not indicate any limitation on the features, and do not particularly indicate any precedence order. Thus, for example, a first side discussed in this application may also be referred to as a second side, and a first window may also be referred to as a second window, or vice versa, without departing from the teachings of this application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Further, in this application, when "connected" or "coupled" is used, it may mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or can be inferred from the context.

Fig. 1 is a schematic circuit diagram of a delay locked loop according to an embodiment of the present application. As shown in fig. 1, the delay locked loop 100 according to this embodiment includes: a phase detector 101, a delay line 102, a delay line controller 103, a nonvolatile memory 104, and an initial value controller 105.

The phase detector 101 is configured to generate an initial signal after the system is powered on and feed back the initial signal to the initial value controller 105, and the phase detector 101 is further configured to compare the received output clock signal with the received input clock signal, and send an adjustment signal to the delay line controller 103 after determining that a phase difference exists between the output clock signal and the input clock signal.

The delay line 102 is a unit for performing delay adjustment on an input clock signal in a Delay Locked Loop (DLL), and the input clock signal is output after being subjected to delay adjustment through the delay line 102 to obtain an output clock signal.

The delay line controller 103 is used to control the delay line 102 of the DLL according to an initial lock value fed back by the initial value controller 105 or an adjustment signal fed back by the phase detector 101.

The non-volatile memory 104 is used to store a plurality of lock values, including: locking values corresponding to condition parameters of different systems, which are pre-stored when the system leaves a factory, and/or locking values which are updated when the system runs every time.

The initial value controller 105 is used to start delay line control according to an initial signal fed back by the phase detector 101, then selects a matched initial lock value from the non-volatile memory 104 through a controller (not shown in fig. 1) outside the DLL, and receives a delay line control signal fed back by the controller, and then the initial value controller 105 forwards the delay line control signal to the delay line controller 103, so that the delay line controller 103 determines an initial lock value according to the delay line control signal and controls the delay line 102 of the DLL to start adjustment from the initial lock value.

Specifically, after the system is powered on, the phase detector 101 generates an initial signal and feeds the initial signal back to the initial value controller 105; then the initial value controller 105 starts delay line control according to the initial signal fed back from the phase detector 101, receives the delay line control signal fed back from the external controller, which indicates the selection of the matched initial lock value from the nonvolatile memory 104; then the initial value controller 105 forwards the delay line control signal to the delay line controller 103, and after receiving the delay line control signal, the delay line controller 103 determines a matched initial locking value; finally, the delay line controller 103 controls the delay line 102 of the DLL according to the initial lock value or the adjustment signal fed back from the phase detector 101 so that the input clock signal becomes the output clock signal output after passing through the delay line 102 and the forward transmission line in each clock cycle. During each clock cycle, the feedback transmission line collects the output clock signal output through the delay line 102, then outputting the collected output clock signal as a feedback clock signal to the phase detector 101, comparing the received output clock signal with the input clock signal by the phase detector 101, determining that the output clock signal and the input clock signal have a phase difference, sends a control signal to the delay line controller 103, outputs an adjustment signal from the delay line controller 103, the delay line 102 is adjusted so that the input clock signal passing through the adjusted delay line is further delay adjusted until the phase detector 101 detects that there is no phase deviation between the received output adjustment signal and the input clock signal, at which time the delay line 102 is locked, i.e., the delay adjustment of the input clock signal by the delay line 102 is maintained. During the delay adjustment by the delay line controller 103, both the input clock signal and the output clock signal are input to the phase detector 101 through the amplifier so that the phase detector 101 can accurately detect.

As for the circuit structure diagram of the delay locked loop in the related art as shown in fig. 2, the delay locked loop 200 only includes: a phase detector 201, a delay line 202 and a delay line controller 203. Wherein the input clock signal becomes the output clock signal output after passing through the delay line 202 and the forward transmission line in each clock cycle. During each clock cycle, the feedback transmission line collects the output clock signal output through the delay line 202, then, the collected output clock signal is outputted to the phase detector 201 as a feedback clock signal, the phase detector 201 compares the received output clock signal with the input clock signal, and after determining that there is a phase difference between the output clock signal and the input clock signal, sends a control signal to the delay line controller 203, outputs an adjustment signal from the delay line controller 203, the delay line 202 is adjusted so that the input clock signal is further delay adjusted by the adjusted delay line 202 until the phase detector 201 detects that there is no phase deviation between the received output adjustment signal and the input clock signal, at which time the delay line 202 is locked, i.e., the current delay adjustment of the input clock signal by the delay line 202 is maintained.

In a specific implementation, referring to a flowchart of a delay line locking method 300 of a delay locked loop provided in the related art shown in fig. 3, when a Delay Locked Loop (DLL) starts to adjust a delay line 202 (not shown in fig. 3), an input clock signal and an output clock signal adjusted by delay line delay are fed back to a phase detector 201, the phase detector 201 compares the output clock signal and the input clock signal to generate a comparison signal comp and an adjustment signal trim, where the comparison signal comp represents a comparison result of phases of the output clock signal and the input clock signal, when comp is equal to 0, it represents that a phase difference between the output clock signal and the input clock signal is not zero, and when comp is equal to 1, it represents that a phase difference between the output clock signal and the input clock signal is zero; generating the trim signal trim indicates that the delay line needs to be adjusted, i.e. when comp is 0, the trim signal trim is generated. When the trim signal trim is generated, the phase difference between the output clock signal and the input clock signal is not zero, and the delay line needs to be further adjusted, and the number of times of adjustment of the delay line is counted by the counter 204. The delay line controller 203 starts adjustment from an initial value, and generally the initial value adopts a median value, for example 10000 delay words, to obtain an adjusted delay line 202 ', and the input clock signal generates a new output clock signal through the adjusted delay line 202', and the new output clock signal is fed back to the phase detector 201 for continuous detection. When the adjustment signal trim is not generated, comp is 1, that is, the phase difference between the output clock signal and the input clock signal is zero, and the delay line does not need to be adjusted, so that the current delay line is locked.

It should be noted that, here, taking the phase difference as zero (the preset value is zero) as an example, it is described that the delay line meets the locking condition, and the phase difference between the input signal and the output signal and the preset value may also be determined, when the phase difference is less than or equal to the preset value, it is determined that the current delay line meets the locking condition, and the current delay line is locked; and when the phase difference is larger than the preset value, adjusting the initial locking value to an adjusted locking value, and continuously performing delay adjustment on the input signal according to the delay line corresponding to the adjusted locking value.

The lock value of the delay line tends to be different for different systems. In the related technology, a fixed median is used as an initial value of a delay line of all system adjusting delay locked loops, and the delay line of the delay locked loops can be locked only after being adjusted for many times, and the occupied locking time is usually long, namely the time for clock signals to be asynchronous when the system operates is long, so that the normal operation of the system is easily influenced.

Fig. 4 is a flowchart illustrating a method for locking a delay line of a delay locked loop according to an embodiment of the present application. As shown in fig. 4, a method 400 for locking a delay line of a delay locked loop according to this embodiment includes: in step S401, a condition parameter and a pre-stored lock value of a system including a delay locked loop are acquired; next, in step S402, an initial lock value corresponding to the condition parameter is determined among the lock values stored in advance; and finally in step S403, in response to determining that the delay line of the delay locked loop satisfies the lock condition according to the initial lock value, locking the current delay line.

Steps S401 to S403 are further described below, respectively.

In step S401, condition parameters of the system and lock values stored in advance are acquired. Wherein the condition parameters include at least one of: operating frequency, process-voltage-temperature, path delay. The working frequency represents the current operating frequency of the system; Process-Voltage-Temperature, commonly referred to as PVT (Process-Voltage-Temperature), represents the conditions of Voltage and Temperature for the different processes in the system; path delay represents the delay between the input signal and the output signal due to the path.

The pre-stored lock value is a lock value of a delay line pre-stored in a non-volatile memory of the system, and the lock value may be a lock value corresponding to a condition parameter of a different system pre-stored at the time of factory shipment of the system, may be a lock value updated every time the system operates, or may be both pre-stored in the non-volatile memory of the system. Wherein the data stored in the non-volatile memory is not lost due to a power failure.

Further, the step of S401 may include: after the system is powered on, the condition parameters of the system and the locking values stored in the nonvolatile memory of the system in advance are acquired. Specifically, after the system is powered on, the selection controller in the system may acquire condition parameters of the system, such as an operating frequency and a path delay of the system, and simultaneously acquire a lock value pre-stored in a non-volatile memory of the system, so as to subsequently select a corresponding lock value as an initial lock value according to the condition parameters to adjust a delay line of the delay locked loop.

In another embodiment, the step S401 may include: before the system is powered on, the condition parameters of the system and the locking values stored in a nonvolatile memory of the system in advance are acquired. Specifically, before the system is shipped from factory, the delay locked loop may be operated multiple times, and the lock value of each operation may be stored in the nonvolatile memory. Meanwhile, in order to save the reading time after the system is powered on, the condition parameters of the system and the locking values stored in the nonvolatile memory of the system in advance can be read by the selection controller in the system before the system is powered on, so that the selection controller can select at the first time after the system is powered on.

In step S402, an initial lock value corresponding to the condition parameter is determined among the lock values stored in advance. The initial lock value is a delay value of a delay line when the system is powered on, and generally takes a delay control word as a unit. Specifically, according to the condition parameters of the system, a lock value matching the condition parameters of the system is selected from the pre-stored lock values, the matched lock value is used as an initial lock value, and the delay adjustment is performed on the input clock signal through a delay line corresponding to the initial lock value, so as to output the output clock signal after the delay adjustment. Further, the step of S402 may include: the last updated lock value of the system is obtained as the initial lock value. Specifically, in the same system, the delay time does not vary much, and therefore, when it is judged that there is a lock value of the system updated last time, the lock value is directly taken as an initial lock value, so that even if a certain preparation time is required, the lock time of the delay locked loop is very short, and it is possible to lock in three cycles, for example.

In another embodiment, the step of S402 may include: and determining an initial locking value corresponding to the condition parameter of the system in the pre-stored locking values according to the preset corresponding table of the condition parameters of different systems and each locking value. Specifically, a preset correspondence table between condition parameters of different systems and each lock value may be stored in the nonvolatile memory, and after the condition parameters of the systems are obtained, the lock value corresponding to the condition parameters may be obtained by directly looking up the table, and the lock value may be used as an initial lock value, and a delay line of the system may also be locked quickly.

In step S403, the current delay line is locked in response to determining that the delay line of the delay locked loop satisfies the lock condition according to the initial lock value. Wherein the current delay line is the delay line corresponding to the current lock value. For example, after the nth time of delay line adjustment, the phase difference between the output clock signal after delay adjustment and the input clock signal is zero, so that the current delay line can be locked without adjusting the delay line, and the input clock signal can be subsequently delay-adjusted by the locked delay line to obtain the output clock signal with the phase difference from the input clock signal being zero.

Further, the step of S403 may include: carrying out delay adjustment on an input signal of the system according to a delay line corresponding to the initial locking value to obtain an output signal; and in response to the phase difference between the input signal and the output signal being zero, determining that the current delay line satisfies a lock condition, and locking the current delay line. And responding to the condition that the phase difference between the input signal and the output signal is not zero, adjusting the initial locking value to an adjusted locking value, and continuously carrying out delay adjustment on the input signal according to a delay line corresponding to the adjusted locking value.

Specifically, referring to the flowchart of the delay line locking method 500 of the delay locked loop provided in the present embodiment shown in fig. 5, when the delay locked loop starts adjusting the delay line 102 (not shown in fig. 5), the phase detector 101 generates an initial signal and feeds the initial signal back to the initial value controller 105; the initial value controller 105 may determine the initial lock value corresponding to the condition parameter of the system directly from the lock values pre-stored in the non-volatile memory 104, or may receive the initial lock value directly from the outside, or as shown in fig. 5, determine the initial lock value corresponding to the condition parameter of the system from the lock values pre-stored in the non-volatile memory 104 through the selection controller 107, and receive the initial lock value fed back by the selection controller 107; then the initial value controller 105 feeds back the initial lock value to the delay line controller 103, the delay line controller 103 sets the delay line 102 (not shown in fig. 5) to correspond to the initial lock value, the input clock signal is delayed and adjusted by the delay line 102 (not shown in fig. 5) to obtain the output clock signal, the output clock signal is fed back to the phase detector 101, the phase detector 101 compares the output clock signal with the input clock signal to generate a comparison signal comp and an adjustment signal trim, when comp is 0, it indicates that the phase difference between the output clock signal and the input clock signal is not zero, the delay line 102 (not shown in fig. 5) needs to be continuously adjusted, at this time, the number of adjustments of the delay line is counted by the counter 106, and at the same time, the phase detector 101 generates the adjustment signal trim which is fed back to the delay line controller 103, the adjustment is started from the initial lock value by the delay line controller 103, obtaining an adjusted delay line 102 ', wherein an input clock signal generates a new output clock signal through the adjusted delay line 102', and the new output clock signal is fed back to the phase detector 101 for continuous detection; when comp is 1, it indicates that the phase difference between the output clock signal and the input clock signal is zero, and the adjustment signal trim is not generated, so the delay line controller 103 can lock the current delay line without readjusting the delay line, and store the lock value in the nonvolatile memory 104. After the system is powered up, the selection controller 107 may retrieve the matched initial lock value directly from the non-volatile memory 104.

In the embodiment, the locking values of a plurality of delay lines are stored in advance through the nonvolatile memory, and the initial value controller selects the locking value suitable for the system to start adjusting the delay lines by combining the condition parameters of the system, so that the initial locking value is as close to the final locking value of the system as possible, the adjusting times of the delay lines are greatly reduced, the locking time of the delay lines is reduced, the time of clock signal asynchronization during the operation of the system is further reduced, and the influence on the operation of the system is reduced as much as possible.

Fig. 6 is a flowchart illustrating a method for locking a delay line of a delay locked loop according to an embodiment of the present application. As shown in fig. 6, a method 600 for locking a delay line of a delay locked loop according to this embodiment includes: in step S601, a condition parameter and a pre-stored lock value of a system including a delay locked loop are acquired; next, in step S602, an initial lock value corresponding to the condition parameter is determined among the lock values stored in advance; then in step S603, in response to determining that the delay line of the delay locked loop satisfies the lock condition according to the initial lock value, locking the current delay line; then, in step S604, a current lock value when the current delay line is locked is obtained; finally, in step S605, the corresponding lock value in the non-volatile memory of the system is updated according to the current lock value.

Steps S601 to S603 are the same as steps S401 to S403 corresponding to fig. 4 and further limitations thereof, and are not described herein again.

The following further describes steps S604 to S605, respectively.

In step S604, a current lock value at the time when the current delay line is locked is acquired. The current delay line is a delay line obtained after the delay line is adjusted this time, that is, a delay line when the phase difference between the input signal and the output signal is zero. The current lock value is the delay value of the delay line locked after the delay line is adjusted this time, that is, the delay value of the delay line when the phase difference between the input signal and the output signal is zero.

In step S605, the corresponding lock value in the non-volatile memory of the system is updated according to the current lock value. Specifically, if it is determined that the current frequency and PVT condition exist in the nonvolatile memory, the lock value corresponding to the frequency and PVT condition in the nonvolatile memory is updated to the current lock value. And if the current frequency and PVT condition do not exist in the nonvolatile memory, storing the current frequency and PVT condition and the current lock value in the nonvolatile memory.

Fig. 7 is a schematic diagram of an overall structure of a delay line locking method of a delay locked loop according to an embodiment of the present application. Fig. 7 is a schematic diagram illustrating a connection relationship and a signal control relationship between the DLL 701, the controller 702 outside the DLL, and the nonvolatile memory 104 according to this embodiment. Wherein the controller 702 receives the initial lock value through the delay line control signal after selecting the matched initial lock value from the nonvolatile memory 104; the controller 702 then transmits the delay line control signal to the DLL 701, and the DLL 701 adjusts the delay line by determining an initial lock value according to the delay line control signal until there is no phase deviation between the output signal and the input clock signal through the delay line, locks the delay line, and transmits the current lock value to the nonvolatile memory 104 through the delay line control signal for storage.

The specific processing flow of the DLL 701 refers to the embodiment corresponding to fig. 1, and is not described herein again.

Fig. 8 is a schematic structural diagram of a delay line locking apparatus 800 implemented by a software environment for a delay locked loop according to an embodiment of the present application. As shown in fig. 8, the apparatus 800 includes: a parameter acquisition module 801 configured to acquire a condition parameter and a pre-stored lock value of a system including a delay locked loop; a lock value determination module 802 configured to determine an initial lock value corresponding to the condition parameter among lock values stored in advance; and a delay line locking module 803 configured to lock the current delay line in response to determining from the initial lock value that the delay line of the delay locked loop satisfies the lock condition.

Further, the parameter obtaining module 801 is further configured to obtain the condition parameters of the system and the lock values pre-stored in the non-volatile memory of the system after the system is powered on.

Further, the parameter obtaining module 801 is further configured to obtain the condition parameters of the system and the lock values pre-stored in the non-volatile memory of the system before the system is powered on.

Further, the condition parameter includes at least one of: operating frequency, process-voltage-temperature, path delay.

Further, the lock value determination module 802 is configured to obtain a last updated lock value of the system as the initial lock value.

Further, the locking value determining module 802 is configured to determine an initial locking value corresponding to the condition parameter of the system among the pre-stored locking values according to the preset correspondence table of the condition parameters of different systems and the respective locking values.

Further, the pre-stored lock values include: locking values corresponding to condition parameters of different systems, which are pre-stored when the system leaves a factory, and/or locking values which are updated when the system runs every time.

Further, the delay line locking module 803 is further configured to: carrying out delay adjustment on an input signal of the system according to a delay line corresponding to the initial locking value to obtain an output signal; and responding to the phase difference between the input signal and the output signal being less than or equal to a preset value, determining that the current delay line meets a locking condition, and locking the current delay line.

Further, the delay line locking module 803 is further configured to adjust the initial locking value to the adjusted locking value in response to the phase difference between the input signal and the output signal being greater than the preset value, and continue to perform the delay adjustment on the input signal according to the delay line corresponding to the adjusted locking value.

Further, the delay line locking apparatus 800 may further include: the locking value acquisition module is used for acquiring a current locking value when the current delay line is locked; and the locking value storage module is used for updating the corresponding locking value in the nonvolatile memory of the system according to the current locking value.

An embodiment of the present application further provides a delay locked loop, including: phase detector, delay line and delay line controller, the delay locked loop still includes: a non-volatile memory and an initial value controller;

the non-volatile memory is used for storing a locking value which is sent by the delay line controller and used for the delay line and sending the stored locking value to the initial value controller;

the initial value controller is used for acquiring condition parameters of a system comprising a delay phase-locked loop and stored locking values, selecting matched initial locking values from the stored locking values according to an initial signal sent by the phase detector, and feeding back the initial locking values to the delay line controller;

the delay line controller is used for responding to the fact that the delay line of the delay phase-locked loop meets the locking condition according to the initial locking value and locking the current delay line.

Further, the initial value controller is further configured to:

after the system is powered on, the condition parameters of the system and the locking values stored in the nonvolatile memory of the system in advance are acquired.

Further, the initial value controller is further configured to:

before the system is powered on, the condition parameters of the system and the locking values stored in a nonvolatile memory of the system in advance are acquired.

Further, the condition parameter includes at least one of: operating frequency, process-voltage-temperature, path delay.

Further, the delay line controller is further configured to:

carrying out delay adjustment on an input signal of the system according to a delay line corresponding to the initial locking value to obtain an output signal; and

and determining that the current delay line meets the locking condition and locking the current delay line in response to the phase difference between the input signal and the output signal being less than or equal to a preset value.

Further, the delay line controller is further configured to:

and responding to the fact that the phase difference between the input signal and the output signal is larger than a preset value, adjusting the initial locking value to an adjusted locking value, and continuing to perform delay adjustment on the input signal according to a delay line corresponding to the adjusted locking value.

Further, the delay line controller is further configured to:

acquiring a current locking value when a current delay line is locked; and

and updating the corresponding lock value in the nonvolatile memory of the system according to the current lock value.

Further, the initial value controller is further configured to:

the last updated lock value of the system is obtained as the initial lock value.

Further, the initial value controller is further configured to:

and determining an initial locking value corresponding to the condition parameter of the system in the pre-stored locking values according to the preset corresponding table of the condition parameters of different systems and each locking value.

Further, the pre-stored lock values include:

locking values corresponding to condition parameters of different systems, which are pre-stored in the system when the system leaves a factory, and/or,

lock values that are updated each time the system runs.

The embodiment of the application also provides a delay locking system, which comprises a controller, a nonvolatile memory and the delay locked loop;

after receiving a delay line control signal sent by a nonvolatile memory, the controller forwards the delay line control signal to a delay phase-locked loop;

the delay locked loop locks the delay line according to the delay line control signal and sends a locking value to the nonvolatile memory for storage through a new delay line control signal.

According to embodiments of the present application, there are also provided an electronic device, a readable storage medium, and a computer program product. The electronic device may include: one or more processors; a memory for storing one or more programs which, when executed by the one or more processors, cause the one or more processors to implement the method for delay line locking of a delay locked loop of any embodiment of the present application. The storage medium may store a computer program that when executed by a processor implements the delay line locking method of the delay locked loop of any of the embodiments of the present application. The computer program product may comprise a computer program which, when executed by a processor, implements the method of delay line locking of a delay locked loop of any of the embodiments of the present application.

Fig. 9 is a block diagram of an electronic device for implementing the electronic device or supporting the operation of the readable storage medium and the computer program product according to the embodiment of the present application. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smart phones, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present application that are described and/or claimed herein.

As shown in fig. 9, the electronic apparatus includes: one or more processors 901, memory 902, and interfaces for connecting the various components, including a high-speed interface and a low-speed interface. The various components are interconnected using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions for execution within the electronic device, including instructions stored in or on the memory to display graphical information of a GUI on an external input/output apparatus (such as a display device coupled to the interface). In other embodiments, multiple processors and/or multiple buses may be used, along with multiple memories and multiple memories, as desired. Also, multiple electronic devices may be connected, with each device providing portions of the necessary operations (e.g., a multi-processor system).

Memory 902 is a non-transitory computer readable storage medium as provided herein. The memory stores instructions executable by the at least one processor to cause the at least one processor to perform the method for locking a delay line of a delay locked loop provided by the present application. A non-transitory computer-readable storage medium of the present application stores computer instructions for causing a computer to execute a delay line locking method of a delay locked loop provided by the present application.

The memory 902, which is a non-transitory computer readable storage medium, may be used to store non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions/modules corresponding to the delay line locking method of the dll in the embodiment of the present application (for example, the parameter obtaining module 801, the lock value determining module 802, and the delay line locking module 803 shown in fig. 8). The processor 901 executes various functional applications of the server and data processing, i.e., a delay line locking method of the delay locked loop in the above method embodiment, by executing non-transitory software programs, instructions, and modules stored in the memory 902.

The memory 902 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function; the storage data area may store data created according to use of the electronic device for image processing, and the like. Further, the memory 902 may include high speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory 902 may optionally include a memory remotely located from the processor 901, and these remote memories may be connected via a network to an electronic device for performing the delay line locking method of the delay locked loop. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The electronic device may further include: an input device 903 and an output device 904. The processor 901, the memory 902, the input device 903 and the output device 904 may be connected by a bus or other means, and fig. 9 illustrates the connection by a bus as an example.

The input device 903 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the electronic device locked by the delay line of the delay locked loop, such as a touch screen, keypad, mouse, track pad, touch pad, pointer stick, one or more mouse buttons, track ball, joystick, or other input device. The output devices 904 may include a display device, auxiliary lighting devices (e.g., LEDs), tactile feedback devices (e.g., vibrating motors), and the like. The display device may include, but is not limited to, a Liquid Crystal Display (LCD), a Light Emitting Diode (LED) display, and a plasma display. In some implementations, the display device can be a touch screen.

Various implementations of the systems and techniques described here can be realized in digital electronic circuitry, integrated circuitry, application specific ASICs (application specific integrated circuits), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

These computer programs (also known as programs, software applications, or code) include machine instructions for a programmable processor, and may be implemented using high-level procedural and/or object-oriented programming languages, and/or assembly/machine languages. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and/or device (e.g., magnetic discs, optical disks, memory, Programmable Logic Devices (PLDs)) used to provide machine instructions and/or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal used to provide machine instructions and/or data to a programmable processor.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.