阅读说明：本技术 锁定检测电路及锁相环电路系统 (Lock detection circuit and phase-locked loop circuit system ) 是由 白涛 王晓峰 李佳明 于 2021-08-23 设计创作，主要内容包括：本发明提供了一种锁定检测电路,用于锁相环电路的锁定检测,包括第一采样单元、第二采样单元、与门和计数单元,所述与门与所述第一采样单元和所述第二采样单元以及计数单元连接,第一采样单元用于接收前置分频信号和反馈分频信号,并通过所述反馈分频信号对所述前置分频信号采样,以输出第一采样信号,第二采样单元用于接收所述前置分频信号的反向信号和所述反馈分频信号,并通过所述前置分频信号的反向信号对所述反馈分频信号采样,以输出第二采样信号的反向信号,采用双沿环路锁定检测,降低锁相环电路的误锁几率。本发明提供了一种锁相环电路系统。(The invention provides a lock detection circuit, which is used for lock detection of a phase-locked loop circuit and comprises a first sampling unit, a second sampling unit, an AND gate and a counting unit, wherein the AND gate is connected with the first sampling unit, the second sampling unit and the counting unit, the first sampling unit is used for receiving a prepositive frequency division signal and a feedback frequency division signal and sampling the prepositive frequency division signal through the feedback frequency division signal to output a first sampling signal, the second sampling unit is used for receiving a reverse signal of the prepositive frequency division signal and the feedback frequency division signal and sampling the feedback frequency division signal through the reverse signal of the prepositive frequency division signal to output a reverse signal of the second sampling signal, and double-edge loop lock detection is adopted to reduce the false lock probability of the phase-locked loop circuit. The invention provides a phase-locked loop circuit system.)

1. A lock detection circuit for lock detection of a phase locked loop circuit, comprising:

the device comprises a first sampling unit, a second sampling unit and a control unit, wherein the first sampling unit is used for receiving a pre-frequency division signal and a feedback frequency division signal and sampling the pre-frequency division signal through the feedback frequency division signal so as to output a first sampling signal;

the second sampling unit is used for receiving the reverse signal of the pre-frequency-division signal and the feedback frequency-division signal and sampling the feedback frequency-division signal through the reverse signal of the pre-frequency-division signal so as to output the reverse signal of a second sampling signal;

the AND gate is connected with the first sampling unit and the second sampling unit so as to receive the inverted signals of the first sampling signal and the second sampling signal and output a control signal;

and the counting unit is connected with the AND gate and is used for receiving the feedback frequency division signal and a preset sampling signal by taking the received control signal as an enabling signal, sampling the preset sampling signal through the feedback frequency division signal and outputting a locking signal when the sampled number of the preset sampling signal reaches a preset value.

2. The lock-in detection circuit of claim 1, wherein the first sampling unit is a D flip-flop, a D input of the first sampling unit is configured to receive the pre-divided signal, and a clock terminal of the first sampling unit is configured to receive the feedback divided signal.

3. The lock-in detection circuit of claim 2, wherein the second sampling unit is a D flip-flop, a D input of the second sampling unit is configured to receive the feedback frequency-divided signal, and a clock terminal of the second sampling unit is configured to receive an inverted signal of the pre-frequency-divided signal.

4. The lock-in detection circuit according to claim 1 or 3, further comprising an inverter unit, an output of the inverter unit being connected to the second sampling unit, an input of the inverter unit being configured to receive the prescaled signal.

5. The lock-in detection circuit of claim 3, wherein a first input of the AND gate is connected to the Q output of the first sampling unit, and a second input of the AND gate is connected to the QN output of the second sampling unit.

6. A phase-locked loop circuitry, comprising:

a phase-locked loop circuit;

a lock detection circuit as claimed in any one of claims 1 to 5, connected to the phase locked loop circuit for lock detection of the phase locked loop circuit.

7. The pll circuitry of claim 6, wherein the pll circuitry comprises an oscillator unit, a prescaler unit, a phase frequency detector unit, a charge pump unit, a voltage controlled oscillator unit, and a feedback frequency divider unit, wherein the oscillator unit is connected to the prescaler unit, the prescaler unit is connected to the phase frequency detector unit and the lock detection circuit, and is configured to output a prescaled frequency signal, the phase frequency detector unit is connected to the charge pump unit, the charge pump unit is connected to the voltage controlled oscillator unit, the voltage controlled oscillator unit is connected to the feedback frequency divider unit, and the feedback frequency divider unit is connected to the phase frequency detector unit and the lock detection circuit, and is configured to output a feedback frequency signal.

8. The phase-locked loop circuitry of claim 7, wherein the prescaler unit and the feedback divider unit are both falling edge count dividers or falling edge count dividers.

9. The phase-locked loop circuitry of claim 8, wherein the feedback divider unit outputs a feedback divided signal having a duty cycle of less than 50%.

Technical Field

The invention relates to the technical field of phase-locked loops, in particular to a lock detection circuit and a phase-locked loop circuit system.

Background

The phase-locked loop circuit has wide application in today's integrated circuits, wireless communication, wired transmission, sample-and-hold circuits, and the like.

At present, the methodThe locking of the dual-loop phase-locked loop circuit is detected by a loop Lock detector (Lock detector), the loop Lock detector is shown in fig. 1 and comprises a D flip-flop (DFF) and a Counter (Counter), a D input end of the D flip-flop is used for receiving a preliminary frequency division signal ref, a clock end CK of the D flip-flop is used for receiving a feedback frequency division signal fbk, a Q output end of the D flip-flop is connected with an enabling signal receiving end of the Counter, a D input end of the Counter is connected with a high level signal, the clock end CK of the Counter is used for receiving a feedback frequency division signal fbk, the loop Lock detector samples the preliminary frequency division signal by the feedback frequency division signal, and if 2 consecutive frequency division signals are detected, the loop Lock detector is used for sampling the preliminary frequency division signal, and if the Counter is used for receiving 2 consecutive frequency division signals, the Counter is used for counting the Counter^NAnd if the high level is sampled at the time, the loop locking detection circuit judges that the double-loop phase-locked loop circuit is locked.

However, the time span of the detection signal of the existing double-loop lock detection circuit depends heavily on the number of bits of the counter, the longer the duration of the signal to be detected is, the larger the number of bits of the counter is, the longer the duration of the signal to be detected is, after the double-loop phase-locked loop is locked, the time required to wait for detecting the locking of the double-loop phase-locked loop is correspondingly increased, if the duration of the detection signal is shorter, the situation shown in fig. 2 may occur, the correct locking time of the double-loop phase-locked loop circuit is 32 μ s, but the integral path voltage and the proportional path voltage in the double-loop phase-locked loop circuit are not established stably, that is, the double-loop phase-locked loop circuit is not locked, and the double-loop lock detection circuit outputs a high level representing the locking of the double-loop phase-locked loop circuit.

Therefore, there is a need to provide a novel lock detection circuit and a pll circuit system to solve the above problems in the prior art.

Disclosure of Invention

The invention aims to provide a lock detection circuit and a phase-locked loop circuit system, which can reduce the false lock probability of a phase-locked loop circuit.

To achieve the above object, the lock detection circuit of the present invention is used for lock detection of a phase-locked loop circuit, and includes:

the device comprises a first sampling unit, a second sampling unit and a control unit, wherein the first sampling unit is used for receiving a pre-frequency division signal and a feedback frequency division signal and sampling the pre-frequency division signal through the feedback frequency division signal so as to output a first sampling signal;

the second sampling unit is used for receiving the reverse signal of the pre-frequency-division signal and the feedback frequency-division signal and sampling the feedback frequency-division signal through the reverse signal of the pre-frequency-division signal so as to output the reverse signal of a second sampling signal;

the AND gate is connected with the first sampling unit and the second sampling unit so as to receive the inverted signals of the first sampling signal and the second sampling signal and output a control signal;

and the counting unit is connected with the AND gate and is used for receiving the feedback frequency division signal and a preset sampling signal by taking the received control signal as an enabling signal, sampling the preset sampling signal through the feedback frequency division signal and outputting a locking signal when the sampled number of the preset sampling signal reaches a preset value.

The lock detection circuit has the advantages that: the first sampling unit is used for receiving a front frequency division signal and a feedback frequency division signal, and sampling the front frequency division signal through the feedback frequency division signal to output a first sampling signal, the second sampling unit is used for receiving a reverse signal of the front frequency division signal and the feedback frequency division signal, and sampling the feedback frequency division signal through the reverse signal of the front frequency division signal to output a reverse signal of a second sampling signal, double-edge loop locking detection is adopted, and the false locking probability of the phase-locked loop circuit is reduced.

Preferably, the first sampling unit is a D flip-flop, a D input end of the first sampling unit is configured to receive the pre-divided signal, and a clock end of the first sampling unit is configured to receive the feedback divided signal. The beneficial effects are that: the pre-divided signal is conveniently sampled by a rising edge of the feedback divided signal.

Further preferably, the second sampling unit is a D flip-flop, a D input end of the second sampling unit is configured to receive the feedback frequency-divided signal, and a clock end of the second sampling unit is configured to receive an inverted signal of the pre-frequency-divided signal. The beneficial effects are that: the feedback frequency-divided signal is conveniently sampled by the falling edge of the pre-frequency-divided signal.

Further preferably, the lock detection circuit further includes an inverter unit, an output end of the inverter unit is connected to the second sampling unit, and an input end of the inverter unit is configured to receive the prescaled frequency division signal. The beneficial effects are that: so as to obtain the inverse signal of the pre-divided signal.

Further preferably, a first input end of the and gate is connected to a Q output end of the first sampling unit, and a second input end of the and gate is connected to a QN output end of the second sampling unit.

The present invention also provides a phase-locked loop circuit system, including:

a phase-locked loop circuit;

and the locking detection circuit is connected with the phase-locked loop circuit and used for locking detection of the phase-locked loop circuit.

The phase-locked loop circuit system has the advantages that: the locking detection circuit is connected with the phase-locked loop circuit to detect whether the phase-locked loop circuit is locked or not, and the probability of false locking of the phase-locked loop circuit is reduced by adopting double-edge loop locking detection.

Preferably, the phase-locked loop circuit includes oscillator unit, leading frequency divider unit, phase frequency detector unit, charge pump unit, voltage controlled oscillator unit and feedback frequency divider unit, the oscillator unit with leading frequency divider unit connects, leading frequency divider unit with phase frequency detector unit with locking detection circuitry connects for export leading frequency division signal, phase frequency detector unit with charge pump unit connects, charge pump unit with voltage controlled oscillator unit connects, voltage controlled oscillator unit with feedback frequency divider unit connects, feedback frequency divider unit with phase frequency detector unit with locking detection circuitry connects for export feedback frequency division signal.

Further preferably, the pre-divider unit and the feedback divider unit are both falling edge count dividers or falling edge count dividers.

Further preferably, the duty ratio of the feedback frequency-divided signal output by the feedback frequency divider unit is less than 50%.

Drawings

FIG. 1 is a schematic diagram of a prior art loop lock detection circuit;

FIG. 2 is a graph illustrating the integral path voltage, proportional path voltage and counter output signal of the prior art;

FIG. 3 is a schematic diagram of PLL circuitry according to the present invention;

FIG. 4 is a schematic diagram of a phase-locked loop circuit according to the present invention;

FIG. 5 is a schematic diagram of waveforms of an input signal and a feedback frequency-divided signal of the feedback frequency divider unit according to the present invention;

FIG. 6 is a schematic waveform diagram of a prescaled signal and a feedback frequency-divided signal according to the present invention;

FIG. 7 is a schematic diagram of a lock-in detection circuit according to the present invention;

FIG. 8 is a graph illustrating the integration path voltage, the proportional path voltage and the output signal of the counting unit according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.

In view of the problems in the prior art, an embodiment of the present invention provides a phase-locked loop circuit system, and referring to fig. 3, the phase-locked loop circuit system 100 includes a phase-locked loop circuit 101 and a lock detection circuit 102, where the lock detection circuit 102 is connected to the phase-locked loop circuit 101 and is used for lock detection of the phase-locked loop circuit 101.

FIG. 4 is a diagram of a phase-locked loop circuit according to the present invention. Referring to fig. 4, the phase-locked loop circuit 101 includes an oscillator unit 1011, a prescaler unit 1012, a phase frequency detector unit 1013, a charge pump unit 1014, a voltage controlled oscillator unit 1015, and a feedback frequency divider unit 1016, where the oscillator unit 1011 is connected to the prescaler unit 1012, the prescaler unit 1012 is connected to the phase frequency detector unit 1013 and the lock detection circuit (not shown) to output a prescaler signal ref, the phase frequency detector unit 1013 is connected to the charge pump unit 1014, the charge pump unit 1014 is connected to the voltage controlled oscillator unit 1015, the voltage controlled oscillator unit 1015 is connected to the feedback frequency divider unit 1016, and the feedback frequency divider unit 1016 is connected to the phase frequency detector unit 1013 and the lock detection circuit to output a feedback frequency-divided signal fbk.

Referring to fig. 4, the charge pump unit 1014 includes an integral path circuit 10141 and a proportional path circuit 10142, and the integral path circuit 10141 and the proportional path circuit 10142 are well known in the art and are not described in detail herein.

In some embodiments, when the pll circuit is applied to a port of an MIPI D-PHY protocol, the reference frequency input by the pll circuit is 266MHz, and the output frequency of the pll circuit is 600MHz to 1.5GHz, which shows that the output frequency of the pll circuit is higher than the reference frequency input by the pll circuit.

In some embodiments, the output frequencies of the prescaler unit and the feedback frequency divider unit are equal, for example, the reference frequency input by the phase-locked loop circuit is 266MHz, the output frequency is 1.07GHz, the output frequency divided by the prescaler unit is 133MHz, and the output frequency divided by the feedback frequency divider unit is also 133 MHz.

In some embodiments, the prescaler unit and the feedback frequency divider unit are both falling edge counting frequency dividers or falling edge counting frequency dividers, and the duty ratio of the feedback frequency division signal output by the feedback frequency divider unit is less than 50%

In some embodiments, taking the falling edge counting frequency divider as an example, it can be known from the working principle of the falling edge counting frequency divider that the width of one high level of the output signal of the falling edge counting frequency divider is related to the frequency of the input signal, and the higher the frequency of the input signal is, the narrower the width of one high level of the output signal is.

Fig. 5 is a schematic waveform diagram of the input signal and the feedback frequency-divided signal of the feedback frequency divider unit according to the present invention. Referring to fig. 5, the input signal and the feedback frequency-divided signal are included in the graph, the feedback frequency-divided signal is formed by dividing the input signal by 10, the width of one high-level signal of the feedback frequency-divided signal is equal to the width of one cycle of the input signal, and the width of one low-level signal of the feedback frequency-divided signal is equal to the width of 9 cycles of the input signal.

In some embodiments, the output frequency of the pll circuit is higher than the reference frequency of the pll circuit input, and therefore, the width of a high level of the prescaled signal is greater than the width of a high level of the feedback signal.

Fig. 6 is a schematic waveform diagram of a prescaled signal and a feedback frequency-divided signal according to the present invention. Referring to fig. 6, the frequency of the prescaled signal and the frequency of the feedback divided signal are the same, and the width of one high level of the feedback divided signal is smaller than that of the prescaled signal. If the phase-locked loop circuit is locked, the rising edge of the feedback frequency division signal corresponds to the high level of the pre-frequency division signal, and the falling edge of the pre-frequency division signal corresponds to the low level of the feedback frequency division signal.

In some embodiments, the lock detection circuit includes a first sampling unit, a second sampling unit, an and gate, and a counting unit. The first sampling unit is used for receiving a pre-frequency division signal and a feedback frequency division signal, and sampling the pre-frequency division signal through the feedback frequency division signal to output a first sampling signal; the second sampling unit is used for receiving the reverse signal of the pre-frequency-division signal and the feedback frequency-division signal, and sampling the feedback frequency-division signal through the reverse signal of the pre-frequency-division signal so as to output the reverse signal of a second sampling signal; the AND gate is connected with the first sampling unit and the second sampling unit to receive the inverted signals of the first sampling signal and the second sampling signal and output control signals; the counting unit is connected with the AND gate and is used for receiving the feedback frequency division signal and a preset sampling signal by taking the received control signal as an enabling signal, sampling the preset sampling signal through the feedback frequency division signal, and outputting a locking signal when the number of the preset sampling signal reaches a preset value.

In some embodiments, the predetermined sampling signal is a high level signal or a low level signal, and the counting unit is a known technology in the art and will not be described in detail herein, for example, a counter in the loop lock detection circuit.

In some embodiments, the lock detection circuit further comprises an inverter unit, an output of the inverter unit is connected to the second sampling unit, and an input of the inverter unit is configured to receive the prescaled signal.

FIG. 7 is a schematic diagram of a lock detection circuit according to the present invention. Fig. 7, the lock detection circuit 102 includes a first sampling unit 1021, an inverter unit 1022, a second sampling unit 1023, an and gate 1024, and a counting unit 1025, where the first sampling unit 1021 and the second sampling unit 1023 are both D flip-flops, a D input of the first sampling unit 1021 is configured to receive the pre-divided signal ref, a clock terminal ck of the first sampling unit 1021 is configured to receive the feedback divided signal fbk, an input of the inverter unit 1022 is configured to receive the pre-divided signal ref, an output of the inverter unit 1022 is connected to a clock terminal ck of the second sampling unit 1023 to send an inverted signal of the pre-divided signal ref to the clock terminal ck of the second sampling unit 1023, a D input of the second sampling unit fbk is configured to receive the feedback divided signal fbk, and a first input of the and gate 1024 is connected to a Q output of the first sampling unit 1021, the second input end of the and gate 1024 is connected to the QN output end of the second sampling unit 1023, the output end of the and gate 1024 is connected to the enable end of the counting unit 1025, so that the control signal output by the and gate 1024 is used as an enable signal, the D input end of the counting unit 1025 is connected to a high level signal, the clock end ck of the counting unit 1025 is used for receiving the feedback frequency division signal fbk, the high level signal is sampled by the feedback frequency division signal fbk, and a locking signal lock _ signal is output when the sampled number of the high level signal reaches a preset value.

Referring to fig. 4 and 7, the D input terminal of the first sampling unit 1021 is connected to the output terminal of the prescaler unit 1012 to receive the prescaled signal ref output by the prescaler unit 1012, the clock terminal ck of the second sampling unit 1023 is connected to the output terminal of the feedback frequency divider unit 1016 to receive the feedback frequency-divided signal fbk output by the feedback frequency divider unit 1016, the D input terminal of the second sampling unit 1023 is connected to the output terminal of the feedback frequency divider unit 1016 to receive the feedback frequency-divided signal fbk output by the feedback frequency divider unit 1016, and the input terminal of the inverter unit 1022 is connected to the output terminal of the prescaler unit ref to receive the prescaled signal ref output by the prescaler unit 1012.

Referring to fig. 7, the first sampling unit 1021 samples the pre-divided signal ref through a rising edge of the feedback divided signal fbk, and if the pre-divided signal ref is sampled to a high level, a Q output terminal of the first sampling unit 1021 outputs a high level, and if the pre-divided signal ref is sampled to a low level, a Q output terminal of the first sampling unit 1021 outputs a low level.

Referring to fig. 7, the second sampling unit 1023 samples the feedback frequency-divided signal fbk by a rising edge of an inverted signal of the pre-frequency-divided signal ref, that is, the second sampling unit 1023 samples the feedback frequency-divided signal fbk by a falling edge of the pre-frequency-divided signal ref, if a high level is sampled, the QN output terminal of the second sampling unit 1023 outputs a low level, and if a low level is sampled, the QN output terminal of the second sampling unit 1023 outputs a high level.

Referring to fig. 7, if the Q output terminal of the first sampling unit 1021 outputs a high level and the QN terminal of the second sampling unit 1023 outputs a high level, the control signal output by the and gate 1024 is a high level, the high level is used as the enable signal of the counting unit 1025, and the counting unit 1025 operates to sample the high level through the rising edge of the feedback frequency-divided signal fbk, and 1 is added to the sampled number of the high-level signal every time the high level is sampled.

Referring to fig. 7, if the Q output of the first sampling unit 1021 outputs a low level, which represents that the pre-divided signal ref is sampled to a low level by the rising edge of the feedback divided signal fbk, and further represents that the pll circuit 101 is not locked, the control signal output by the and gate 1024 must be a low level, which is an enable signal of the counting unit 1025, the counting unit 1025 is reset, and the counting unit 1025 counts again.

Referring to fig. 7, if the QN output terminal of the second sampling unit 1023 outputs a low level, which represents that the high level of the feedback frequency-divided signal fbk is sampled by the rising edge of the inverted signal of the pre-frequency-divided signal ref, and also corresponds to that the high level of the feedback frequency-divided signal fbk is sampled by the falling edge of the pre-frequency-divided signal ref, which represents that the pll 101 is not locked, the control signal output by the and gate 1024 is necessarily a low level, which is an enable signal of the counting unit 1025, the counting unit 1025 is reset, and the counting unit 1025 counts again.

FIG. 8 is a graph illustrating the integration path voltage, the proportional path voltage and the output signal of the counting unit according to the present invention. Referring to fig. 8, it can be seen that after the integration path voltage and the proportional path voltage have settled, i.e. at 32 μ s, the counting unit issues a high level lock signal, representing that the phase locked loop circuit is locked, and does not issue a high level lock signal for false lock before the integration path voltage and the proportional path voltage have settled.

Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.