阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 王炜 杨伟臣 张耀中 苏如意 林彦谷 邹权炜 蔡俊琳 于 2021-08-02 设计创作，主要内容包括：本发明提供了半导体结构。该半导体结构包括：位于衬底上的氮化镓(GaN)层；设置在GaN层上的氮化铝镓(AlGaN)层；设置在AlGaN层上的栅极堆叠件；设置在AlGaN层上并且由栅极堆叠件插入的源极部件和漏极部件；介电材料层设置在栅极堆叠件上；以及设置在介电材料层上并且电连接至源极部件的场板,其中,该场板包括阶梯式结构。本申请的实施例还涉及形成半导体结构的方法。(The invention provides a semiconductor structure. The semiconductor structure includes: a gallium nitride (GaN) layer on the substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer disposed on the gate stack; and a field plate disposed on the layer of dielectric material and electrically connected to the source feature, wherein the field plate includes a stepped structure. Embodiments of the present application also relate to methods of forming semiconductor structures.)

1. A semiconductor structure, comprising:

a gallium nitride (GaN) layer on the substrate;

an aluminum gallium nitride (AlGaN) layer disposed on the gallium nitride layer;

a gate stack disposed on the aluminum gallium nitride layer;

a source feature and a drain feature disposed on the aluminum gallium nitride layer and interposed by the gate stack;

a dielectric material layer disposed on the gate stack; and

a field plate disposed on the dielectric material layer and electrically connected to the source electrode feature, wherein the field plate includes a stepped structure.

2. The semiconductor structure of claim 1, wherein the field plate includes a first segment extending horizontally, a second segment extending vertically from the first segment, and a third segment extending horizontally from the second segment.

3. The semiconductor structure of claim 2, wherein,

the first segment is horizontally spaced from the gate stack by a first dimension D1;

the drain feature is horizontally spaced from the gate stack by a second dimension D2; and is

The first ratio D1/D2 is less than 95%.

4. The semiconductor structure of claim 3, wherein,

the field plate spans width W horizontally; and is

The second ratio W/D2 is greater than 5% and less than 100%.

5. The semiconductor structure of claim 4, wherein,

the source member is electrically connected to the field plate through a conductive member;

the conductive feature extends horizontally from the source feature;

the conductive feature is vertically spaced from the gate stack by a third dimension D3;

the field plate vertically spans a height H; and is

The third ratio H/D3 is less than 50%.

6. The semiconductor structure of claim 2, wherein the field plate further comprises a fourth segment extending vertically from the third segment and a fifth segment extending horizontally from the fourth segment.

7. The semiconductor structure of claim 1, wherein the gate stack comprises a III-V compound p-type doped layer.

8. The semiconductor structure of claim 1, wherein the gate stack further comprises a dielectric layer underlying the III-V compound p-type doped layer.

9. A semiconductor structure, comprising:

a first III-V compound layer on the substrate;

a second III-V compound layer directly on the first III-V compound layer, the second III-V compound layer being different in composition from the first III-V compound layer and further comprising aluminum;

a gate stack on the second III-V compound layer;

a source feature and a drain feature disposed on the second III-V compound layer; and

a field plate disposed over the gate stack and electrically connected to the source feature, wherein the field plate includes at least three segments having a stepped structure.

10. A method of forming a semiconductor structure, comprising:

forming a first III-V compound layer on a substrate;

forming a second III-V compound layer on the first III-V compound layer, wherein the second III-V compound layer is different in composition from the first III-V compound layer and further includes aluminum;

forming a gate stack on the second III-V compound layer;

forming a source feature and a drain feature on the second III-V compound layer, and the source feature and the drain feature are interposed by the gate stack; and

forming a field plate over the gate stack and electrically connecting the field plate to the source feature, wherein the field plate comprises at least three segments configured in a stepped configuration.

Technical Field

Embodiments of the present application relate to semiconductor structures and methods of forming the same.

Background

In semiconductor technology, gallium nitride (GaN) is used to form various integrated circuit devices such as high power field effect transistors, high frequency transistors, or High Electron Mobility Transistors (HEMTs) due to its characteristics. In some examples, GaN-based devices are used in integrated circuits to achieve high breakdown voltages and low on-resistance. However, breakdown voltage is a related variety of factors. Existing GaN-based devices are far from satisfactory in view of breakdown voltage and other device parameters including threshold voltage. Accordingly, there is a need for a structure of a GaN-based device with enhanced breakdown voltage and a method of fabricating the same for solving the above-mentioned problems.

Disclosure of Invention

Some embodiments of the present application provide a semiconductor structure comprising: a gallium nitride (GaN) layer on the substrate; an aluminum gallium nitride (AlGaN) layer disposed on the gallium nitride layer; a gate stack disposed on the aluminum gallium nitride layer; a source feature and a drain feature disposed on the aluminum gallium nitride layer and interposed by the gate stack; a dielectric material layer disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source electrode part, wherein the field plate includes a stepped structure.

Other embodiments of the present application provide a semiconductor structure comprising: a first III-V compound layer on the substrate; a second III-V compound layer directly on the first III-V compound layer, the second III-V compound layer being different in composition from the first III-V compound layer and further comprising aluminum; a gate stack on the second III-V compound layer; a source feature and a drain feature disposed on the second III-V compound layer; and a field plate disposed over the gate stack and electrically connected to the source feature, wherein the field plate includes at least three segments having a stepped structure.

Still other embodiments of the present application provide a method of forming a semiconductor structure, comprising: forming a first III-V compound layer on a substrate; forming a second III-V compound layer on the first III-V compound layer, wherein the second III-V compound layer is different in composition from the first III-V compound layer and further includes aluminum; forming a gate stack on the second III-V compound layer; forming a source feature and a drain feature on the second III-V compound layer, and the source feature and the drain feature are interposed by the gate stack; and forming a field plate over the gate stack and electrically connecting the field plate to the source feature, wherein the field plate includes at least three segments configured in a stepped configuration.

Drawings

Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1a is a cross-sectional view of a semiconductor structure having a gallium nitride (GaN) based transistor constructed in accordance with some embodiments;

FIG. 1b is a cross-sectional view of a semiconductor structure having a gallium nitride (GaN) -based device constructed in accordance with some embodiments;

FIGS. 2 a-8 a are cross-sectional views of a gate structure incorporated in the semiconductor structure of FIG. 1a, in accordance with various embodiments;

fig. 2 b-8 b are schematic diagrams of the semiconductor structure of fig. 1a with the gate stacks of fig. 2 a-8 a, respectively, according to various embodiments;

FIG. 9 is a cross-sectional view of a semiconductor structure having a GaN-based transistor constructed in accordance with some embodiments;

FIG. 10 is a cross-sectional view of a semiconductor structure having a gallium nitride (GaN) -based transistor constructed in accordance with some embodiments;

FIG. 11 is a flow chart of fabricating a semiconductor structure with a GaN-based device (such as those of FIG. 1a, FIG. 1b, FIG. 9, and FIG. 10) constructed in accordance with some embodiments;

fig. 12-19 are cross-sectional views of semiconductor structures, such as those of fig. 1a, 9, and 10, at various stages of manufacture, in accordance with various embodiments;

fig. 20-24 are cross-sectional views of semiconductor structures, such as those of fig. 1a, 9, and 10, at various stages of fabrication, in accordance with various embodiments;

figures 25-27 are cross-sectional views of a semiconductor structure at various stages of fabrication, in accordance with various embodiments; and is

Fig. 28 is a graphical view of various characteristic data for a gallium nitride (GaN) -based device according to some embodiments.

Detailed Description

It is contemplated that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. The present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Fig. 1a is a cross-sectional view of one embodiment of a semiconductor structure (or device structure) 100 having a gallium nitride (GaN) based transistor. FIG. 1b is a cross-sectional view of one embodiment of a semiconductor structure 180 having a GaN-based device. Fig. 2 a-8 a are cross-sectional views of a gate structure incorporated in the semiconductor structure of fig. 1a, in accordance with various embodiments of the present invention. Fig. 2 b-8 b are schematic diagrams of the semiconductor structure of fig. 1a with the gate structures of fig. 2 a-8 a, respectively, in accordance with various embodiments of the present invention. A GAN-based device, such as semiconductor structure 100 (or 180), and a method of fabricating the same are collectively described with reference to fig. 1a, 1b, 2 a-8 a, 2 b-8 b, and other figures.

Referring to fig. 1a, a semiconductor structure 100 includes a sapphire substrate 110. Alternatively, the substrate may be a silicon carbide (SiC) substrate or a silicon substrate. For example, the silicon substrate may be a (111) silicon wafer.

The semiconductor structure 100 also includes a heterojunction formed between two different layers of semiconductor material, such as layers of material having different band gaps. For example, the semiconductor structure 100 includes an undoped narrow-gap channel layer and a wide-gap n-type donor-supplying layer. In one embodiment, the semiconductor structure 100 includes a first III-V compound layer (or buffer layer) 114 formed on a substrate 110 and a second III-V compound layer (or barrier layer) 116 formed on the buffer layer 114. The buffer layer 114 and the barrier layer 116 are compounds made of groups III-V of the periodic table. However, the buffer layer 114 and the barrier layer 116 are different from each other in composition. The buffer layer 114 is undoped or unintentionally doped (UID). In the present embodiment of the semiconductor structure 100, the buffer layer 114 includes a gallium nitride (GaN) layer (also referred to as GaN layer 114). The barrier layer 116 includes an aluminum gallium nitride (AlGaN) layer (also referred to as AlGaN layer 116). In some embodiments, GaN layer 114 and AlGaN layer 116 may be in direct contact with each other.

In the depicted embodiment, the GaN layer 114 is undoped. Optionally, the GaN layer 114 is unintentionally doped, such as lightly doped with n-type, due to the precursors used to form the GaN layer 114. The GaN layer 114 may be epitaxially grown by Metal Organic Vapor Phase Epitaxy (MOVPE) using a gallium-containing precursor and a nitrogen-containing precursor. Gallium-containing precursors include Trimethylgallium (TMG), Trimethylaluminum (TEG), or other suitable chemicals. The nitrogen-containing precursor comprises ammonia (NH)₃) Tert-butylamine (TBAm), phenylhydrazine, or other suitable chemical species. In one example, the thickness of the GaN layer 114 ranges between about 0.5 microns and about 10 microns. In another example, the thickness of the GaN layer 114 is about 2 microns.

AlGaN layer 116 is n-type doped, such as lightly n-type doped. Alternatively or additionally, AlGaN layer 116 has n-type dopants introduced from adjacent layers. In some embodiments, AlGaN layer 116 is p-type doped, such as lightly p-type doped. AlGaN layer 116 is deposited on GaN layer 114 by selective epitaxial growth. AlGaN layer 116 may be epitaxially grown by MOVPE using an aluminum-containing precursor, a gallium-containing precursor, and a nitrogen-containing precursor. The aluminum-containing precursor comprises TMA, TEA or other suitable chemical. Gallium-containing precursors include TMG, TEG, or other suitable chemicals. Nitrogen-containing precursors include ammonia, TBAm, phenylhydrazine, or other suitable chemicals. In one example, AlGaN layer 116 has a thickness in a range between about 5 nanometers and about 50 nanometers. In another example, AlGaN layer 116 is about 15 nanometers thick.

Electrons in AlGaN layer 116 fall into GaN layer 114, creating a very thin layer 118 of high mobility conduction electrons in GaN layer 114. This thin layer 118 is referred to as a two-dimensional electron gas (2-DEG) that forms a carrier channel. A thin layer 118 of 2-DEG is positioned at the interface of AlGaN layer 116 and GaN layer 114. Thus, the carrier channel has high electron mobility because the GaN layer 114 is undoped or unintentionally doped, and electrons can move freely without colliding with impurities or with substantially reduced collisions.

The semiconductor structure 100 also includes a source feature 120A and a drain feature 120B formed on the substrate 110 and configured to be electrically connected to the channel layer 118. The source feature 120A and the drain feature 120B are also collectively referred to as source/drain (S/D) features 120. The S/D components 120 include one or more conductive materials. For example, the S/D part 120 includes one metal selected from the group consisting of titanium, aluminum, nickel, and gold. S/D components 120 may be formed by a process such as Physical Vapor Deposition (PVD) or other suitable techniques. A thermal annealing process may be applied to the S/D member 120 such that the S/D member 120 and the AlGaN layer 116 react to form an alloy for effective electrical connection from the S/D member 120 and the channel to the ohmic contact. As one example, a Rapid Thermal Annealing (RTA) apparatus and process is used for thermal annealing.

A gate stack 122 is formed on the barrier layer 116 and interposed between the source and drain features 120. In some embodiments, gate stack 122 includesA junction isolation feature disposed on the barrier layer (AlGaN layer in this embodiment) 116. The junction isolation feature comprises at least one doped semiconductor layer such that a p-n junction is formed with the barrier layer 116. In the depicted embodiment, the junction isolation feature comprises at least one p-type doped III-V compound, while the barrier layer 116 is n-type doped. In yet another embodiment, the p-type doped III-V compound layer is a p-type doped GaN (p-GaN) layer, wherein the GaN is doped with a p-type dopant such as magnesium, calcium, zinc beryllium, carbon, or a combination thereof. According to some embodiments, the dopant concentration ranges from 10¹⁹cm^-3And 10²¹cm^-3In the meantime. In the depicted embodiment, the junction isolation feature of p-GaN and the barrier layer 116 of n-AlGaN are configured to form a p-n junction to provide isolation and capacitive coupling to the channel layer 118. In some embodiments, the gate stack 122 includes a layer of conductive material, such as a metal, metal alloy, other suitable conductive material, or a combination thereof, disposed on the junction isolation feature and serving as a gate electrode. The layer of conductive material is configured for voltage biasing and electrical coupling with the channel layer.

In some examples, the gate stack 122 includes at least one n-type doped semiconductor layer and one p-type doped semiconductor layer to form a diode, which may be an n-type doped III-V compound layer and a p-type doped III-V compound layer, respectively. In yet another example, the n-type doped III-V compound layer and the p-type doped III-V compound layer are an n-type doped GaN layer (or n-GaN layer) and a p-type doped GaN layer (p-GaN layer), respectively. The diodes in the gate stack provide a junction isolation effect. In the present embodiment, the gate stack 122, the S/D features 120, and the 2-DEG channel in the buffer layer 114 are configured as GaN-based transistors. Specifically, the transistor thus configured is also referred to as a High Electron Mobility Transistor (HEMT).

Fig. 2 a-8 a illustrate various embodiments of a gate stack 122 of a semiconductor structure 100 constructed in accordance with various aspects of the invention. A gate stack 122 is also described according to various embodiments. In one embodiment shown in fig. 2a, the gate stack 122 includes a metal layer 124 and junction isolation features 126 disposed below the metal layer 124. The metal layer 124 may include any suitable metal or metal alloy, such as copper, aluminum, tungsten, nickel, cobalt, other suitable metals, or combinations thereof. The junction isolation feature 126 includes at least one doped semiconductor layer such that a p-n junction is formed with the AlGaN layer 116. In the depicted embodiment, the junction isolation features 126 comprise at least one p-doped semiconductor layer, while the AlGaN layer 116 is n-doped. In yet another embodiment, the p-type doped III-V compound layer is a p-type doped GaN layer (p-GaN layer).

Fig. 2b shows a schematic diagram of a GaN-based transistor of the semiconductor structure 100 with the gate stack 122 of fig. 2 a. In fig. 2b, "G", "S" and "D" denote a gate, a source and a drain, respectively. A 2-DEG channel is defined between the source and drain. Diode 138a is formed between p-GaN layer 130 and barrier layer 116 having n-type dopants. The resulting capacitance from diode 138a decreases and the device switching speed increases.

Optionally, the junction isolation features 126 may also include another n-doped GaN layer, another p-doped GaN layer, or both. A junction (or diode) is formed between each pair of adjacent n-GaN layers and p-GaN layers. Various diodes between the n-GaN and p-GaN layers are electrically configured in series. These diodes not only provide isolation from the channel to the gate electrode with reduced gate leakage, but also improve device switching speed, as explained below. Since the various diodes are coupled in series, the corresponding capacitors are also coupled in series. Thus, the total capacitance of the series capacitor will be less than that of either. Thus, the device switching speed is increased due to the reduced capacitance.

In one embodiment, the interface between the metal layer and the diode is an ohmic contact formed by thermal annealing, wherein the annealing temperature ranges between about 800 ℃ and about 900 ℃. In another embodiment, the interface between the metal layer and the diode is a schottky contact. In this case, the process for forming the gate stack is not thermally annealed.

In one embodiment shown in FIG. 3a, junction isolation feature 126 of gate stack 122 includes a p-GaN layer 130 and an n-GaN layer 132 disposed on p-GaN layer 130. The p-GaN layer 130 is doped with a p-type dopant such as magnesium, calcium, zinc beryllium, carbon, or a combination thereof. In one embodiment, the p-GaN layer 130 may be formed by Metal Organic Chemical Vapor Deposition (MOCVD) or other suitable techniques. In another embodiment, the thickness of the p-GaN layer 130 ranges between about 1nm and about 100 nm. The n-GaN layer 132 is doped with an n-type dopant such as silicon, oxygen, or a combination thereof. In one embodiment, the n-GaN layer 132 may be formed by MOCVD or other suitable techniques. In another embodiment, the thickness of the n-GaN layer 132 ranges between about 1nm and about 100 nm.

Fig. 3b shows a schematic diagram of a GaN-based transistor of the semiconductor structure 100 with the gate stack 122 of fig. 3 a. In fig. 3b, "G", "S" and "D" denote a gate, a source and a drain, respectively. A 2-DEG channel is defined between the source and drain. Diode 138a is formed between p-GaN layer 130 and barrier layer 116 having n-type dopants. A second diode 138b is formed between the p-GaN layer 130 and the n-GaN layer 132. Diodes 138a and 138b are configured in series. The resulting capacitance from diodes 138a and 138b decreases and the device switching speed increases.

In another embodiment shown in FIG. 4a, the junction isolation feature 126 of the gate stack 122 is similar to the junction isolation feature 126 in FIG. 3a, but further includes an additional p-GaN layer 134 disposed on the n-GaN layer 132. The additional p-GaN layer 134 and n-GaN layer 132 are configured to form another diode for additional isolation effects. The additional p-GaN layer 134 is similar in composition and formation to the p-GaN layer 130. For example, the p-GaN layer 134 is doped with a p-type dopant such as magnesium, calcium, zinc beryllium, carbon, or a combination thereof.

Fig. 4b shows a schematic diagram of a GaN-based transistor of the semiconductor structure 100 with the gate stack 122 of fig. 4 a. Symbols "G", "S" and "D" denote a gate, a source and a drain, respectively. A 2-DEG channel is defined between the source and drain. Diode 138a is formed between p-GaN layer 130 and barrier layer 116 having n-type dopants. A second diode 138b is formed between the p-GaN layer 130 and the n-GaN layer 132. A third diode 138c is formed between the n-GaN layer 132 and the p-GaN layer 134. Diodes 138a, 138b, and 138c are configured in series. The resulting capacitance between the gate electrode and the channel from these diodes is further reduced, while the device switching speed is further increased.

In another embodiment shown in FIG. 5a, the junction isolation feature 126 of the gate stack 122 is similar to the junction isolation feature 126 in FIG. 3a, but further includes an additional p-GaN layer 134 disposed on the n-GaN layer 132 and an additional n-GaN layer 136 disposed on the p-GaN layer 134. Additional p-GaN layer 134 and additional n-GaN layer 136 are similar in composition and formation to p-GaN layer 130 and n-GaN layer 132, respectively. For example, the n-GaN layer 136 is doped with an n-type dopant such as silicon or oxygen.

Fig. 5b shows a schematic diagram of a GaN-based transistor of the semiconductor structure 100 with the gate stack 122 of fig. 5 a. Symbols "G", "S" and "D" denote a gate, a source and a drain, respectively. A 2-DEG channel is defined between the source and drain. Diode 138a is formed between p-GaN layer 130 and barrier layer 116 having n-type dopants. A second diode 138b is formed between the p-GaN layer 130 and the n-GaN layer 132. A third diode 138c is formed between the n-GaN layer 132 and the p-GaN layer 134. A fourth diode 138d is formed between the p-GaN layer 134 and the n-GaN layer 136. Diodes 138a, 138b, 138c, and 138d are configured in series. The resulting capacitance between the gate electrode and the channel from these diodes is further reduced, while the device switching speed is thereby further increased.

In one embodiment shown in FIG. 6a, junction isolation feature 126 of gate stack 122 includes an n-GaN layer 132 and a p-GaN layer 130 disposed on n-GaN layer 132. The gate stack 122 of FIG. 5a is similar to the gate stack 122 of FIG. 3a, but the p-GaN layer 130 and the n-GaN layer 132 are configured differently. The p-GaN layer 130 is doped with a p-type dopant such as magnesium, calcium, zinc beryllium, carbon, or a combination thereof. In one embodiment, the p-GaN layer 130 may be formed by MOCVD or other suitable techniques. In another embodiment, the thickness of the p-GaN layer 130 ranges between about 1nm and about 100 nm. The n-GaN layer 132 is doped with an n-type dopant such as silicon, oxygen, or a combination thereof. In one embodiment, the n-GaN layer 132 may be formed by MOCVD or other suitable techniques. In another embodiment, the thickness of the n-GaN layer 132 ranges between about 1nm and about 100 nm.

Fig. 6b shows a schematic diagram of a GaN-based transistor of the semiconductor structure 100 with the gate stack 122 of fig. 6 a. Diode 138e is formed between p-GaN layer 130 and n-GaN layer 132 for isolation to prevent gate leakage.

In another embodiment shown in fig. 7a, the junction isolation feature 126 of the gate stack 122 is similar to the junction isolation feature 126 in fig. 3a, but has a different structure. Specifically, the n-GaN layer 132 is disposed on the barrier layer 116. The p-GaN layer 130 is disposed on the n-GaN layer 132. An additional n-GaN layer 136 is disposed on the p-GaN layer 130.

Fig. 7b shows a schematic diagram of a GaN-based transistor of the semiconductor structure 100 with the gate stack 122 of fig. 7 a. A diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132. Another diode 138f is formed between p-GaN layer 130 and n-GaN layer 136. Diodes 138e and 138f are configured in series. The resulting capacitance between the gate electrode and the channel from these diodes provides isolation to place gate leakage and also enhances device switching speed.

In another embodiment shown in FIG. 8a, the junction isolation feature 126 of the gate stack 122 is similar to the junction isolation feature 126 in FIG. 5a, but configured differently. Gate stack 122 in fig. 8a includes n-GaN layer 132 on barrier layer 116, p-GaN layer 130 on n-GaN layer 132, additional nn-GaN layer 136 on p-GaN layer 130, and additional p-GaN layer 134 disposed on additional n-GaN layer 136. Each of the n-GaN layer and the p-GaN layer is similar in composition and formation to the corresponding layer of gate stack 122 in fig. 4 a. For example, the n-GaN layer 136 is doped with an n-type dopant such as silicon or oxygen.

Fig. 8b shows a schematic diagram of a GaN-based transistor of the semiconductor structure 100 with the gate stack 122 of fig. 8 a. Symbols "G", "S" and "D" denote a gate, a source and a drain, respectively. A 2-DEG channel is defined between the source and drain. Diode 138e is formed between n-GaN layer 132 and p-GaN layer 130. A second diode 138f is formed between the p-GaN layer 130 and the additional n-GaN layer 136. A third diode 138g is formed between n-GaN layer 136 and additional p-GaN layer 134. Diodes 138e, 138f, and 138g are configured in series. The resulting capacitance between the gate electrode and the channel from these diodes is reduced and the device switching speed is thereby further increased.

Returning to fig. 1a, the semiconductor structure 100 further includes a field plate 148 configured proximate to the gate stack 122 and designed to redistribute the electric field distribution, thereby reducing the surface field (RESURF) and increasing the breakdown voltage. Other advantages may also be present according to various embodiments, such as improved figure of merit (FOM), such as Qgd, Ronsp Cgd, Ron Coss, Ron Ciss, Ron Crss, and the like. For example, the corresponding GaN-based transistor may be stabilized by reducing the shift or no shift of the threshold voltage. In the depicted embodiment, the field plate 148 is disposed on the first layer of dielectric material 150 and is positioned between the gate stack 122 and the drain member 120B. The field plate 148 extends from the bottom of the trench to the outside of the trench toward the drain feature 120B. Specifically, in the depicted embodiment, the field plate 148 is disposed horizontally away from the drain feature 120B. In other words, the field plate 148 is configured not to overlap with the drain feature 120B in the top view. The field plate 148 includes a conductive material, such as a metal, metal alloy, silicide, other suitable conductive material, or combinations thereof. In some embodiments, the field plate 148 comprises titanium nitride, titanium aluminum, aluminum copper, or combinations thereof. In the depicted embodiment, the field plate 148 is electrically connected to the source feature 120A through the conductive elements 152 and 154 of the interconnect structure. The source has a stable voltage (0V or Vss) compared to the field plate connected to the gate, which does not have a trapping effect below the field plate. In some examples, the conductive element 152 may include a metal line and a via extending vertically from the source feature 120A to the metal line. The conductive element 154 can include a via extending from the field plate 148 to the conductive element 152. The conductive elements 152 and 154 are at least partially embedded in another layer of dielectric material 156.

Specifically, the field plate 148 has a stepped structure (stepped structure) having at least three segments that are sequentially connected and alternately oriented in different directions, such as two orthogonal directions (X and Y directions). In the depicted embodiment, the field plate 148 includes three segments, namely a first segment 148A extending horizontally (in the X-direction), a second segment 148B extending vertically (in the Y-direction) from the first segment 148A, and a third segment 148C extending horizontally (in the X-direction) from the second segment 148B. The disclosed stepped structure of the field plate 148 can effectively reduce the surface field and enhance the breakdown voltage, and is beneficial for other performance parameters. In off-state operation, the path from the drain to the source may have a large voltage drop and the peak electric field will appear in the boundary (such as the gate edge, field plate edge, metal edge …). More steps in the stepped structure of the field plate 148 can provide more electric field peaks and maintain more voltage drop in the channel, which is the voltage drop between the drain and source and is a component of the electric field. The structure and formation of the field plate 148 will be described in further detail later.

Turning to fig. 1b, a cross-sectional view of a semiconductor structure 180 having a gallium nitride GaN-based device constructed in accordance with one or more embodiments. The semiconductor structure 180 is similar to the semiconductor 100 of fig. 1 a. However, semiconductor structure 180 includes a GaN-based device having two electrodes and not a gate, also referred to as a GaN-based diode. The semiconductor structure 180 also includes a field plate 148 similarly disposed between the source feature 120A and the drain feature 120B, and the field plate 148 is electrically connected to the source feature 120A, such as by the conductive features 152 and 154. The field plate 148 extends from the bottom of the trench to the outside of the trench toward the drain feature 120B. Specifically, the field plate 148 is disposed horizontally away from the drain feature 120B. In other words, the field plate 148 is configured not to overlap with the drain electrode 120B in the top view.

Fig. 9 is a cross-sectional view of a semiconductor structure 182 with a GaN-based transistor constructed in accordance with one or more other embodiments. Semiconductor structure 182 and its method of fabrication are collectively described with reference to fig. 9, 2 a-8 a, and 2 b-8 b.

The semiconductor structure 182 is similar to the semiconductor structure 100 of fig. 1a, but further includes a layer of dielectric material (or insulating layer) 141 formed on the barrier layer 116 and disposed between the source feature 120A and the drain feature 120B. Specifically, a layer of dielectric material 141 is formed between barrier layer 116 and gate stack 122. According to various examples, the dielectric material layer 141 comprises a dielectric material selected from the group consisting of: silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Alumina (Al)₂O₃) Tantalum oxide (Ta)₂O₅) Titanium oxide (TiO)₂) Zinc oxide (ZnO)₂) Hafnium oxide (HfO)₂) Or a combination thereof. In one embodiment, the thickness of the dielectric material layer 141 ranges between about 3nm and about 100 nm. The dielectric material layer 141 may be formed by any suitable fabrication technique such as Chemical Vapor Deposition (CVD), PVD, Atomic Layer Deposition (ALD), or thermal oxidation. The dielectric material layer 141 also provides isolation to prevent gate leakage and also improves device switching speed.

The gate stack 122 of fig. 9 is similar to the gate stack 122 of fig. 1 a. For example, the gate stack 122 includes a junction isolation feature 126 disposed on the dielectric material layer 141 and a metal layer 124 disposed on the junction isolation feature 126. Further, according to various embodiments, the gate stack 122 may have any one of the structures shown in fig. 2a to 8 a.

In fig. 9, semiconductor structure 182 further includes a field plate 148 configured proximate to gate stack 122 and designed to redistribute the electric field distribution, thereby reducing the surface field and increasing the breakdown voltage. The field plate 148 is similar in structure, configuration and formation to the field plate 148 of fig. 1 a. In the depicted embodiment, the field plate 148 is disposed on the layer of dielectric material 150 and is positioned between the gate stack 122 and the drain member 120B. The field plate 148 extends from the bottom of the trench to the outside of the trench toward the drain feature 120B. Specifically, the field plate 148 is disposed horizontally away from the drain 120B. In other words, the field plate 148 is configured not to overlap with the drain electrode 120B in the top view. The field plate 148 includes a conductive material such as a metal, metal alloy, silicide, or other suitable conductive material. In the depicted embodiment, the field plate 148 is electrically connected to the source feature 120A through the conductive elements 152 and 154 of the interconnect structure. Specifically, the field plate 148 has a stepped structure having at least three segments that are sequentially connected and alternately oriented in different directions, such as two orthogonal directions (X and Y directions). In the depicted embodiment, the field plate 148 includes three segments, namely a first segment 148A extending horizontally (in the X direction), a second segment 148B extending vertically (in the Y direction) from the first segment, and a third segment 148C extending horizontally (in the X direction) from the second segment.

FIG. 10 is a cross-sectional view of one embodiment of a semiconductor structure 184 having a GaN-based transistor. The semiconductor structure 184 is similar to the semiconductor structure 100 of fig. 1a, but the gate stack 122 further includes a layer of dielectric material (or insulating layer) 144 disposed between the metal layer 124 and the junction isolation feature 126. According to various examples, the dielectric material layer 144 includes a dielectric material selected from the group consisting of: SiO 2₂、Si₃N₄、Al₂O₃、Ta₂O、TiO₂、ZnO₂、HfO₂Or a combination thereof. In one embodiment, the thickness of the dielectric material layer 144 ranges between about 3nm and about 100 nm. The dielectric material layer 144 may be formed by any suitable fabrication technique, such as CVD, PVD, ALD, or thermal oxidation. The dielectric material layer 144 also provides isolation to prevent gate leakage and also improves device switching speed. The junction isolation member 126 may have a different structure, such as any one of those shown in fig. 2a to 2b to 8a to 8 b.

The semiconductor structure 184 in fig. 10 also includes a field plate 148 configured proximate to the gate stack 122 and designed to redistribute the electric field distribution, thereby reducing the surface field and increasing the breakdown voltage. The field plate 148 is similar in structure, configuration and formation to the field plate 148 of fig. 1 a. In the depicted embodiment, the field plate 148 is disposed on the layer of dielectric material 150 and is positioned between the gate stack 122 and the drain member 120B. The field plate 148 includes a conductive material, such as a metal, metal alloy, silicide, or other suitable conductive material, or combinations thereof. In the depicted embodiment, the field plate 148 is electrically connected to the source feature 120A through the conductive elements 152 and 154 of the interconnect structure. Specifically, the field plate 148 has a stepped structure having at least three segments that are sequentially connected and alternately oriented in different directions, such as two orthogonal directions (X and Y directions). In the depicted embodiment, the field plate 148 includes three segments, namely a first segment 148A extending horizontally (in the X-direction), a second segment 148B extending vertically (in the Y-direction) from the first segment 148A, and a third segment 148C extending horizontally (in the X-direction) from the second segment 148B.

Fig. 11 is a flow chart of a method 200 of fabricating a semiconductor structure having a III-V compound device, or specifically a GaN-based device, such as 100, 180, 182, or 184, according to some embodiments. The method 200 includes block 202 to form a III-V semiconductor compound-based device, such as a GaN-based transistor including the channel layer 118, the source feature 120A, the drain feature 120B, and the gate stack 122 as described in fig. 1 a. At block 204, a first dielectric layer 150 is formed on the III-V semiconductor compound based device by deposition (such as CVD) and then additionally by a CMP process. At block 206, the first dielectric layer 150 is patterned to form trenches in the first dielectric layer 150. Block 206 may include one or more patterning processes to form trenches having a desired profile such that field plates 148 having a desired stepped structure are formed. At 208, an electrically conductive layer is deposited by a suitable deposition, such as PVD, over the first dielectric layer 150 and in the trenches of the first dielectric layer 150. At 210, the conductive layer is patterned to form a field plate 148 having a stepped structure. The field plate 148 extends from the bottom of the trench to the outside of the trench toward the drain feature 120B. At 212, an interconnect structure is formed over the III-V semiconductor compound based device and the field plate 148 such that the field plate 148 is electrically connected to the source feature 120A. The method 200 may also include other manufacturing processes performed at block 214 before, during, and/or after the operations described above.

Fig. 12-19 are cross-sectional views of a semiconductor structure 100 constructed in accordance with some embodiments at various stages of manufacture. The method 200 of fabricating III-V compound based devices is described in detail below with reference to these figures. The semiconductor structure 100 serves as an exemplary structure fabricated by the method 200.

Referring to fig. 12, III-V semiconductor compound-based devices, such as GaN-based transistors, are formed on a substrate 110. The III-V semiconductor compound-based device includes a channel layer 118 configured to form a functional field effect transistor, a source feature 120A, a drain feature 120B, and a gate stack 122. The structure and formation of a III-V semiconductor compound based device is depicted in fig. 1 a. In particular, the gate stack 122 may have different structures, such as those shown in fig. 1a, 2 a-8 b, and 9-10.

Referring to fig. 13, a first dielectric layer 150 is formed on the III-V semiconductor compound based device by deposition, such as CVD, flowable CVD (CVD), spin-on coating, ALD, other suitable deposition, or combinations thereof. The first dielectric layer 150 comprises one or more dielectric materials such as silicon oxide, silicon nitride, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. In some embodiments, the formation of the first dielectric layer 150 includes deposition and CMP.

Referring to fig. 14, the first dielectric layer 150 is patterned to form a trench 160 in the first dielectric layer 150. The operation for patterning the first dielectric layer 150 may include one, two, or more patterning processes applied to the first dielectric layer 150 to form trenches 160 having a desired profile such that field plates 148 are subsequently formed with a desired stepped structure. For example, the first dielectric layer 150 may be patterned two, three, or more times such that the trench 160 includes a stepped profile. The patterning process may include forming a hard mask and applying an etching process to the first dielectric layer 150 through the opening of the hard mask to form a trench in the first dielectric layer 150. The hard mask may be formed by a procedure that includes: depositing a hard mask material layer and etching the hard mask material layer through the openings of the patterned photoresist layer. In some examples, the hard mask material layer comprises silicon oxide and silicon nitride subsequently deposited on the first dielectric layer 150. The hard mask layer may be formed by thermal oxidation, CVD, ALD, or any other suitable method. The process for forming the hard mask further includes forming a patterned photoresist (resist) layer by a photolithography process, and etching the hard mask material layer through the opening of the patterned resist layer to transfer the opening to the hard mask material layer. An exemplary photolithography process may include forming a resist layer, exposing the resist through a photolithography exposure process, performing a post-exposure bake process, and creating a photoresist layer to form a patterned photoresist layer. The lithographic process may optionally be replaced by other techniques such as e-beam writing, ion-beam writing, maskless patterning, or molecular printing. In some other embodiments, the patterned photoresist layer may be used directly as an etch mask for an etching process to form the trench. The etching process may include dry etching, wet etching, or a combination thereof with one or more suitable etchants to etch the first dielectric layer 150.

Referring to fig. 15, conductive layer 148 is deposited by a suitable deposition, such as PVD, over first dielectric layer 150 and in trench 160 of first dielectric layer 150. Conductive layer 148 includes a conductive material such as a metal, metal alloy, silicide, other suitable conductive material, or combinations thereof. In some embodiments, conductive layer 148 includes titanium nitride, titanium aluminum, aluminum copper, or combinations thereof. In still other embodiments, conductive layer 148 includes two or more layers of conductive material, such as a barrier layer and a fill metal layer. In still other embodiments, the barrier layer comprises titanium nitride and titanium, or tantalum nitride and tantalum, and the fill metal layer comprises aluminum copper, aluminum, tungsten, other suitable metals, or combinations thereof.

Referring to fig. 16, the conductive layer 148 is patterned to form field plates, also labeled 148. The field plate 148 has a stepped structure. The patterning process includes patterning the first dielectric layer 150 similar to the patterning process but with a different etchant or etchants and process conditions. For example, the patterning process may include a photolithography process and etching, and the patterned hard mask may be additionally used as an etching mask. In the depicted embodiment, the field plate 148 includes three segments 148A, 148B, and 148C that are continuously connected and alternately oriented.

A multi-layer interconnect structure is formed to electrically connect the field plate 148 to the source feature 120A. The multi-level interconnect structure is designed to couple various devices to form a functional integrated circuit. The multi-layer interconnect structure includes vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines distributed in multiple metal layers. In the depicted embodiment, the multilayer interconnect structure includes conductive features 152 and 154 configured to electrically connect the field plate 148 to the source feature 120A. The multilayer interconnect structure can be configured differently with different conductive elements to electrically connect the field plate 148 to the source feature 120A.

The formation of the multi-layer interconnect structure may include any suitable technique or procedure. For example, the multilayer interconnect structure may be formed by: a dual damascene process or a single damascene process, such as a damascene process implemented in a copper-based multilayer interconnect structure, optionally a metal deposition and patterning process, such as a process implemented in an aluminum-based multilayer interconnect structure, or other suitable techniques. In accordance with some embodiments, a multilayer interconnect structure, and in particular its conductive features 152 and 154, is described below.

Referring to fig. 17, a second dielectric layer 156 is formed over the first dielectric layer 150 and the field plate 148 by deposition, such as CVD, PVD, spin coating, ALD, other suitable deposition, or combinations thereof. The second dielectric layer 156 may be similar or different in composition from the first dielectric layer 150 and may include one or more dielectric materials, such as silicon oxide, silicon nitride, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. In some examples, the second dielectric layer 156 includes an etch stop layer (such as silicon nitride) and a fill dielectric layer (such as silicon oxide or a low-k dielectric material) disposed on the etch step layer. In some embodiments, the formation of the second dielectric layer 156 includes deposition and CMP.

Still referring to fig. 17, the second dielectric layer 156 is patterned to form trenches 162 and 164 to at least partially expose the source features 120A and the field plates 148 within the respective trenches. The patterning process is similar to the other patterning processes described above, and may include a photolithography process and etching, and may additionally use a hard mask as an etch mask. In some embodiments, trenches 162 and 164 may be formed separately or collectively by two or more photolithography and etching processes.

Referring to fig. 18, one or more layers 166 of conductive material are deposited in trenches 162 and 164 and on second dielectric layer 156 by a suitable deposition, such as PVD, CVD, plating, other suitable deposition, or combinations thereof. A seed layer is deposited in the trench, for example by PVD, and an electroless plating process is applied to fill the metal in the trench. In some embodiments, a high temperature reflow process may be applied to the conductive material to achieve better trench fill.

Referring to fig. 19, the layer of conductive material 166 is patterned to form the conductive features 152 and 154 by a procedure that includes a photolithography process and etching. The patterning process is similar to the other patterning processes described above, and may include a photolithography process and etching, and may additionally use a hard mask as an etch mask.

In the semiconductor structure 100 of fig. 19, the field plate 148 is not only designed and formed to have a stepped structure, but is also configured with various sizes and distances to achieve optimized performance. In particular, field plate 148 is designed to span width W and height H, and is positioned horizontally a distance S from gate stack 122. The drain member 120B is a first distance D1 from the gate stack 122. The conductive feature 152 is a second distance D2 from the gate stack 122. All those dimensions were designed based on an understanding of the electric field distribution, experimental data, and theoretical analysis for improved performance including breakdown voltage and threshold voltage shift (such as that of fig. 28). In some embodiments, width W ranges between 0.25 μm and 5 μm and height H ranges between 30nm and 500 nm. In particular, it has been found experimentally that the relevant points in the field plate are all located between the drain and source electrodes. Thus, in some embodiments, the field plate 148 is designed such that the first ratio S/D1 is less than 1, such as 0 ≦ S/D ≦ 95%, and the second ratio W/D1 is greater than 5%, such as 5 ≦ W/D1 ≦ 100%; and the third ratio H/D2 is less than 50%, such as 0 ≦ S/D ≦ 50%. In some embodiments, the first ratio S/D1 ranges between 5% and 15%; the second ratio W/D1 ranges between 40% and 60%; and the third ratio H/D2 ranges between 5% and 15%.

Similarly, the field plate 148 in the semiconductor structure 180 of fig. 1b is not only designed and formed to have a stepped structure, but is also configured with various dimensions and distances to achieve optimal performance. In particular, referring to fig. 1b, the field plate 148 is designed to span the width W and the height H, and is positioned horizontally a third distance D3 from the source feature 120A. The source feature 120A and the drain feature 120B are a fourth distance D4 apart. The conductive feature 152 is a fifth distance D5 from the barrier layer 116. All those dimensions were designed based on an understanding of the electric field distribution, experimental data, and theoretical analysis for improved performance including breakdown voltage. In particular, according to some embodiments, the fourth ratio D1/D4 is less than 1, such as 0 ≦ S/D ≦ 95%; the fifth ratio W/D4 is greater than 5%, such as 5 ≦ W/D1 ≦ 100%; and a sixth ratio H/D5 is less than 50%, such as 0 ≦ S/D ≦ 50%. In some embodiments, the fourth ratio D1/D4 ranges between 50% and 70%; the range of the fifth ratio W/D4 is between 20% and 30%; and the sixth ratio H/D5 ranges between 5% and 15%.

The conductive members 152 and 154 may be separately formed. One embodiment is provided in cross-sectional views with reference to fig. 20-24. The conductive features 154 are formed by a single damascene process that includes patterning the second dielectric layer 156 to form trenches 164, as shown in fig. 20; and filling the trench 164 with one or more conductive materials by deposition; and a CMP process is performed to remove excess conductive material on the second dielectric layer 156, thereby forming the conductive features 154, as shown in fig. 21. The conductive features 152 are formed by a process that includes: patterning the second dielectric layer 156 to form trenches 162, as shown in fig. 22; depositing a layer of conductive material 166 on the second dielectric layer 156 and in the trenches 162 by a suitable deposition method, as shown in fig. 23; and a patterning process is performed on the conductive material layer 166 to form the conductive features 152, as shown in fig. 24.

Fig. 25-27 are cross-sectional views of a semiconductor structure 100 constructed in accordance with some other embodiments. The semiconductor structure 100 in fig. 27 is similar to the semiconductor structure 100 in fig. 1a, 9, 10, 19, or 24, except that the field plate 148 in fig. 27 includes five segments with a stepped structure that are continuously connected and alternately oriented in two orthogonal directions (X and Y directions). Such a field plate 148 may be formed by the method 200, but the block 206 includes two patterning processes applied to the first dielectric layer 150 to form a trench having a stepped structure. In particular, as shown in fig. 25, a first patterning process is applied to the first dielectric layer 150 to form the trench 170, and as shown in fig. 26, a second patterning process is also applied to the first dielectric layer 150 to form the trench 172. Thereafter, operation 208 and 212 are performed to form the field plate 148, as shown in fig. 27. In an alternative embodiment, the semiconductor structure 100 is a two-terminal device without the gate stack 122, but the field plate has a stepped structure with five segments. In some embodiments, the field plate 148 in the semiconductor structure 100 may include a stepped structure having 4, 6, 7, 8, or more segments formed by a similar procedure. For example, instead of two patterning processes of the dielectric material layer 150, the method may include three or more patterning processes to obtain a desired trench profile, such that the field plate 148 may have individual segments formed in the trenches.

FIG. 28 is a diagrammatic view of an electric field (electric field) in the X direction constructed in accordance with some embodiments. The electric field strength is represented by the vertical axis. Graph (a) in fig. 28 includes two data sets, a first set labeled "FP 1" being associated with a semiconductor structure having a field plate with the disclosed stepped structure (such as one of semiconductor structures 100 in fig. 19), and a second set labeled "FP 2" being associated with a semiconductor structure having a field plate with a structure other than the stepped structure (as a reference). Specifically, the electric field of EP1 has three peaks at different positions, corresponding to positions L1, L2 and L3 of fig. 19, respectively. In particular, the second peak is contributed by the junction portions of the first and second segments of the field plate 148, which are absent in field plates having different structures. This redistributes the electric field and reduces the maximum electric field (at P3), thereby reducing the breakdown voltage accordingly. Due to the geometry of the disclosed stepped structure of the field plate (such as 148 in fig. 19), various corner portions of the edge of the field plate having the stepped structure will more contribute to redistributing the electric field and reducing the surface field, thereby correspondingly reducing the breakdown voltage. The field plate 148 in fig. 27 has a stepped structure with five segments and more edge portions that will redistribute the electric field more efficiently and reduce the surface field.

Graph (b) in fig. 28 shows the gate leakage current (Idoff) versus the gate voltage (Vd). The gate voltage is represented on the horizontal axis and the gate leakage current is represented on the vertical axis. The data show that the gate leakage current of the semiconductor structure with the field plate having the stepped structure is substantially reduced.

Graph (c) in fig. 28 shows the dynamic Ronratio (or doron ratio) versus the gate voltage (Vd). The gate voltage is represented on the horizontal axis and the dynamic Ronratio is presented on the vertical axis. The data show that the dynamic Ronratio of the semiconductor structure with the stepped structure field plate is substantially increased. The dRon ratio is the dynamic Ron ratio. For example, the dynamic Ron in 60V is defined as Rds (60V)/Rds (1V). Rds (60V/1V) means Rds under sustained transient switching stress Vds-60/1V. If the value is closer to 1, this means better channel trapping effects, where the AC Vds stress will cause less trapping in the channel.

Although various embodiments are provided and explained in the present disclosure. Other alternatives and embodiments may be used without departing from the spirit of the invention. For example, a GaN-based device, such as 100, 180, 182, or 184, may further include an aluminum nitride (AlN) layer disposed between the buffer layer 114 and the barrier layer 116. In one embodiment, an AlN layer is selectively epitaxially grown on the buffer layer 114. The AlN layer may be epitaxially grown by MOVPE using an aluminum-containing precursor and a nitrogen-containing precursor. The aluminum-containing precursor comprises TMA, TEA or other suitable chemical. Nitrogen-containing precursors include ammonia, TBAm, phenylhydrazine, or other suitable chemicals. In one example, the AlN layer has a thickness ranging between about 5nm and about 50 nm.

Alternatively, an AlN layer may be used as a barrier layer instead of the AlGaN layer. In another embodiment, the dimensions of the various n-GaN layers and p-GaN layers may vary depending on the specifications, performance, and circuit requirements of the device. For example, the thickness of the various n-GaN layers and p-GaN layers may be adjusted based on threshold voltage or other device/circuit considerations. In another embodiment, the gate stack 122 of a semiconductor structure (such as 100, 182, or 184) may include more n-GaN layers and/or p-GaN layers configured in the junction isolation feature 126.

The invention provides a III-V compound-based device having a field plate with a stepped structure and a method of manufacturing the same. The disclosed field plate has a plurality of segments that are continuously connected and alternately oriented in different directions. The disclosed field plate can effectively reduce the surface field, thereby increasing the breakdown voltage or maintaining a high breakdown voltage, reducing leakage current, and reducing the shift in threshold voltage.

In one exemplary aspect, the present invention provides a semiconductor structure. The semiconductor structure includes: a gallium nitride (GaN) layer on the substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source electrode part, wherein the field plate includes a stepped structure.

In some embodiments, the field plate includes a first segment extending horizontally, a second segment extending vertically from the first segment, and a third segment extending horizontally from the second segment. In some embodiments, the first segment is horizontally spaced from the gate stack by a first dimension D1; the drain feature is horizontally spaced from the gate stack by a second dimension D2; and the first ratio D1/D2 is less than 95%. In some embodiments, the field plate spans width W horizontally; and the second ratio W/D2 is greater than 5% and less than 100%. In some embodiments, the source member is electrically connected to the field plate through a conductive member; the conductive feature extends horizontally from the source feature; the conductive feature is vertically spaced from the gate stack by a third dimension D3; the field plate vertically spans a height H; and the third ratio H/D3 is less than 50%. In some embodiments, the field plate further comprises a fourth segment extending vertically from the third segment and a fifth segment extending horizontally from the fourth segment. In some embodiments, the gate stack comprises a III-V compound p-type doped layer. In some embodiments, the gate stack further comprises a dielectric layer underlying the III-V compound p-type doped layer. In some embodiments, the gate stack further comprises a III-V compound n-type doped layer located adjacent to the III-V compound p-type doped layer. In some embodiments, the III-V compound n-type doped layer comprises an n-type gallium nitride layer and the III-V compound p-type doped layer comprises a p-type gallium nitride layer. In some embodiments, the III-V compound p-type doped layer is doped with an impurity selected from the group consisting of magnesium, calcium, zinc, beryllium, and carbon; and the III-V compound n-type doped layer is doped with an impurity selected from the group consisting of silicon and oxygen. In some embodiments, the field plate comprises a conductive material selected from the group consisting of: titanium nitride, titanium aluminum, aluminum copper, combinations thereof. In some embodiments, the gallium nitride layer is undoped or unintentionally doped. In some embodiments, the source feature, the drain feature, and the gate stack are configured with the gallium nitride layer and the aluminum gallium nitride layer to form a high electron mobility transistor.

In another exemplary aspect, the present invention provides a semiconductor structure. The semiconductor structure includes: a first III-V compound layer on the substrate; a second III-V compound layer directly on the first III-V compound layer, the second III-V compound layer being different in composition from the first III-V compound layer and further comprising aluminum; a gate stack on the second III-V compound layer; a source feature and a drain feature disposed on the second III-V compound layer; and a field plate disposed over the gate stack and electrically connected to the source feature, wherein the field plate includes at least three segments having a stepped structure.

In some embodiments, the substrate comprises one of a sapphire substrate, a silicon substrate, and a silicon carbide substrate; the first III-V compound layer includes a gallium nitride (GaN) layer; the second III-V compound layer includes an aluminum gallium nitride (AlGaN) layer; the gate stack includes a p-type doped III-V compound layer. In some embodiments, the field plate includes a first segment extending horizontally, a second segment extending vertically from the first segment, and a third segment extending horizontally from the second segment. In some embodiments, the field plate further comprises a fourth segment extending vertically from the third segment and a fifth segment extending horizontally from the fourth segment.

In yet another example aspect, the present disclosure provides a method. The method comprises the following steps: forming a first III-V compound layer on a substrate; forming a second III-V compound layer on the first III-V compound layer, wherein the second III-V compound layer is different in composition from the first III-V compound layer and further includes aluminum; forming a gate stack on the second III-V compound layer; forming a source feature and a drain feature on the second III-V compound layer, and the source feature and the drain feature being interposed by the gate stack; and forming a field plate over the gate stack and electrically connecting the field plate to the source feature, wherein the field plate comprises at least three segments configured in a stepped configuration.

In some embodiments, forming the first III-V compound layer includes forming an undoped gallium nitride layer; forming the second III-V compound layer includes forming an aluminum gallium nitride layer; and forming the field plate includes: forming a dielectric material layer on the gate stack, the source feature and the drain feature, performing a first patterning process to form a trench in the dielectric material layer, depositing a conductive layer on the dielectric material layer, and performing a second patterning process on the conductive layer, thereby producing a patterned conductive layer having a first section located in a bottom surface of the trench, a second section located on a sidewall of the trench, and a third section located on a top surface of the dielectric material layer, wherein the first section, the second section and the third section are continuously connected.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.