阅读说明：本技术 半导体复合衬底、半导体器件及制备方法 (Semiconductor composite substrate, semiconductor device and preparation method ) 是由 田野 母凤文 于 2021-10-26 设计创作，主要内容包括：本申请提供了一种半导体复合衬底、半导体器件及制备方法,属于微电子制造技术领域,半导体复合衬底具体包括基底层；键合界面层,位于基底层上表面；以及SiC转移层,位于键合界面层的上表面,SiC转移层由SiC晶圆的剥离转移得到。半导体复合衬底制备方法：获取基底层和SiC晶圆；向SiC晶圆中注入离子形成离子化SiC晶圆；对基底层和离子化SiC晶圆进行键合形成键合体；进行高温退火,退火后离子化SiC晶圆在离子注入最大浓度所对应的深度处沿与离子化SiC晶圆表面平行的方向分裂,对离子化SiC晶圆远离键合界面层的部分进行剥离,离子化SiC晶圆靠近键合界面层的部分为SiC转移层。通过本申请的处理方案,可节省SiC原材料,降低制造成本,简化工艺流程,提高生产效率。(The application provides a semiconductor composite substrate, a semiconductor device and a preparation method, which belong to the technical field of microelectronic manufacturing, wherein the semiconductor composite substrate specifically comprises a substrate layer; the bonding interface layer is positioned on the upper surface of the substrate layer; and the SiC transfer layer is positioned on the upper surface of the bonding interface layer and is obtained by peeling and transferring the SiC wafer. The preparation method of the semiconductor composite substrate comprises the following steps: obtaining a substrate layer and a SiC wafer; implanting ions into the SiC wafer to form an ionized SiC wafer; bonding the substrate layer and the ionized SiC wafer to form a bonding body; and performing high-temperature annealing, splitting the ionized SiC wafer at the depth corresponding to the maximum ion implantation concentration along the direction parallel to the surface of the ionized SiC wafer after annealing, and stripping the part of the ionized SiC wafer far away from the bonding interface layer, wherein the part of the ionized SiC wafer near the bonding interface layer is an SiC transfer layer. By the processing scheme, SiC raw materials can be saved, the manufacturing cost is reduced, the process flow is simplified, and the production efficiency is improved.)

1. A semiconductor composite substrate, characterized in that the semiconductor composite substrate comprises:

a base layer;

the bonding interface layer is positioned on the upper surface of the substrate layer and is used for assisting the planarization of the surface of the substrate layer; and

and the SiC transfer layer is positioned on the upper surface of the bonding interface layer and is obtained by peeling and transferring the SiC wafer.

2. The semiconductor composite substrate according to claim 1, wherein the material of the SiC transfer layer comprises 3C-SiC, 4H-SiC or 6H-SiC, the SiC transfer layer has a thickness in the range of 0.2 μ ι η to 5 μ ι η, and the SiC transfer layer has a diameter in the range of 6inch to 12 inch.

3. The semiconductor composite substrate according to claim 1, wherein the material of the base layer is Si, the thickness of the base layer is in a range of 300 μm to 1mm, the diameter of the base layer is greater than or equal to the diameter of the SiC transfer layer, and the diameter of the base layer is in a range of 6inch to 12 inch.

4. The semiconductor composite substrate according to claim 1, wherein the base layer is made of polycrystalline AlN, the base layer has a thickness in a range of 300 μm to 1mm, the base layer has a diameter greater than or equal to a diameter of the SiC transfer layer, and the base layer has a diameter in a range of 6inch to 12 inch.

5. The semiconductor composite substrate according to claim 1, wherein a material of the bonding interface layer comprises Si, SiC, AlN, Al₂O₃、SiN_xDiamond and a high melting point compound containing W, the bonding interface layer having a thickness in a range of 10nm to 5 μm.

6. A semiconductor device comprising the semiconductor composite substrate according to any one of claims 1 to 5, and an epitaxial buffer layer and an epitaxial layer which are provided on the semiconductor composite substrate in this order, the semiconductor composite substrate comprising:

a base layer;

the bonding interface layer is positioned on the upper surface of the substrate layer and is used for assisting the surface planarization of the substrate layer; and

and the SiC transfer layer is positioned on the upper surface of the bonding interface layer and is obtained by peeling and transferring the SiC wafer.

7. The semiconductor device of claim 6, wherein the material of the epitaxial buffer layer is a combination of one or more of AlN, AlGaN, GaN and SiC, the thickness of the epitaxial buffer layer is in the range of 10nm-3 μm, and the growth method of the epitaxial buffer layer includes, but is not limited to, metal-organic chemical vapor deposition, molecular beam epitaxy or liquid phase epitaxy.

8. The semiconductor device according to claim 6, wherein the material of the epitaxial layer is GaN, Ga₂O₃And Si, the thickness of the epitaxial layer ranges from 200nm to 10 μm, and the epitaxial layer is grown by a method including but not limited to metal organic chemical vapor deposition, molecular beam epitaxy or liquid phase epitaxy.

9. A method for producing a semiconductor composite substrate according to any one of claims 1 to 5, comprising:

obtaining a substrate layer and a SiC wafer;

growing a bonding interface layer on the substrate layer, and carrying out surface planarization on the bonding interface layer;

implanting ions into the SiC wafer to form an ionized SiC wafer, wherein the implantation depth of the ions is smaller than the thickness of the SiC wafer;

bonding the substrate layer with the bonding interface layer and the ionized SiC wafer to form a bonded body, wherein the bonding interface layer is positioned between the substrate layer and the ionized SiC wafer;

and carrying out high-temperature annealing on the bonding body, splitting the ionized SiC wafer into two parts at the depth corresponding to the maximum ion implantation concentration along the direction parallel to the surface of the ionized SiC wafer after annealing, stripping the part of the ionized SiC wafer far away from the bonding interface layer, and taking the part of the ionized SiC wafer close to the bonding interface layer as a SiC transfer layer.

10. The method for producing a semiconductor composite substrate according to claim 9, wherein the ions implanted into the SiC wafer are one or a combination of H ions and He ions.

11. The method for producing a semiconductor composite substrate according to claim 9, wherein the ion is implanted in a dose range ofThe implantation depth of the ions ranges from 0.3 μm to 5 μm.

12. A method for manufacturing a semiconductor device according to any one of claims 6 to 8, comprising:

obtaining a substrate layer and a SiC wafer;

growing a bonding interface layer on the substrate layer, and carrying out surface planarization on the bonding interface layer;

implanting ions into the SiC wafer to form an ionized SiC wafer, wherein the implantation depth of the ions is smaller than the thickness of the SiC wafer;

bonding the substrate layer with the bonding interface layer and the ionized SiC wafer to form a bonded body, wherein the bonding interface layer is positioned between the substrate layer and the ionized SiC wafer;

carrying out high-temperature annealing on the bonding body, splitting the ionized SiC wafer into two parts at the depth corresponding to the maximum ion implantation concentration along the direction parallel to the surface of the ionized SiC wafer after annealing, stripping the part of the ionized SiC wafer far away from the bonding interface layer, and taking a SiC transfer layer as the part of the ionized SiC wafer close to the bonding interface layer to obtain a semiconductor composite substrate;

growing an epitaxial buffer layer on the upper surface of the semiconductor composite substrate;

and growing an epitaxial layer on the epitaxial buffer layer.

Technical Field

The present disclosure relates to the field of microelectronic fabrication technologies, and in particular, to a semiconductor composite substrate, a semiconductor device, and a method for manufacturing the semiconductor composite substrate.

Background

Gallium oxide and gallium nitride have the advantages of wide band gap, high breakdown field strength and the like, the Baliga factor of the gallium oxide and the gallium nitride is higher than that of silicon by several orders of magnitude, and the potential of the gallium oxide and the gallium nitride in the application of next-generation power electronic products draws wide attention of researchers. However, gallium oxide, gallium nitride, has not high thermal conductivity, reducing the operating performance and reliability of devices made from these materials. For example, gallium oxide has a highly anisotropic crystal structure due to its monoclinic system, the thermal conductivity of gallium oxide bulk materials is at least an order of magnitude lower than that of other wide bandgap semiconductors, and the thermal conductivity of gallium oxide thin film materials is much lower than that of gallium oxide bulk materials. Local joule heating near the gate of the device in high frequency and high power environments causes the channel temperature to be too high, severely limiting the performance and reliability of devices made from gallium oxide materials.

To solve the above problems, power electronic devices are generally prepared by epitaxially growing a gallium oxide thin film on a substrate having high thermal conductivity such as SiC, diamond, AlN, or the like to achieve effective heat dissipation. However, high-quality substrates with high thermal conductivity, such as SiC, diamond, AlN, etc., have high material costs, which makes it difficult to reduce device costs, thereby limiting the applications of electronic devices made of gallium oxide, gallium nitride, etc.

Disclosure of Invention

In view of the above, embodiments of the present application provide a semiconductor composite substrate, a semiconductor device and a manufacturing method thereof, which at least partially solve the problem of high manufacturing cost of a high thermal conductivity substrate in the prior art.

In a first aspect, an embodiment of the present application provides a semiconductor composite substrate, including:

a base layer;

the bonding interface layer is positioned on the upper surface of the substrate layer and is used for assisting the planarization of the surface of the substrate layer; and

and the SiC transfer layer is positioned on the upper surface of the bonding interface layer and is obtained by peeling and transferring the SiC wafer.

According to a specific implementation of the embodiment of the application, the material of the SiC transfer layer comprises 3C-SiC, 4H-SiC or 6H-SiC, the thickness of the SiC transfer layer is in the range of 0.2-5 μm, and the diameter of the SiC transfer layer is in the range of 6-12 inch.

According to a specific implementation manner of the embodiment of the application, the material of the substrate layer is Si, the thickness of the substrate layer is in a range of 300 μm-1mm, the diameter of the substrate layer is larger than or equal to that of the SiC transfer layer, and the diameter of the substrate layer is in a range of 6inch-12 inch.

According to a specific implementation manner of the embodiment of the application, the material of the substrate layer is polycrystalline AlN, the thickness of the substrate layer is in a range of 300 μm-1mm, the diameter of the substrate layer is larger than or equal to that of the SiC transfer layer, and the diameter of the substrate layer is in a range of 6inch-12 inch.

According to a specific implementation manner of the embodiment of the application, the material of the bonding interface layer comprises Si, SiC, AlN and Al₂O₃、SiN_xDiamond and a high melting point compound containing W, the bonding interface layer having a thickness in a range of 10nm to 5 μm.

In a second aspect, an embodiment of the present application further provides a semiconductor device, where the semiconductor device includes the semiconductor composite substrate according to any one of the embodiments of the first aspect, and an epitaxial buffer layer and an epitaxial layer sequentially located on the semiconductor composite substrate, where the semiconductor composite substrate includes:

a base layer;

the bonding interface layer is positioned on the upper surface of the substrate layer and is used for assisting the surface planarization of the substrate layer; and

and the SiC transfer layer is positioned on the upper surface of the bonding interface layer and is obtained by peeling and transferring the SiC wafer.

According to a specific implementation manner of the embodiment of the application, the material of the epitaxial buffer layer is one or more of AlN, AlGaN, GaN and SiC, the thickness of the epitaxial buffer layer ranges from 10nm to 3 μm, and the growth method of the epitaxial buffer layer includes, but is not limited to, metal organic chemical vapor deposition, molecular beam epitaxy or liquid phase epitaxy.

According to a specific implementation manner of the embodiment of the present application, the epitaxial layer is made of GaN or Ga₂O₃And Si, the thickness of the epitaxial layer ranges from 200nm to 10 μm, and the epitaxial layer is grown by a method including but not limited to metal organic chemical vapor deposition, molecular beam epitaxy or liquid phase epitaxy.

In a third aspect, an embodiment of the present application further provides a method for manufacturing a semiconductor composite substrate according to any one of the embodiments of the first aspect, where the method includes:

obtaining a substrate layer and a SiC wafer;

growing a bonding interface layer on the substrate layer, and carrying out surface planarization on the bonding interface layer;

implanting ions into the SiC wafer to form an ionized SiC wafer, wherein the implantation depth of the ions is smaller than the thickness of the SiC wafer;

bonding the substrate layer with the bonding interface layer and the ionized SiC wafer to form a bonded body, wherein the bonding interface layer is positioned between the substrate layer and the ionized SiC wafer;

and carrying out high-temperature annealing on the bonding body, splitting the ionized SiC wafer into two parts at the depth corresponding to the maximum ion implantation concentration along the direction parallel to the surface of the ionized SiC wafer after annealing, stripping the part of the ionized SiC wafer far away from the bonding interface layer, and taking the part of the ionized SiC wafer close to the bonding interface layer as a SiC transfer layer.

According to a specific implementation manner of the embodiment of the application, the ions implanted into the SiC wafer are one or a combination of H ions and He ions.

According to a specific implementation manner of the embodiment of the present application, the implantation dose range of the ions isThe implantation depth of the ions ranges from 0.3 μm to 5 μm.

In a fourth aspect, embodiments of the present application further provide a method for manufacturing a semiconductor device according to any of the embodiments of the second aspect, where the method includes:

obtaining a substrate layer and a SiC wafer;

growing a bonding interface layer on the substrate layer, and carrying out surface planarization on the bonding interface layer;

implanting ions into the SiC wafer to form an ionized SiC wafer, wherein the implantation depth of the ions is smaller than the thickness of the SiC wafer;

bonding the substrate layer with the bonding interface layer and the ionized SiC wafer to form a bonded body, wherein the bonding interface layer is positioned between the substrate layer and the ionized SiC wafer;

carrying out high-temperature annealing on the bonding body, splitting the ionized SiC wafer into two parts at the depth corresponding to the maximum ion implantation concentration along the direction parallel to the surface of the ionized SiC wafer after annealing, stripping the part of the ionized SiC wafer far away from the bonding interface layer, and taking a SiC transfer layer as the part of the ionized SiC wafer close to the bonding interface layer to obtain a semiconductor composite substrate;

growing an epitaxial buffer layer on the upper surface of the semiconductor composite substrate;

and growing an epitaxial layer on the epitaxial buffer layer.

Advantageous effects

In the composite semiconductor substrate in the embodiment of the application, the base layer is bonded with the SiC wafer, and the SiC wafer is stripped to obtain a thin SiC transfer layer with a certain thickness by a stripping and transferring technology, so that the cost for manufacturing the composite substrate is reduced, and the residual thick SiC wafer raw material can be used for the preparation of the next composite substrate or other procedures, can be recycled, and saves materials; and the preparation process flow of the composite semiconductor substrate is simple, and the production efficiency is high.

In addition, when the base layer is made of Si, the low cost of the Si can effectively reduce the cost of the substrate material on the basis of keeping the advantages of high thermal conductivity, high breakdown field strength and the like of SiC; when polycrystalline AlN is used as the base layer, AlN with excellent thermal conductivity, thermal stability, high resistance, and other characteristics provides transistors fabricated using the substrate structure with superior high power performance and better thermal management.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a flowchart of a method for manufacturing a semiconductor composite substrate according to an embodiment of the present invention;

fig. 2 to 7 are schematic structural views corresponding to steps of a method for manufacturing a semiconductor composite substrate according to an embodiment of the present invention, wherein fig. 7 is a schematic structural view of the semiconductor composite substrate according to the present invention;

fig. 8 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

fig. 9 is a flowchart of a method of fabricating a semiconductor device according to an embodiment of the present invention.

In the figure: 1. a base layer; 2. bonding the interface layer; 3. a SiC wafer; 4. ionizing the SiC wafer; 41. ions; 42. a SiC peeling layer; 43. a SiC transfer layer; 5. an epitaxial buffer layer; 6. an epitaxial layer.

Detailed Description

The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.

In a first aspect, an embodiment of the present application provides a semiconductor composite substrate, whose structure refers to fig. 7, which specifically includes: the substrate comprises a substrate layer 1, a bonding interface layer 2 and a SiC transfer layer 43, wherein the bonding interface layer 2 is positioned between the substrate layer 1 and the SiC transfer layer 43, the bonding interface layer 2 is formed on the upper surface of the substrate layer 1 through a thin film growth process, and the surface roughness is reduced through a surface planarization process to assist the surface smoothing of the substrate layer 1. The SiC transfer layer 43 is obtained by lift-off transfer of the SiC wafer 3.

In one embodiment, the material of the SiC transfer layer 43 includes, but is not limited to, 3C-SiC, 4H-SiC, or 6H-SiC, the thickness of the SiC transfer layer 43 ranges from 0.2 μm to 5 μm, and the diameter of the SiC transfer layer 43 ranges from 6inch to 12 inch.

Further, the material of the substrate layer 1 includes, but is not limited to, Si or polycrystalline AlN; the thickness of the substrate layer 1 ranges from 100 mu m to 1mm, the diameter of the substrate layer 1 is larger than or equal to that of the SiC transfer layer 43, and the diameter of the substrate layer 1 ranges from 6inch to 12 inch. Preferably, the material of the base layer 1 is Si (100).

Further, the material of the bonding interface layer 2 includes, but is not limited to, Si, SiC, AlN, SiN_x、Al₂O₃Diamond, or a high-melting-point compound containing W may be one or more of them, and the above materials may have a single crystal structure or a polycrystalline or amorphous structure, and the thickness of the bonding interface layer 2 is in the range of 1nm to 5 μm.

In a second aspect, the present application also provides a method for manufacturing the above semiconductor composite substrate, including the steps of:

s101, obtaining a substrate layer 1 and a SiC wafer 3, and performing surface cleaning and chemical mechanical polishing on the substrate layer 1 and the SiC wafer 3 to enable the root-mean-square roughness RMS of the surfaces of the substrate layer 1 and the SiC wafer 3 to be less than 5 nm;

s102, growing a bonding interface layer 2 on the substrate layer 1, and flattening the surface of the bonding interface layer 2. In one embodiment, the bonding interface layer 2 is grown on the planarized surface (i.e., upper surface) of the substrate layer 1 by a thin film growth process such as Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), Atomic Layer Deposition (ALD), etc., and the bonding interface layer 2 is surface-planarized using surface cleaning and chemical mechanical polishing, etc., such that the root mean square roughness RMS of the surface of the bonding interface layer 2 is less than 5 nm. It should be noted that the thin film growth process used for growing the bonding interface layer 2 is not limited to the above-mentioned Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), Atomic Layer Deposition (ALD), etc., and the surface planarization means used for the bonding interface layer 2 is also not limited to the above-mentioned surface cleaning and chemical mechanical polishing, etc.

S103, implanting ions 41 into the SiC wafer 3 at a certain depth to form an ionized SiC wafer 4, wherein the implantation depth of the ions 41 is smaller than the thickness of the SiC wafer 3;

s104, bonding the substrate layer 1 with the bonding interface layer 2 and the ionized SiC wafer 4 to form a bonded body, wherein the bonding interface layer 2 is positioned between the substrate layer 1 and the ionized SiC wafer 4, and the specific bonding process is not particularly limited in the embodiment and can be implemented according to the existing bonding technology;

s105, carrying out high-temperature annealing on the bonding body, wherein the ionized SiC wafer 4 is at the depth (namely the projection distance R) corresponding to the maximum concentration of ions 41 after annealing_pWhere) is split into two parts in a direction parallel to the surface of the ionized SiC wafer 4, and the part of the ionized SiC wafer 4 remote from the bonding interface layer 2 (SiC exfoliation layer 42 in fig. 4 and 5) is delaminated, and the part of the ionized SiC wafer 4 near the bonding interface layer 2 is a SiC transfer layer 43.

In step S101, please refer to step S101 and fig. 2in fig. 1, a substrate layer 1 and a SiC wafer 3 are obtained.

As an example, the material of the substrate layer 1 may be selected according to actual needs, and preferably, the material of the substrate layer 1 includes, but is not limited to, Si or polycrystalline AlN; the thickness range of the substrate layer 1 is 100 mu m-1 mm. When the base layer 1 adopts Si, the low cost of the Si can effectively reduce the cost of the substrate material on the basis of keeping the advantages of high thermal conductivity, high breakdown field strength and the like of SiC; when polycrystalline AlN is used for the base layer 1, the excellent thermal conductivity, thermal stability, high resistance, etc. of AlN enable the transistors fabricated using the substrate structure to have superior high power performance and better thermal management.

In step S102, please refer to step S102 in fig. 1 and fig. 3, a bonding interface layer 2 is grown on the substrate layer 1.

In step S103, please refer to step S103 in fig. 1 and fig. 4, ions 41 are implanted into the SiC wafer 3 at a certain depth.

As an example, the ions 4 implanted into the SiC wafer 3 are one or a combination of H ions and He ions.

Further, the implantation dosage range of the ions 41 isThe implantation depth of the ions 41 ranges from 0.3 μm to 5 μm.

In step S104, please refer to step S104 and fig. 5 in fig. 1, the substrate layer 1 and the ionized SiC wafer 4 are bonded to form a bond.

As an example, the material of the bonding interface layer 2 includes, but is not limited to, Si, SiC, AlN, SiN_x、Al₂O₃Diamond, or a W-containing high melting point compound, which may be one or more thereof; the above materials may have a single crystal structure, or may have a polycrystalline or amorphous structure.

In step S105, referring to step S105 in fig. 1 and fig. 6 and 7, the SiC peeling layer 42 is peeled off, and the SiC transfer layer 43 attached to the bonding interface layer 2 is formed in the remaining portion, and the thickness of the SiC transfer layer 43 is in the range of 0.2 μm to 5 μm. It can be seen that the thickness of the SiC transfer layer 43 in this embodiment is smaller than that of the substrate layer 1, which can effectively save SiC material; the SiC exfoliation layer 42 having a certain thickness that has been exfoliated can also be recycled, for example, the next fabrication of the semiconductor composite substrate can be performed, and SiC materials can also be effectively saved.

By way of example, the material of SiC transfer layer 43 includes, but is not limited to, 3C-SiC, 4H-SiC, or 6H-SiC.

For example, the annealing temperature is in the range of 800 ℃ to 1300 ℃, the annealing can be performed in air or in an inert gas atmosphere such as nitrogen or argon, the chamber pressure during the annealing is normal pressure, and the annealing time is in the range of 30min to 24 h.

In a third aspect, the present application further provides a semiconductor device, where the semiconductor device includes the semiconductor composite substrate according to any one of the embodiments of the first aspect, and an epitaxial buffer layer 5 and an epitaxial layer 6 sequentially located on the semiconductor composite substrate, and referring to fig. 8, the semiconductor composite substrate includes: the SiC wafer lift-off device comprises a base layer 1, a bonding interface layer 2 and a SiC transfer layer 43, wherein the bonding interface layer 2 is positioned between the base layer 1 and the SiC transfer layer 43, and the SiC transfer layer 43 is obtained by peeling and transferring the SiC wafer 3.

In a specific embodiment, the material of the epitaxial buffer layer 5 comprises one or more of AlN, AlGaN, GaN and SiC, the thickness of the epitaxial buffer layer 5 ranges from 10nm to 3 μm, and the growth method of the epitaxial buffer layer 5 includes, but is not limited to, metal organic chemical vapor deposition, molecular beam epitaxy or liquid phase epitaxy.

Furthermore, the material of the epitaxial layer 6 includes GaN and Ga₂O₃And Si, the thickness of the epitaxial layer 6 ranges from 200nm to 10 μm, and the growth method of the epitaxial layer 6 comprises but is not limited to metal organic chemical vapor deposition, molecular beam epitaxy or liquid phase epitaxy.

As for the manufacturing method of the semiconductor device, referring to fig. 9, the method specifically includes the following steps:

s201, obtaining a substrate layer 1 and a SiC wafer 3, and performing surface cleaning and chemical mechanical polishing on the substrate layer 1 and the SiC wafer 3, wherein surface planarization means used for the substrate layer 1 and the SiC wafer 3 are not limited to the means of surface cleaning, chemical mechanical polishing and the like, so that the root-mean-square roughness RMS of the surfaces of the substrate layer 1 and the SiC wafer 3 is less than 5 nm.

S202, growing a bonding interface layer 2 on the base layer 1, and planarizing the surface of the bonding interface layer 2. A bonding interface layer 2 is grown on the planarized surface (i.e., upper surface) of the base layer 1 by a thin film growth process such as Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), Atomic Layer Deposition (ALD), etc., and the bonding interface layer 2 is surface-planarized using surface cleaning and chemical mechanical polishing, etc. Such that the root mean square roughness RMS of the surface of the bonding interface layer 2 is <5 nm. It should be noted that the thin film growth process used for growing the bonding interface layer 2 is not limited to the above-mentioned Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), Atomic Layer Deposition (ALD), etc., and the surface planarization means used for the bonding interface layer 2 is also not limited to the above-mentioned surface cleaning and chemical mechanical polishing, etc.

And S203, implanting ions 41 into the SiC wafer 3 at a certain depth to form an ionized SiC wafer 4, wherein the implantation depth of the ions 41 is smaller than the thickness of the SiC wafer 3.

And S204, bonding the substrate layer 1 and the ionized SiC wafer 4 to form a bonded body, wherein the specific bonding process is not particularly limited in this embodiment and can be implemented according to the existing bonding technology.

S205, carrying out high-temperature annealing on the bonding body, wherein the ionized SiC wafer 4 is at the depth (namely the projection distance R) corresponding to the maximum concentration of ions 41 after annealing_pWhere) is split into two parts in a direction parallel to the surface of the ionized SiC wafer 4, and a part of the ionized SiC wafer 4 remote from the bonding interface layer 2 (SiC exfoliation layer 42 in fig. 4 and 5) is exfoliated, and a part of the ionized SiC wafer 4 near the bonding interface layer 2 is a SiC transfer layer 43, resulting in a semiconductor composite substrate.

S206, growing an epitaxial buffer layer 5 on the upper surface of the semiconductor composite substrate, and growing the epitaxial buffer layer 5 by using a metal organic chemical vapor deposition process or a molecular beam epitaxy process or other thin film growth processes, wherein the material of the epitaxial buffer layer comprises but is not limited to one or more of AlN, AlGaN, GaN and SiN materials, and the thickness range is 10nm-3 μm. If the material of the epitaxial buffer layer 5 includes AlGaN, the molar composition of the Al element is in the range of 0.05 to 0.3.

S207, growing an epitaxial layer 6 on the outer delayed buffer layer 5, wherein a metal organic chemical vapor deposition process or a molecular beam epitaxy process or other processes can be used, and the material of the epitaxial layer 6 includes but is not limited to GaN, Ga₂O₃Si, etc., in a thickness range of 200nm-10 μm, the layer being undoped.

The embodiment provided by the invention aims at the problem of high manufacturing cost of the existing high-thermal conductivity substrate, and provides a composite semiconductor substrate prepared based on a bonding, stripping and transferring technology, wherein a base layer is bonded with a SiC wafer, and a thin SiC transferring layer with a certain thickness is stripped from the SiC wafer by the stripping and transferring technology, so that the manufacturing cost of the substrate is reduced, and the rest SiC wafer raw material can be used for preparing the next composite substrate or other processes, can be recycled, and saves materials; and the preparation process flow of the composite semiconductor substrate is simple, and the production efficiency is high.

In addition, when the base layer is made of Si, the low cost of the Si can effectively reduce the cost of the substrate material on the basis of keeping the advantages of high thermal conductivity, high breakdown field strength and the like of SiC; when polycrystalline AlN is used as the base layer, AlN with excellent thermal conductivity, thermal stability, high resistance, and other characteristics provides transistors fabricated using the substrate structure with superior high power performance and better thermal management.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.