阅读说明：本技术 具有局域底栅的晶体管及其制作方法 (Transistor with local bottom gate and manufacturing method thereof ) 是由 许海涛 高宁飞 于 2021-07-14 设计创作，主要内容包括：本发明涉及一种局域底栅的晶体管及其制作方法,该晶体管包括衬底、低维半导体层、源极、漏极和局部底栅,局部底栅位于上述衬底上,局部底栅上具有一栅介质层,低维半导体层位于上述栅介质层上作为晶体管器件的沟道,源极和漏极位于低维半导体沟道的相对两侧,并分别与上述低维半导体层一个或多个部分接触；在上述源极、上述漏极以及所述沟道层上具有一过渡层和一静电掺杂层,该静电掺杂层中具有固定电荷,从而对其对应的低维半导体沟道层进行静电掺杂从而形成NMOS器件,同时还提出了上述晶体管的制作方法。本发明的晶体管具有热稳定性好、阈值电压精确可控,同时工艺具有兼容性,能够满足大规模碳基集成电路生产的要求。(The invention relates to a transistor of a local bottom gate and a manufacturing method thereof, wherein the transistor comprises a substrate, a low-dimensional semiconductor layer, a source electrode, a drain electrode and a local bottom gate, the local bottom gate is positioned on the substrate, a gate dielectric layer is arranged on the local bottom gate, the low-dimensional semiconductor layer is positioned on the gate dielectric layer and used as a channel of a transistor device, and the source electrode and the drain electrode are positioned on two opposite sides of the low-dimensional semiconductor channel and are respectively contacted with one or more parts of the low-dimensional semiconductor layer; the source electrode, the drain electrode and the channel layer are provided with a transition layer and an electrostatic doping layer, and the electrostatic doping layer is provided with fixed charges, so that the corresponding low-dimensional semiconductor channel layer is subjected to electrostatic doping to form an NMOS device. The transistor has the advantages of good thermal stability, accurate and controllable threshold voltage, compatible process and capability of meeting the requirement of large-scale carbon-based integrated circuit production.)

1. A transistor comprising a substrate (101), a local bottom gate (102), a gate dielectric layer (103), a low dimensional semiconductor layer (104), a source and a drain, characterized in that:

the local bottom gate (102) is embedded in the substrate (101) and is in the same plane with the substrate or is positioned on the substrate (101);

a gate dielectric layer (103) is arranged on the local bottom gate (102), and the low-dimensional semiconductor layer (104) is positioned on the gate dielectric layer (103) and is used as a channel of the transistor device;

the source electrode and the drain electrode are positioned on two opposite sides of the channel and respectively form one or more partial contacts with the low-dimensional semiconductor layer (104);

the channel has a transition layer (107) and an electrostatically doped layer (108) thereon, and fixed charges are formed in the electrostatically doped layer (108).

2. The transistor of claim 1, wherein the substrate (101) comprises SiO₂a/Si substrate, a quartz substrate, Al₂O₃At least one of a substrate, a glass substrate, or a polymer substrate.

3. Transistor according to claim 1, characterized in that the low dimensional semiconductor layer (104) is selected from the group consisting of carbon nanotubes, silicon nanowires and nanowires of elements of groups II-VI, nanowires of elements of groups III-V and two dimensional layered semiconductor materials, the carbon nanotubes further preferably being single walled carbon nanotubes, multi walled carbon nanotubes, network-like carbon nanotubes or carbon nanotube arrays, the two dimensional layered semiconductor materials further preferably being black phosphorus or molybdenum disulfide.

4. The transistor of claim 1, wherein the local bottom gate (102) comprises at least one of tantalum nitride (TaN), titanium nitride (TiN), polysilicon, gold (Au), palladium (Pd), platinum (Pt), a titanium/gold stack (Ti/Au), a titanium/palladium stack (Ti/Pd), or a titanium/platinum stack (Ti/Pt).

5. The transistor of claim 1, wherein the source and drain electrodes comprise at least one of platinum (Pt), titanium (Ti), or palladium (Pd), and preferably palladium (Pd).

6. The transistor according to claim 1, wherein a first gate dielectric sub-layer (103 ') is provided between the local bottom gate (102) and the gate dielectric layer (103), and a second gate dielectric sub-layer (103 ') is provided between the gate dielectric layer (103) and the electrostatically doped layer (108) or the transition layer (107), wherein the first gate dielectric sub-layer (103 ') and the second gate dielectric sub-layer (103 ") are of the same or different materials.

7. The transistor of claim 6, wherein the first gate dielectric sublayer (103') and the second gate dielectric sublayer (103 ") comprise aluminum oxide (Al)₂O₃) Aluminum nitride (AlN), hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Hafnium oxynitride (HfO)_xN_y) Lanthanum oxynitride (LaO)_xN_y) Yttrium oxide (Y)₂O₃) Or lanthanum oxide (La)₂O₃) At least one of (1).

8. The transistor according to claim 1, characterized in that the electrostatically doped layer (108) is a metal oxide or nitride, preferably at least one of aluminum oxide, hafnium oxide or aluminum nitride, and further preferably aluminum nitride.

9. The transistor of claim 1, characterized in that a protective layer (109) is provided on said electrostatically doped layer (108).

10. A transistor according to claim 1, characterized in that there is a transition layer (107) between the electrostatically doped layer (108) and the low dimensional semiconductor layer (104).

11. A method of manufacturing a transistor as claimed in any one of claims 1 to 10, comprising the steps of:

providing a substrate (101), and forming a local bottom gate (102) on the substrate (101);

forming a gate dielectric layer (103) on the local bottom gate (102);

forming a low-dimensional semiconductor layer (104) on the gate dielectric layer (103);

forming a source electrode and a drain electrode on two opposite sides of the low-dimensional semiconductor layer (104), and exposing a part of the low-dimensional semiconductor layer (104) to be used as a channel layer of the transistor;

a dielectric layer (107) and an electrostatic doping layer (108) are further formed on the channel layer, the electrostatic doping layer (108) having fixed charges therein.

12. Method for manufacturing a transistor according to claim 11, characterized in that the substrate (101) is selected from SiO₂a/Si substrate, a quartz substrate, Al₂O₃At least one of a substrate, a glass substrate or a polymer substrate, before forming the low dimensional material layer, further comprising an operation of pre-treating the surface of the substrate, wherein the pre-treatment comprises at least one of plasma treatment, annealing treatment, wet chemical cleaning and surface molecular modification.

13. The method of claim 11, wherein the low dimensional semiconductor layer is at least one selected from the group consisting of carbon nanotubes, silicon nanowires, group II-VI element nanowires, group III-V element nanowires, and two dimensional layered semiconductor material, the carbon nanotubes are preferably single-walled carbon nanotubes, multi-walled carbon nanotubes, network-like carbon nanotubes, or carbon nanotube arrays, and the two dimensional layered semiconductor material is preferably black phosphorus or molybdenum disulfide.

14. The method of claim 11, wherein the local bottom gate is selected from at least one of tantalum nitride (TaN), titanium nitride (TiN), polysilicon, gold (Au), palladium (Pd), platinum (Pt), titanium/gold stack (Ti/Au), titanium/palladium stack (Ti/Pd), or titanium/platinum stack (Ti/Pt).

15. The method of claim 11, wherein the source and drain electrodes are selected from at least one of platinum (Pt), titanium (Ti), or palladium (Pd), and preferably palladium (Pd).

16. The method of claim 11, wherein a first gate dielectric sublayer (103') is formed after the formation of the local bottom gate (102), wherein the gate dielectric layer (103) is formed on the first gate dielectric sublayer, and further wherein a second gate dielectric sublayer (103 ") is formed on the gate dielectric layer (103), wherein the first gate dielectric sublayer and the second gate dielectric sublayer are made of the same or different materials.

17. The method of claim 16 wherein the first and second gate dielectric sublayers comprise aluminum oxide (Al)₂O₃) Aluminum nitride (AlN), hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Hafnium oxynitride (HfO)_xN_y) Lanthanum oxynitride (LaO)_xN_y) Yttrium oxide (Y)₂O₃) Or lanthanum oxide (La)₂O₃) At least one of them, and further preferably yttria.

18. The transistor of claim 11, wherein the electrostatically doped layer (108) comprises a metal oxide or nitride, preferably at least one of aluminum oxide, hafnium oxide, silicon nitride or aluminum nitride, and further preferably aluminum nitride.

19. The transistor of claim 11, further comprising a protective layer (109) formed on said electrostatically doped layer (108), said protective layer (109) comprising at least one of aluminum oxide or silicon nitride.

20. A transistor according to claim 11, characterized in that a transition layer (107) is provided between the electrostatically doped layer (108) and the low dimensional semiconductor layer (104), the transition layer (107) being deposited in a non-plasma manner, preferably by thermal atomic layer deposition or physical vapour deposition, the transition layer (107) comprising at least one of aluminum oxide, yttrium oxide or hafnium oxide, and preferably yttrium oxide.

21. A method for manufacturing a complementary field effect transistor is characterized by comprising the following steps:

providing a substrate (101), and forming a first local bottom gate and a second local bottom gate on the substrate (101) to be used as corresponding gates of a PMOS and an NMOS respectively;

forming a gate dielectric layer (103) on the first local bottom gate and the second local bottom gate;

forming a low-dimensional semiconductor layer (104) on the gate dielectric layer (103);

forming a source electrode and a drain electrode on two opposite sides of the low-dimensional semiconductor layer (104) corresponding to the first local bottom gate and the second local bottom gate respectively, and exposing part of the low-dimensional semiconductor layer (104) to be used as channel layers of the PMOS and the NMOS respectively;

further depositing a dielectric layer (107) and an electrostatic doping layer (108) on the structure formed in the step, wherein the electrostatic doping layer (108) has fixed charges;

further forming a first protective layer on the structure, filling the dielectric in the groove between the source electrode and the drain electrode, and further flattening;

defining a window pattern of a semiconductor channel layer corresponding to the first local bottom gate on the dielectric surface formed after the planarization, and carrying out dry etching on the first protective layer and the electrostatic doping layer by taking the transition layer as an etching stop layer;

and further depositing a second protective layer in the groove formed after the etching, thereby forming a PMOS corresponding to the first local bottom gate and an NMOS corresponding to the second local bottom gate, and finally further forming the nano complementary field effect transistor through an interconnection process.

22. The transistor of claim 21, wherein a first gate dielectric sublayer is formed after the first local under-gate and the second local under-gate are formed, wherein the gate dielectric layer is formed on the first gate dielectric sublayer, and further wherein a second gate dielectric sublayer is formed on the gate dielectric layer, wherein the first gate dielectric sublayer and the second gate dielectric sublayer are made of the same or different materials.

23. The method of claim 22 wherein the first gate dielectric sublayer and the second gate dielectric sublayer comprise aluminum oxide(Al₂O₃) Aluminum nitride (AlN), hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Hafnium oxynitride (HfO)_xN_y) Lanthanum oxynitride (LaO)_xN_y) Yttrium oxide (Y)₂O₃) Or lanthanum oxide (La)₂O₃) At least one of them, and further preferably yttria.

24. The transistor of claim 21, wherein the electrostatically doped layer is a metal oxide or nitride, preferably at least one of aluminum oxide, hafnium oxide, or aluminum nitride, and further preferably aluminum nitride.

25. The transistor as claimed in claim 21, wherein when the electrostatic doping layer is aluminum nitride, the NMOS threshold voltage is controlled by adjusting a process temperature of aluminum nitride atomic layer deposition, wherein the process temperature is 200-400 ℃, preferably 220-300 ℃.

26. The transistor of claim 21, wherein the first protective layer is preferably alumina or silicon nitride and the second protective layer is preferably yttria.

Technical Field

The invention relates to the field of semiconductor devices, in particular to a transistor with a local bottom gate and a preparation method thereof.

Background

Low dimensional semiconductor materials, such as carbon nanotubes, graphene, black phosphorus, or two dimensional materials, have been widely used as channel materials in transistors due to their excellent properties such as thin thickness, high mobility, high physical and chemical stability, and high thermal conductivity. Similarly to the conventional semiconductor process, a transistor with a channel made of a low dimensional material can change the distribution of carriers in the semiconductor channel material by doping the low dimensional material, thereby changing the electrical properties of the transistor, and a p-type region and an n-type region are formed respectively, so as to form semiconductor devices with various structural functions, such as a diode and a field effect transistor. However, the forbidden bandwidth of the low-dimensional semiconductor is generally smaller than that of silicon, wherein the typical band gap of the carbon nanotube is about 0.5eV, which corresponds to the band gap of silicon being about 1.12 eV. Because the band gap is narrow, the width of the tunneling barrier between the drain end bands under the off state is greatly compressed, larger tunneling current is generated, and the static energy consumption is influenced. The off-state tunneling effect of the corresponding transistor is more remarkable than that of a silicon-based transistor, and in the existing undoped MOS structure, the Schottky barrier existing near a channel bias drain terminal is too thin due to the over-concentrated and over-strong electric field of the drain terminal, so that the Schottky tunneling is serious.

Due to the particularity of the low-dimensional semiconductor material, doping the channel material by conventional thermal diffusion and ion implantation methods easily causes various problems. For example, the low dimensional material is more susceptible to the environment, so that it is difficult to form uniform and reliable doping by thermal diffusion or ion implantation, and damage to the low dimensional material is easily caused during the doping process. Meanwhile, the channel of the low-dimensional material is extremely thin and is generally a single atomic layer or a plurality of atomic layers, effective doping in the channel is difficult to realize by the traditional impurity ion doping method, and the impurity ions are more likely to be distributed in the insulating substrate. And partial low-dimensional materials, such as carbon nanotubes and graphene, have stable chemical properties, strong chemical bond energy between atoms and no dangling bond on the surface, and doped impurity ions are difficult to form a stable structure by bonding with carbon atoms and tend to exist in an unstable weak interaction mode (such as surface adsorption), so that the doping effect is unstable. In addition, the conventional doping method usually requires annealing at a high temperature of over 1000 ℃ to repair the lattice damage caused by the doping process. Most low-dimensional materials cannot bear the temperature, and the compatibility of the device preparation process is limited by the high-temperature annealing process. Therefore, the low-dimensional semiconductor material transistor cannot realize the light doped source drain (LDD) of the silicon-based transistor to finely regulate the distribution of the doping concentration of the drain end in the space, thereby reducing the negative effects of short channel effect, junction leakage current, parasitic current and the like. However, due to the characteristics of ultra-thin channels and limited carrier concentration (compared with bulk semiconductor material), the low dimensional semiconductor material is easier to realize electrostatic regulation than bulk semiconductor material, and the contact characteristics of the low dimensional semiconductor material and metal semiconductor are different from those of the conventional semiconductor, for example, no significant fermi pinning effect is observed when the carbon nanotubes are contacted with some metals.

At present, a PMOS or NMOS can be realized by selecting a metal material matched with the work function of a channel material as a source electrode and a drain electrode to replace the doping of the channel material, or a bottom gate device structure is adopted, and the problem is solved by depositing a material layer with fixed charges on the surface of a channel and performing electrostatic doping on the channel. The method comprises the steps of selecting a metal material matched with the work function of a channel material to form a source electrode and a drain electrode, effectively injecting electrons (NMOS) or holes (PMOS) in an on state, controlling the on and off of a transistor by regulating and controlling the energy band bending in the channel through a grid electrode, performing electrostatic doping on the channel through depositing a material layer with fixed charges on the surface of the channel, performing electrostatic doping on the whole channel, further adjusting the energy band bending between the source electrode and the drain electrode and realizing barrier-free injection or tunneling injection of carriers. However, the transistors made of the low-dimensional materials prepared by the two methods still have more problems, for example, the carbon nanotube transistor is taken as an example, the high-k dielectric transistor made of the source and drain electrodes made of the metal material with matched metal work function has the problems that the threshold voltage cannot be effectively regulated and controlled, reverse tunneling is easily generated at the drain end in the off state, the on-off ratio is reduced and the like. The transistor is prepared by combining local bottom gate with channel surface electrostatic doping or using a top gate structure by using gate dielectric oxide electrostatic doping, and at present, electrostatic doping is usually realized by using metal oxides with incomplete proportion (namely, more oxygen vacancies or dangling bonds exist), so that the interface is unstable, a plurality of defect states and interface states exist, the channel mobility is reduced, gate control is not facilitated, the uniformity of a device is influenced, and the process repeatability is poor.

Therefore, effective doping technology based on low-dimensional semiconductor materials is required to be developed, so that the critical indexes of the transistor based on the low-dimensional materials can simultaneously meet the requirements, such as on-state and off-state currents, threshold voltage, gate control capability, device reliability, thermal stability and the like, and meanwhile, the process has certain compatibility and can meet the requirements of large-scale carbon-based integrated circuit production.

Disclosure of Invention

In view of the above problems in the prior art, the present invention provides a transistor with local bottom gate and a method for manufacturing the same by using a dielectric material capable of directly forming fixed charges therein as an electrostatic doping layer, and the technical solution of the embodiment of the first aspect of the present invention is as follows:

a transistor comprises a substrate, a local bottom gate, a gate dielectric layer, a low-dimensional semiconductor layer, a source electrode and a drain electrode, and the scheme is as follows: the local bottom gate is embedded in the substrate and is positioned on the same plane with the substrate or positioned on the substrate;

a gate dielectric layer is arranged on the local bottom gate, and the low-dimensional semiconductor layer is positioned on the gate dielectric layer and is used as a channel of the transistor device;

the source electrode and the drain electrode are positioned at two opposite sides of the channel and are respectively in contact with one or more parts of the low-dimensional semiconductor layer;

the channel has a transition layer and an electrostatic doped layer on the channel, and fixed charges are formed in the electrostatic doped layer.

In an embodiment of the first aspect of the invention, the substrate comprises SiO₂a/Si substrate, a quartz substrate, Al₂O₃At least one of a substrate, a glass substrate, or a polymer substrate.

In an embodiment of the first aspect of the present invention, the low dimensional semiconductor layer includes at least one of a carbon nanotube, a silicon nanowire, and a group II-VI element nanowire, a group III-V element nanowire, or a two dimensional layered semiconductor material, the carbon nanotube is preferably a single-walled carbon nanotube, a multi-walled carbon nanotube, a network-like carbon nanotube, or a carbon nanotube array, and the two dimensional layered semiconductor material is preferably black phosphorus or molybdenum disulfide.

In an embodiment of the first aspect of the present invention, the local bottom gate is selected from at least one of tantalum nitride (TaN), titanium nitride (TiN), polysilicon, gold (Au), palladium (Pd), platinum (Pt), a titanium/gold stack (Ti/Au), a titanium/palladium stack (Ti/Pd), or a titanium/platinum stack (Ti/Pt).

In an embodiment of the first aspect of the present invention, the source electrode and the drain electrode are selected from at least one of platinum (Pt), titanium (Ti), or palladium (Pd), and preferably palladium (Pd).

In an embodiment of the first aspect of the present invention, a first gate dielectric sublayer is provided between the local bottom gate and the gate dielectric layer, and a second gate dielectric sublayer is provided between the gate dielectric layer and the low dimensional semiconductor layer, where the first gate dielectric sublayer and the second gate dielectric sublayer are the same or different in material. The first gate dielectric sublayer, the gate dielectric layer and the second gate dielectric sublayer collectively function as a gate dielectric.

Further, the first gate dielectric sublayer and the second gate dielectric sublayer comprise aluminum oxide (Al)₂O₃) Aluminum nitride (AlN), hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Hafnium oxynitride (HfO)_xN_y) Lanthanum oxynitride (LaO)_xN_y) Yttrium oxide (Y)₂O₃) Or lanthanum oxide (La)₂O₃) At least one of them.

In an embodiment of the first aspect of the present invention, the electrostatic doping layer is a metal oxide or nitride, preferably aluminum oxide, hafnium oxide, aluminum nitride, and more preferably aluminum nitride.

In an embodiment of the first aspect of the present invention, a protection layer is disposed on the electrostatic doping layer.

In an embodiment of the first aspect of the present invention, a transition layer is disposed between the electrostatically doped layer and the low dimensional semiconductor layer.

In an embodiment of the first aspect of the present invention, a method for manufacturing the transistor is provided, which specifically includes the following steps:

s1, providing a substrate, forming a partial bottom gate on the substrate;

s2, forming a gate dielectric layer on the local bottom gate;

s3, forming a low-dimensional semiconductor layer on the gate dielectric layer;

s4, forming a source and a drain on two opposite sides of the low dimensional semiconductor layer and exposing a part of the low dimensional semiconductor layer as the channel layer of the transistor;

and S5, forming a transition layer and an electrostatic doping layer on the channel layer, wherein the electrostatic doping layer has fixed charges.

In an embodiment of the second aspect of the invention, the substrate is selected from SiO₂Si substrate, quartz substrate, Al₂O₃The substrate, the glass substrate or the polymer substrate further comprises an operation of performing pretreatment on the surface of the substrate before the low-dimensional material layer is formed, wherein the pretreatment comprises at least one of plasma treatment, annealing treatment, wet chemical cleaning and surface molecular modification.

In an embodiment of the second aspect of the present invention, the low dimensional semiconductor layer includes at least one of a carbon nanotube, a silicon nanowire, a group II-VI element nanowire, a group III-V element nanowire, or a two dimensional layered semiconductor material, the carbon nanotube is preferably a single-walled carbon nanotube, a multi-walled carbon nanotube, a network-like carbon nanotube, or a carbon nanotube array, and the two dimensional layered semiconductor material is preferably black phosphorus or molybdenum disulfide.

In an embodiment of the second aspect of the present invention, the local bottom gate comprises at least one of tantalum nitride (TaN), titanium nitride (TiN), polysilicon, gold (Au), palladium (Pd), platinum (Pt), titanium/gold stack (Ti/Au), titanium/palladium stack (Ti/Pd), or titanium/platinum stack (Ti/Pt).

In an embodiment of the second aspect of the present invention, the source electrode and the drain electrode include at least one of platinum (Pt), titanium (Ti), or palladium (Pd), and preferably palladium (Pd).

In an embodiment of the second aspect of the present invention, after the local area bottom gate is formed, a first gate dielectric sub-layer is formed, the gate dielectric layer is formed on the first gate dielectric sub-layer, and a second gate dielectric sub-layer is further formed on the gate dielectric layer, where the first gate dielectric sub-layer and the second gate dielectric sub-layer are made of the same material or different materials.

In an embodiment of the second aspect of the present invention, the first gate dielectric sublayer and the second gate dielectric sublayer comprise aluminum oxide (Al)₂O₃) Aluminum nitride (AlN), hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Hafnium oxynitride (HfO)_xN_y) Lanthanum oxynitride (LaO)_xN_y) Yttrium oxide (Y)₂O₃) Or lanthanum oxide (La)₂O₃) And further preferably yttria.

In an embodiment of the second aspect of the present invention, the electrostatic doping layer is a metal oxide or nitride, and includes at least one of aluminum oxide, hafnium oxide, or aluminum nitride, and is further preferably aluminum nitride.

In an embodiment of the second aspect of the present invention, a transition layer is disposed between the electrostatically doped layer and the low dimensional semiconductor layer.

In an embodiment of the second aspect of the present invention, a protective layer is further formed on the electrostatic doping layer, and the protective layer may be selected from aluminum oxide or silicon nitride.

In an embodiment of the second aspect of the present invention, a transition layer is disposed between the electrostatically doped layer and the low dimensional semiconductor layer, the transition layer is deposited by a non-plasma method, such as thermal atomic layer deposition or physical vapor deposition, and the transition layer comprises at least one of aluminum oxide, yttrium oxide or hafnium oxide, and is preferably yttrium oxide.

The embodiment of the third aspect of the present invention further provides a method for manufacturing a complementary field effect transistor, which specifically includes the following steps:

s1, providing a substrate, forming a first local bottom gate and a second local bottom gate on the substrate, and using the first local bottom gate and the second local bottom gate as corresponding gates of a PMOS and an NMOS respectively;

s2, forming a gate dielectric layer on the first and the second local bottom gates;

s3, forming a low-dimensional semiconductor layer on the gate dielectric layer;

s4, forming a source and a drain on two opposite sides of the low dimensional semiconductor layer corresponding to the first local bottom gate and the second local bottom gate, respectively, and exposing part of the low dimensional semiconductor layer to be used as the channel layer of the PMOS and the NMOS respectively;

s5, further depositing a transition layer and an electrostatic doping layer on the structure formed in the step, wherein the electrostatic doping layer has fixed charges;

s6, forming a first protection layer on the structure, filling the groove between the source and the drain with the dielectric, and further flattening;

s7, defining a window pattern of the semiconductor channel layer corresponding to the first local bottom gate on the dielectric surface formed after the planarization, and carrying out dry etching on the first protective layer and the electrostatic doping layer by taking the transition layer as an etching stop layer;

and S8, depositing a second protective layer in the groove formed after etching to form a PMOS corresponding to the first local bottom gate and an NMOS corresponding to the second local bottom gate, and further forming the nanometer complementary field effect transistor through an interconnection process.

In an embodiment of the third aspect of the present invention, after the first local bottom gate and the second local bottom gate are formed, a first gate dielectric sub-layer is formed, the gate dielectric layer is formed on the first gate dielectric sub-layer, and a second gate dielectric sub-layer is further formed on the gate dielectric layer, where the first gate dielectric sub-layer and the second gate dielectric sub-layer are made of the same material or different materials.

In an embodiment of the third aspect of the present invention, the first gate dielectric sublayer and the second gate dielectric sublayer comprise aluminum oxide (Al)₂O₃) Aluminum nitride (AlN), hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Hafnium oxynitride (HfO)_xN_y) Lanthanum oxynitride (LaO)_xN_y) Yttrium oxide (Y)₂O₃) Or lanthanum oxide (La)₂O₃) And further preferably yttria.

In an embodiment of the third aspect of the present invention, the electrostatic doping layer is a metal oxide or nitride, preferably at least one of aluminum oxide, hafnium oxide, or aluminum nitride, and more preferably aluminum nitride.

In the embodiment of the third aspect of the invention, when the electrostatic doping layer is aluminum nitride, the NMOS threshold voltage is regulated and controlled by adjusting the process temperature of aluminum nitride atomic layer deposition, wherein the process temperature is 200-.

In an embodiment of the third aspect of the present invention, the first protective layer is preferably alumina or silicon nitride, and the second protective layer is preferably yttria.

The embodiment of the invention has the following beneficial effects:

the invention adopts a material capable of directly forming fixed charges as an electrostatic doping layer, and simultaneously adopts a high-k dielectric layer as a transition layer between the electrostatic doping layer and a channel layer, so that the device has better thermal stability, and when the transition layer (107) and a second gate dielectric sublayer (103') in a gate dielectric are made of the same material, such as yttrium oxide, the device has better interface characteristics.

Drawings

FIG. 1 is a schematic view of one embodiment of a non-gate dielectric transition layer transistor according to the present invention;

FIG. 2 is a schematic diagram of one embodiment of a transistor with a symmetric gate dielectric transition layer according to the present invention;

FIG. 3 is a schematic diagram of one embodiment of a transistor having a raised local bottom gate of the present invention;

FIG. 4 is a schematic diagram of forming an embedded local area bottom gate in one embodiment of the present invention;

FIG. 5 is a schematic view of forming a gate dielectric layer according to an embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating the formation of a low dimensional semiconductor material layer and source and drain electrodes in one embodiment of the present invention;

FIG. 7 is a schematic illustration of the formation of a dielectric layer in an embodiment of the invention;

FIG. 8 is a schematic view of forming an electrostatically doped layer in an embodiment in accordance with the present invention;

FIG. 9 is a schematic view of forming a first protective layer in one embodiment of the present invention;

FIG. 10 is a schematic view of forming a mask pattern in accordance with an embodiment of the present invention;

FIG. 11 is a schematic diagram illustrating etching of a first protective layer according to an embodiment of the invention;

FIG. 12 is a schematic diagram illustrating etching of an electrostatically doped layer in an embodiment of the present invention;

FIG. 13 is a schematic view of depositing a second protective layer in one embodiment of the present invention;

FIG. 14 is a CV characterization of a transistor in one embodiment of the invention;

FIG. 15 shows a dielectric layer of HfO according to the present invention₂The I-V characterization of the transistors in the embodiments of (1);

FIG. 16 shows a dielectric layer Y according to the present invention₂O_3/HfO₂The I-V characterization of the transistors in the embodiments of (1);

FIG. 17 shows a dielectric layer Y according to the present invention₂O₃/HfO₂/Y₂O₃The I-V characterization of the transistors in the embodiments of (1);

FIG. 18 shows an electrostatically doped layer of Y in accordance with the present invention₂O₃I-V characterization of transistors in embodiments of the/AlN stacks;

fig. 19 is a characterization of transistors I-V formed at different ALD growth temperatures of AlN.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Like elements in the drawings are represented by like reference numerals, and parts of the drawings are not drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.

The structure of the local bottom-gate transistor of this embodiment is shown in fig. 1, and the transistor includes a substrate 101 in which a local bottom-gate 102 is embedded. In this embodiment, the substrate 101 is a silicon oxide substrate, and in other embodiments, the substrate 101 may also be made of a hard insulating material such as quartz, glass, or alumina, or a high-temperature-resistant flexible insulating material selected from PET (polyethylene terephthalate), PEN (polyethylene naphthalate), and polyimide. In this embodiment, the local bottom gate is made of a titanium/gold (Ti/Au) stack material, and in other embodiments, the local bottom gate may be selected from one or more alloys of titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), aluminum (A l), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), platinum (Pt), scandium (Sc), yttrium (Y), or erbium (Er).

A gate dielectric layer 103 is provided on the substrate having the local bottom gate 102, and in this embodiment, the gate dielectric layer 103 is hafnium oxide (HfO)₂) In other embodiments, the gate dielectric layer 103 may be made of aluminum oxide (Al)₂O₃) Aluminum nitride (Al N), zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Hafnium oxynitride (HfO)_xN_y) Lanthanum oxynitride (LaO)_xN_y) Yttrium oxide (Y)₂O₃) Or lanthanum oxide (La)₂O₃) High k dielectrics.

Further, a low dimensional semiconductor material layer 104 is disposed on the gate dielectric layer 103, in this embodiment, the low dimensional semiconductor material is a single-walled carbon nanotube material, and in other embodiments, the low dimensional semiconductor material may be a multi-walled carbon nanotube, a network-like carbon nanotube, or a carbon nanotube array. In addition, other low-dimensional semiconductor materials such as silicon nanowires, II-VI element nanowires, III-V element nanowires, two-dimensional layered semiconductor materials and the like can also be adopted, wherein the two-dimensional layered semiconductor materials can be molybdenum disulfide, tungsten disulfide or black phosphorus.

In other embodiments, as shown in fig. 2, there may be a first gate dielectric sub-layer 103 'between the gate dielectric 103 and the local bottom gate 102, and a second gate dielectric sub-layer 103 "between the gate dielectric 103 and the low dimensional semiconductor material layer 104, where the first gate dielectric sub-layer 103' or the second gate dielectric sub-layer 103" may be configured to improve the quality of the interface between the local bottom gate 102 and the gate dielectric 103 and between the gate dielectric 103 and the low dimensional semiconductor material layer 104. The first gate dielectric sub-layer 103 '/gate dielectric 103/second gate dielectric sub-layer 103' is adopted as the gate dielectric, and compared with the single use of the gate dielectric 103 as the gate dielectric, the use of the laminated gate dielectric layer has higher quality and smaller hysteresis, and is also beneficial to improving the on-off ratio of the device under the working condition. The first gate dielectric sub-layer 103' and the second gate dielectric sub-layer 103 ″ may be the same or different in material and may include aluminum oxide (Al)₂O₃) Aluminum nitride (AlN), hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Hafnium oxynitride (HfO)_xN_y) Lanthanum oxynitride (LaO)_xN_y) Yttrium oxide (Y)₂O₃) Or lanthanum oxide (La)₂O₃) At least one of which, in the embodiment shown in fig. 2, both are yttria (Y)₂O₃) A dielectric layer formed by symmetrically disposing two yttrium oxide (Y) layers on both sides of the gate dielectric 103₂O₃) The dielectric layer can reduce the influence of electrostatic doping on a gate dielectric interface, and can realize more accurate control on threshold voltage.

Further, a source 105 and a drain 106 are formed on opposite sides of the low dimensional semiconductor material layer 104, the source 105 and the drain 106 defining a channel region of the transistor therebetween, and a transition layer 107 and an electrostatically doped layer 108, in this embodiment formed of a selected yttrium oxide (Y)₂O₃) As the transition layer, on one hand, the transition layer 107 and the low-dimensional semiconductor layer 104 have better interface quality, which is beneficial to improving the performance and reliability of the device, and on the other hand, the low-dimensional semiconductor channel layer can be prevented from being damaged when the electrostatic doping layer 108 is deposited, for example, the electrostatic doping layer is deposited by adopting a plasma process, and on the other hand, the low-dimensional semiconductor channel layer is prevented from being damaged in the subsequent processProcess for removing yttrium oxide (Y)₂O₃) The layer can also be used as an etch stop layer in an etching process when other dielectric layers are above. The electrostatic doping layer 108 has fixed charges therein, so as to dope the low-dimensional semiconductor channel layer, thereby realizing the regulation and control of the threshold voltage and the switching state. In the present embodiment, the electrostatically doped layer 108 is an aluminum nitride (AlN) material. In other embodiments, the electrostatically doped layer 108 may also be aluminum oxide, organic molecules, or silicon nitride. By adopting the electrostatic doping layer and the transition layer double-layer structure with the protection function, more stable electrostatic doping effect can be realized and the advantages in the preparation process are brought.

In another embodiment, as shown in fig. 3, a local bottom gate pattern is defined on the substrate 201 by a photolithography process, unlike the previous embodiment in which the local bottom gate is embedded in the substrate, the local bottom gate 202 is directly formed on the local bottom gate pattern of the substrate 201, then a transition layer 203 and a gate dielectric layer 204 are formed on the local bottom gate 202, and then a low-dimensional semiconductor material layer 205 is formed on the gate dielectric layer 204, and a source 206 and a drain 207 are respectively formed on two opposite sides thereof. And further a transition layer 208 and an electrostatically doped layer 209 are formed on the layer 205 of low-dimensional semiconductor material.

FIGS. 14-18 are comparative experimental results for examples of the present invention. Fig. 14 shows CV representations of different gate dielectrics of the present invention, and it can be seen that the gate dielectric has higher quality, smaller hysteresis, and better device uniformity by using yttria/hafnia/yttria as the gate dielectric. FIGS. 15-17 are representations of examples I-V of the present invention using different gate dielectrics, respectively, and from the above comparison, using Y₂O₃/HfO₂/Y₂O₃The dielectric combination of (2) has higher switching ratio and better consistency. FIG. 18 is an I-V characterization of an embodiment of the invention using different electrostatically doped layers. Therefore, the yttrium oxide and aluminum nitride laminated layer is used as the electrostatic doping layer, so that more effective electrostatic doping is achieved, the channel layer and the gate dielectric layer have better interface characteristics, and the device has higher on-off ratio, larger on-state current and better consistency. When the aluminum nitride adopts the plasma deposition processDuring growth, such as Plasma Enhanced Atomic Layer Deposition (PEALD) or radio frequency sputtering (RF-Sputter), the transition layer yttria also acts as a protective layer to prevent the carbon nanotubes from being damaged by the plasma process. Fig. 19 is an I-V characterization of transistors formed by ALD deposited AlN at different temperatures, which allows for the tuning of the threshold voltage by adjusting the growth temperature of AlN.

In another embodiment of the present invention, a method for fabricating a transistor with a local bottom gate is provided, and the method is described in detail below with reference to the accompanying drawings.

Step S1, as shown in fig. 4, a silicon oxide substrate 101 is provided, a local bottom gate 102 pattern is defined on the substrate 101 through a photolithography process, then the silicon oxide substrate is etched to form a groove according to the local bottom gate pattern, a titanium/gold (Ti/Au) metal stack is deposited in the groove to form a local bottom gate 102, and the surface of the local bottom gate 102 is in the same plane as the substrate 101. In other embodiments, the substrate may also be made of a hard insulating material such as quartz, glass, or alumina, or a high temperature resistant flexible insulating material selected from PET (polyethylene terephthalate), PEN (polyethylene naphthalate), and polyimide.

In another embodiment, after the local bottom gate pattern is defined on the silicon oxide substrate, the local bottom gate 102 may also be formed directly by Atomic Layer Deposition (ALD) or Physical Vapor Deposition (PVD), at this time, a step is formed between the local bottom gate and the substrate, and during subsequent growth of a gate dielectric layer, deposition is preferably performed by using an Atomic Layer Deposition (ALD) method, so as to enhance the step coverage.

Step S2, as shown in fig. 5, a layer of dielectric is deposited on the local bottom gate 102 to serve as the gate dielectric layer 103, which can be obtained by Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD), and the thickness of the gate dielectric layer 103 can be controlled to be 1-50nm, in this embodiment, 8 nm. The material of the gate dielectric layer may be selected from common high-k dielectric materials, such as from alumina (Al)₂O₃) Aluminum nitride (AlN), zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Hafnium oxide (HfO)₂) Hafnium oxynitride (HfO)_xN_y) Lanthanum oxynitride (LaO)_xN_y) Yttrium oxide (Y)₂O₃) Or lanthanum oxide (La)₂O₃) And the like.

In another embodiment, a first gate dielectric sub-layer is formed before forming the gate dielectric layer, and then a second gate dielectric sub-layer is formed after forming the gate dielectric layer, wherein the materials of the first gate dielectric sub-layer and the second gate dielectric sub-layer can be the same or different, and the first gate dielectric sub-layer can be used as a transition layer for depositing the gate dielectric layer, so that the growth quality of the gate dielectric layer is improved; the second gate dielectric sub-layer is used as the transition of the gate dielectric layer and the low-dimensional semiconductor layer, so that the deposition of the low-dimensional semiconductor layer is facilitated, and a better interface is formed with the transition layer above the low-dimensional semiconductor layer. Preferably, the first gate dielectric sublayer material and the second gate dielectric sublayer material can be made the same, so that symmetry is provided on both sides of the gate dielectric layer, which helps to reduce device hysteresis. By using the laminated combination of the first gate dielectric sublayer/the gate dielectric layer/the second gate dielectric sublayer as the gate dielectric of the device, more accurate control over the threshold voltage and higher on-off ratio can be realized. Specifically, the first gate dielectric sublayer may be yttria (Y)₂O₃) Forming a yttrium metal thin film on the local bottom gate by electron beam evaporation, then performing thermal oxidation to form an yttrium oxide transition layer, and further depositing hafnium oxide (HfO) on the yttrium oxide transition layer by Atomic Layer Deposition (ALD)₂) Forming a gate dielectric layer, and forming a second yttrium oxide (Y) by thermal oxidation₂O₃) And a transition layer.

S3, forming a low-dimensional semiconductor layer 104 on the gate dielectric, wherein the low-dimensional semiconductor layer is a single-walled carbon nanotube film in this embodiment, and can be obtained by inserting the substrate into a carbon nanotube solution for pulling, wherein the carbon nanotube solution is formed by dissolving the carbon nanotube in one or more halogenated hydrocarbons, and the halogenated hydrocarbons can be selected from organic solvents such as chloroform, dichloroethane, trichloroethane, chlorobenzene, dichlorobenzene, bromobenzene, and the like. In other embodiments, the low dimensional semiconducting material may be multi-walled carbon nanotubes, a network of carbon nanotubes, or an array of carbon nanotubes. In addition, other low-dimensional semiconductor materials such as silicon nanowires, II-VI element nanowires, III-V element nanowires, two-dimensional layered semiconductor materials and the like can also be adopted, wherein the two-dimensional layered semiconductor materials can be molybdenum disulfide, tungsten disulfide or black phosphorus.

S4 source and drain electrodes 106 are then formed on opposite sides of the low-dimensional semiconductor layer 104, as shown in fig. 6. Next, a metal yttrium film 107 is formed on the low-dimensional semiconductor layer 104 and the source and drain electrodes by electron beam evaporation, and then thermally oxidized to form an yttrium oxide transition layer, as shown in fig. 6 and 7. In other embodiments, the transition layer may be deposited by a non-plasma method, such as thermal atomic layer deposition or physical vapor deposition, and the transition layer comprises at least one of aluminum oxide, yttrium oxide, or hafnium oxide, and is preferably yttrium oxide. Next, the electrostatic doping layer 108 is formed using the layer as a transition layer, and in this embodiment, the electrostatic doping layer 108 is formed directly by plasma enhanced atomic energy deposition (PEALD) using aluminum nitride (AlN), in which fixed charges are formed.

When the electrostatic doping layer 108 is aluminum nitride, the NMOS threshold voltage can be controlled by adjusting the process temperature of the aluminum nitride atomic layer deposition, wherein the process temperature is 200-. Then, an alumina layer 109 is deposited on the electrostatically doped layer 108, an opening pattern is formed above the p-type channel region by a photolithography process, and the alumina layer 109 and the electrostatically doped layer 108 of aluminum nitride are dry-etched according to the pattern, stopping on the yttria layer, as shown in fig. 9 to 12. Subsequently, filled yttria (Y) can be further deposited in the groove₂O₃) Layer 110 as shown in fig. 13. In another embodiment, the aluminum oxide layer 109 may be dry etched first, and then the aluminum nitride layer 110 may be wet etched, so as to reduce etching damage such as charge doping caused by the dry etching process. And then, flattening the surface of the formed structure to form a PMOS with an yttria dielectric layer above a p-type channel region and an NMOS with a silicon nitride electrostatic doping layer and an alumina protective layer in an n-type channel region, thereby forming the CMOS device.

It should be noted that the above detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the example embodiments described above in accordance with the present application. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise. Furthermore, it will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in other sequences than those illustrated or otherwise described herein.

Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such process, method, article, or apparatus.

Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may also be oriented in other different ways, such as by rotating it 90 degrees or at other orientations, and the spatially relative descriptors used herein interpreted accordingly.

In the foregoing detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, like numerals typically identify like components, unless context dictates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.