阅读说明：本技术 一种钙钛矿晶硅叠层太阳能电池制作方法及电池结构 (Perovskite crystal silicon laminated solar cell manufacturing method and cell structure ) 是由 不公告发明人 于 2021-07-23 设计创作，主要内容包括：本发明公开了一种钙钛矿晶硅叠层太阳能电池制作方法,包括如下步骤：S100、对P型硅片的底部表面进行制绒,顶部表面进行制绒或者抛光,形成硅片基底；S200、采用包括但不限于热生长法,原子沉积法或等离子体增强化学气相沉积法在所述硅片基底底部表面制成底部钝化层,并通过包括但不限于激光刻蚀开孔的方法对底部钝化层进行开孔,形成底电极开孔钝化层。还包括方法制作的电池结构。本发明直接采用双面钝化的且可以独立作为太阳能电池使用的电池结构,同时具有有效的重掺杂复合层,以形成整体的电池结构,并依据这种结构提供结构的制作方法,精良高效；本方案形成的电池结构开路电压高、制备成本低廉,光电效率高。(The invention discloses a manufacturing method of a perovskite crystalline silicon laminated solar cell, which comprises the following steps: s100, performing texturing on the bottom surface of a P-type silicon wafer, and performing texturing or polishing on the top surface of the P-type silicon wafer to form a silicon wafer substrate; and S200, manufacturing a bottom passivation layer on the bottom surface of the silicon wafer substrate by adopting a thermal growth method, an atomic deposition method or a plasma enhanced chemical vapor deposition method, and opening the bottom passivation layer by adopting a laser etching opening method to form a bottom electrode opening passivation layer. Also included are battery structures made by the methods. The invention directly adopts a battery structure which is passivated on two sides and can be independently used as a solar battery, and is provided with an effective heavy doping composite layer to form an integral battery structure; the battery structure formed by the scheme has high open circuit voltage, low preparation cost and high photoelectric efficiency.)

1. A manufacturing method of a perovskite crystalline silicon tandem solar cell is characterized by comprising the following steps:

s100, performing texturing on the bottom surface of a P-type silicon wafer, and performing texturing or polishing on the top surface to form a silicon wafer substrate (110);

s200, manufacturing a bottom passivation layer on the bottom surface of the silicon wafer substrate (110), and opening a hole in the bottom passivation layer to form a bottom electrode hole-opening passivation layer (120);

s300, preparing a metal bottom electrode layer (130) on the bottom electrode opening passivation layer (120);

s400, manufacturing a first passivation layer (140) on the top surface of the silicon wafer substrate (110);

s500, preparing an N-type heavily doped polycrystalline layer (150) on the first passivation layer (140);

s600, preparing a second passivation layer (160) on the N-type heavily doped polycrystalline layer (150);

s700, preparing a P-type heavily-doped polycrystalline layer (170) on the second passivation layer (160);

s800, preparing a hole transport layer (210) on the P-type heavily-doped polycrystalline layer (170);

s900, preparing a perovskite light absorption layer (220) on the hole transport layer (210);

s1000, preparing an electron transport layer (230) on the perovskite light absorption layer (220);

s1100, preparing a top electrode buffer layer (240) on the electron transport layer (230);

s1200, preparing a transparent electrode (250) on the top electrode buffer layer (240);

s1300, preparing a metal grid line electrode layer (260) on the transparent electrode (250);

s1400, preparing an antireflection layer (270) on the metal grid line electrode layer (260).

2. The method of fabricating a perovskite crystalline silicon tandem solar cell as claimed in claim 1, wherein: forming a bottom passivation layer on a bottom surface of the silicon wafer substrate (110) comprises:

preparing a bottom passivation layer on the bottom surface of the silicon wafer substrate (110) by adopting a thermal growth method, or an atomic deposition method or a plasma enhanced chemical vapor deposition method;

the forming the bottom electrode opening passivation layer by opening the bottom passivation layer includes: and opening the bottom passivation layer by a laser etching opening method to form a bottom electrode opening passivation layer (120).

3. The method of fabricating a perovskite crystalline silicon tandem solar cell as claimed in claim 1, wherein: fabricating a metal bottom electrode layer (130) on the bottom electrode opening passivation layer (120) comprises:

and preparing a metal bottom electrode layer (130) on the bottom electrode opening passivation layer (120) by adopting an electroplating method, or an evaporation method or a printing method.

4. The method of fabricating a perovskite crystalline silicon tandem solar cell as claimed in claim 1, wherein:

forming a first passivation layer (140) on a top surface of the silicon wafer substrate (110) comprises: forming a first passivation layer (140) on the top surface of the silicon wafer substrate (110) by using a plasma enhanced chemical vapor deposition method and a thermal growth method; and/or

The preparation of the N-type heavily doped polycrystalline layer (150) on the first passivation layer (140) comprises: preparing an N-type heavily doped polycrystalline layer (150) on the first passivation layer (140) by adopting a plasma enhanced chemical vapor deposition method and a low-pressure chemical vapor deposition method; and/or

The step of preparing a second passivation layer (160) on the N-type heavily doped polycrystalline layer (150) comprises the following steps: preparing a second passivation layer (160) on the N-type heavily doped polycrystalline layer (150) by using a plasma enhanced chemical vapor deposition method and a thermal growth method; and/or

The preparation of the P-type heavily doped polycrystalline layer (170) on the second passivation layer (160) comprises: and preparing the P-type heavily-doped polycrystalline layer (170) on the second passivation layer (160) by adopting a plasma enhanced chemical vapor deposition method and a low-pressure chemical vapor deposition method.

5. The method of fabricating a perovskite crystalline silicon tandem solar cell as claimed in claim 1, wherein: preparing a hole transport layer (210) on the P-type heavily doped polycrystalline layer (170) includes: preparing a hole transport layer (210) on the P-type heavily doped polycrystalline layer (170) by adopting a spin coating, or evaporation, or sputtering, or spraying, or thermal spray decomposition, or blade coating, or printing and slot coating method; and/or

Fabricating a perovskite light absorbing layer (220) on the hole transport layer (210) comprises: preparing a perovskite light absorption layer (220) on the hole transport layer (210) by adopting a spin coating, or evaporation, or sputtering, or spraying, or thermal spraying decomposition, or blade coating, or printing and slit coating method; and/or

Preparing a perovskite light absorbing layer (220) on the hole transport layer (210): and preparing an electron transport layer (230) on the perovskite light absorption layer (220) by adopting a spin coating, or evaporation, or sputtering, or spray coating, or thermal spray decomposition, or blade coating, or printing and slot coating method.

6. The method of fabricating a perovskite crystalline silicon tandem solar cell as claimed in claim 1, wherein: preparing a top electrode buffer layer (240) on the electron transport layer (230) includes: preparing a top electrode buffer layer (240) on the electron transport layer (230) by sputtering, atomic deposition and evaporation; and/or

Preparing a transparent electrode (250) on the top electrode buffer layer (240) includes: preparing a transparent electrode (250) on the top electrode buffer layer (240) by adopting sputtering, atomic deposition and evaporation methods; and/or

Preparing a metal gate line electrode layer (260) on the transparent electrode (250) comprises: preparing a metal grid line electrode layer (260) on the transparent electrode (250) by adopting evaporation, printing and electroplating methods; and/or

Preparing an anti-reflection layer (270) on the metal gate line electrode layer (260) comprises: and preparing an antireflection layer (270) on the metal grid line electrode layer (260) by adopting evaporation, sputtering and atomic deposition methods.

7. The method of fabricating a perovskite crystalline silicon tandem solar cell as defined in any one of claims 1 to 6, wherein: forming an N-type doped emitter layer (180) on the top surface of the silicon wafer substrate (110) by a tubular boron diffusion or chain boron diffusion method between the steps S100 and S200, or between the steps S300 and S400, and forming the first passivation layer (140) on the surface of the N-type doped emitter layer (180).

8. The method of fabricating a perovskite crystalline silicon tandem solar cell as defined in any one of claims 1 to 6, wherein: preparing a P-type silicon wafer with the resistivity of 1-5 ohm-cm for later use by a suspension zone melting method before the step S100.

9. A solar cell structure manufactured by the solar cell manufacturing method according to any one of claims 1 to 8, wherein the solar cell structure is a layered structure and comprises a bottom electrode unit (100) at the bottom and a top electrode unit (200) at the top, and the bottom electrode unit (100) and the top electrode unit (200) are stacked to form a whole;

the bottom electrode unit (100) comprises a silicon wafer substrate (110), the silicon wafer substrate (110) is made of P-type silicon, a bottom electrode opening passivation layer (120) is formed on the bottom surface of the silicon wafer substrate (110), and a metal bottom electrode layer (130) is arranged on the bottom surface of the bottom electrode opening passivation layer (120); a first passivation layer (140) is formed on the top surface of the silicon wafer substrate (110), an N-type heavily-doped polycrystalline layer (150) is formed on the top surface of the first passivation layer (140), a second passivation layer (160) is formed on the top surface of the N-type heavily-doped polycrystalline layer (150), and a P-type heavily-doped polycrystalline layer (170) is formed on the top surface of the second passivation layer (160);

the top electrode unit (200) comprises a hole transport layer (210), the bottom surface of the hole transport layer (210) is connected to the top surface of the P-type heavily-doped polycrystalline layer (170), the top surface of the hole transport layer (210) is provided with a perovskite light absorption layer (220), the top surface of the perovskite light absorption layer (220) is provided with an electron transport layer (230), the top surface of the electron transport layer (230) is provided with a top electrode buffer layer (240), the top surface of the top electrode buffer layer (240) is provided with a transparent electrode (250), the top surface of the transparent electrode (250) is provided with a metal grid line electrode layer (260), and the top surface of the metal grid line electrode layer (260) is provided with an antireflection layer (270); the necessary material of the transparent electrode (250) includes ITO, IZO, AZO, and graphene.

10. The solar cell structure of claim 9, wherein an N-doped emitter layer (180) is formed between the silicon wafer substrate (110) and the first passivation layer (140), and a bottom surface of the N-doped emitter layer (180) is connected to a top surface of the silicon wafer substrate (110), and a top surface of the N-doped emitter layer (180) is connected to a bottom surface of the first passivation layer (140).

Technical Field

The invention relates to the technical field of solar cells, in particular to a perovskite crystalline silicon tandem solar cell manufacturing method and a cell structure.

Background

Photovoltaic energy has been developed rapidly in recent years as one of the most important renewable energy sources. Solar cells are the most important part of photovoltaic energy systems, and improving the photoelectric conversion efficiency of the solar cells is the most important way to reduce the cost of photovoltaic energy.

At present, industrialized crystalline silicon photovoltaic cells are gradually close to the bottleneck, the efficiency improvement is small, and due to the higher limit efficiency of the laminated photovoltaic cells, the most favorable theoretical technical support is provided for reducing the power consumption cost of photovoltaic energy.

The perovskite material has the characteristics of low cost, adjustable band gap and the like, and the perovskite-crystalline silicon laminated solar cell combined with the silicon bottom cell can improve the efficiency limit of the silicon solar cell to more than 40 percent, so that the perovskite-crystalline silicon laminated solar cell is considered as the most promising next-generation photovoltaic technology in the photovoltaic industry.

In the existing crystalline silicon perovskite laminated solar cell, due to the requirement of a preparation process, the front surface of a bottom cell generally adopts a polished emitter without passivation, so that the laminated voltage is low, and the integral photoelectric conversion efficiency is influenced. Therefore, the laminated structure with the passivation front surface can provide effective compounding, the efficiency of the photovoltaic cell can be further improved, and the power generation cost of a photovoltaic system is reduced. Based on this, a corresponding solar cell structure needs to be developed.

Disclosure of Invention

In view of the above circumstances, an object of the present invention is to provide a method for manufacturing a perovskite-crystalline silicon tandem solar cell, which comprises the following steps:

a manufacturing method of a perovskite crystalline silicon tandem solar cell comprises the following steps:

s100, performing texturing on the bottom surface of a P-type silicon wafer, and performing texturing or polishing on the top surface to form a silicon wafer substrate (110);

s200, manufacturing a bottom passivation layer on the bottom surface of the silicon wafer substrate (110), and opening a hole in the bottom passivation layer to form a bottom electrode hole-opening passivation layer (120);

s300, preparing a metal bottom electrode layer (130) on the bottom electrode opening passivation layer (120);

s400, manufacturing a first passivation layer (140) on the top surface of the silicon wafer substrate (110);

s500, preparing an N-type heavily doped polycrystalline layer (150) on the first passivation layer (140);

s600, preparing a second passivation layer (160) on the N-type heavily doped polycrystalline layer (150);

s700, preparing a P-type heavily-doped polycrystalline layer (170) on the second passivation layer (160);

s800, preparing a hole transport layer (210) on the P-type heavily-doped polycrystalline layer (170);

s900, preparing a perovskite light absorption layer (220) on the hole transport layer (210);

s1000, preparing an electron transport layer (230) on the perovskite light absorption layer (220);

s1100, preparing a top electrode buffer layer (240) on the electron transport layer (230);

s1200, preparing a transparent electrode (250) on the top electrode buffer layer (240);

s1300, preparing a metal grid line electrode layer (260) on the transparent electrode (250);

s1400, preparing an antireflection layer (270) on the metal grid line electrode layer (260).

Forming a bottom passivation layer on a bottom surface of the silicon wafer substrate (110) comprises:

preparing a bottom passivation layer on the bottom surface of the silicon wafer substrate (110) by adopting a thermal growth method, or an atomic deposition method or a plasma enhanced chemical vapor deposition method;

opening the bottom passivation layer to form a bottom electrode opening passivation layer comprising: and opening the bottom passivation layer by a laser etching opening method to form a bottom electrode opening passivation layer (120).

Fabricating a metal bottom electrode layer (130) on the bottom electrode opening passivation layer (120) comprises:

and preparing a metal bottom electrode layer (130) on the bottom electrode opening passivation layer (120) by adopting an electroplating method, or an evaporation method or a printing method.

Forming a first passivation layer (140) on a top surface of the silicon wafer substrate (110) comprises: forming a first passivation layer (140) on the top surface of the silicon wafer substrate (110) by using a plasma enhanced chemical vapor deposition method and a thermal growth method; and/or

The preparation of the N-type heavily doped polycrystalline layer (150) on the first passivation layer (140) comprises: preparing an N-type heavily doped polycrystalline layer (150) on the first passivation layer (140) by adopting a plasma enhanced chemical vapor deposition method and a low-pressure chemical vapor deposition method; and/or

The step of preparing a second passivation layer (160) on the N-type heavily doped polycrystalline layer (150) comprises the following steps: preparing a second passivation layer (160) on the N-type heavily doped polycrystalline layer (150) by using a plasma enhanced chemical vapor deposition method and a thermal growth method; and/or

The preparation of the P-type heavily doped polycrystalline layer (170) on the second passivation layer (160) comprises: and preparing the P-type heavily-doped polycrystalline layer (170) on the second passivation layer (160) by adopting a plasma enhanced chemical vapor deposition method and a low-pressure chemical vapor deposition method.

Preparing a hole transport layer (210) on the P-type heavily doped polycrystalline layer (170) includes: preparing a hole transport layer (210) on the P-type heavily doped polycrystalline layer (170) by adopting a spin coating, or evaporation, or sputtering, or spraying, or thermal spray decomposition, or blade coating, or printing and slot coating method; and/or

Fabricating a perovskite light absorbing layer (220) on the hole transport layer (210) comprises: preparing a perovskite light absorption layer (220) on the hole transport layer (210) by adopting a spin coating, or evaporation, or sputtering, or spraying, or thermal spraying decomposition, or blade coating, or printing and slit coating method; and/or

Preparing a perovskite light absorbing layer (220) on the hole transport layer (210): and preparing an electron transport layer (230) on the perovskite light absorption layer (220) by adopting a spin coating, or evaporation, or sputtering, or spray coating, or thermal spray decomposition, or blade coating, or printing and slot coating method.

Preparing a top electrode buffer layer (240) on the electron transport layer (230) includes: preparing a top electrode buffer layer (240) on the electron transport layer (230) by sputtering, atomic deposition and evaporation; and/or

Preparing a transparent electrode (250) on the top electrode buffer layer (240) includes: preparing a transparent electrode (250) on the top electrode buffer layer (240) by adopting sputtering, atomic deposition and evaporation methods; and/or

Preparing a metal gate line electrode layer (260) on the transparent electrode (250) comprises: preparing a metal grid line electrode layer (260) on the transparent electrode (250) by adopting evaporation, printing and electroplating methods; and/or

Preparing an anti-reflection layer (270) on the metal gate line electrode layer (260) comprises: and preparing an antireflection layer (270) on the metal grid line electrode layer (260) by adopting evaporation, sputtering and atomic deposition methods.

Forming an N-type doped emitter layer (180) on the top surface of the silicon wafer substrate (110) by a tubular boron diffusion or chain boron diffusion method between the steps S100 and S200, or between the steps S300 and S400, and forming the first passivation layer (140) on the surface of the N-type doped emitter layer (180).

Preparing a P-type silicon wafer with the resistivity of 1-5 ohm-cm for later use by a suspension zone melting method before the step S100.

Another object of the present invention is to provide a solar cell structure manufactured by the above solar cell manufacturing method, wherein the solar cell structure is a layered structure and includes a bottom electrode unit (100) located at the bottom and a top electrode unit (200) located at the top, and the bottom electrode unit (100) and the top electrode unit (200) are stacked to form a whole;

the bottom electrode unit (100) comprises a silicon wafer substrate (110), the silicon wafer substrate (110) is made of P-type silicon, a bottom electrode opening passivation layer (120) is formed on the bottom surface of the silicon wafer substrate (110), and a metal bottom electrode layer (130) is arranged on the bottom surface of the bottom electrode opening passivation layer (120); a first passivation layer (140) is formed on the top surface of the silicon wafer substrate (110), an N-type heavily-doped polycrystalline layer (150) is formed on the top surface of the first passivation layer (140), a second passivation layer (160) is formed on the top surface of the N-type heavily-doped polycrystalline layer (150), and a P-type heavily-doped polycrystalline layer (170) is formed on the top surface of the second passivation layer (160);

the top electrode unit (200) comprises a hole transport layer (210), the bottom surface of the hole transport layer (210) is connected to the top surface of the P-type heavily-doped polycrystalline layer (170), the top surface of the hole transport layer (210) is provided with a perovskite light absorption layer (220), the top surface of the perovskite light absorption layer (220) is provided with an electron transport layer (230), the top surface of the electron transport layer (230) is provided with a top electrode buffer layer (240), the top surface of the top electrode buffer layer (240) is provided with a transparent electrode (250), the top surface of the transparent electrode (250) is provided with a metal grid line electrode layer (260), and the top surface of the metal grid line electrode layer (260) is provided with an antireflection layer (270); the necessary material of the transparent electrode (250) includes ITO, IZO, AZO, and graphene.

An N-type doped emitter layer (180) is formed between the silicon wafer substrate (110) and the first passivation layer (140), the bottom surface of the N-type doped emitter layer (180) is connected to the top surface of the silicon wafer substrate (110), and the top surface of the N-type doped emitter layer (180) is connected to the bottom surface of the first passivation layer (140).

Has the advantages that: the method can well form various layered structures on a silicon substrate, tunnel and passivate the contacted composite polycrystalline silicon passivation layer on the front side and the back side, the effect of the double-sided passivation structure of the silicon substrate layer can improve the open-circuit voltage of the silicon battery, the composite doped polycrystalline silicon passivation layer on the upper surface can be used as the middle tunneling layer of the laminated battery, and the prepared silicon bottom battery has high open-circuit voltage, is particularly suitable for preparing a multi-junction laminated solar battery and has higher photoelectric conversion efficiency.

Drawings

Fig. 1 is a schematic diagram of a solar structure according to an embodiment of the invention.

Detailed Description

The invention is further described in the following detailed description with reference to the drawings and examples as preferred embodiments:

example one

Referring to fig. 1, the method for manufacturing a perovskite-crystalline silicon tandem solar cell based on the structure includes the following steps:

s100, performing texturing on the bottom surface of a P-type silicon wafer, and performing texturing or polishing on the top surface of the P-type silicon wafer to form a silicon wafer substrate 110;

in the specific implementation process, the surface of the P-type silicon 103 is subjected to texturing or polishing treatment by using but not limited to an alkaline solution.

S200, manufacturing a bottom passivation layer on the bottom surface of the silicon wafer substrate (110), and opening a hole in the bottom passivation layer to form a bottom electrode hole-opening passivation layer (120);

in the specific implementation process, a bottom passivation layer is formed on the bottom surface of the silicon wafer substrate 110 by a thermal growth method, an atomic deposition method or a plasma enhanced chemical vapor deposition method, and the bottom passivation layer is opened by a laser etching opening method to form a bottom electrode opening passivation layer 120;

s300, preparing a metal bottom electrode layer (130) on the bottom electrode opening passivation layer (120);

in the specific implementation process, the metal bottom electrode layer 130 is prepared on the bottom electrode opening passivation layer 120 by using a plating method, an evaporation method or a printing method;

s400, manufacturing a first passivation layer (140) on the top surface of the silicon wafer substrate (110);

in the specific implementation process, a first passivation layer 140 is formed on the top surface of the silicon wafer substrate 110 by using a plasma enhanced chemical vapor deposition method and a thermal growth method;

s500, preparing an N-type heavily doped polycrystalline layer (150) on the first passivation layer (140);

in the specific implementation process, the N-type heavily doped polycrystalline layer 150 is prepared on the first passivation layer 140 by using a plasma enhanced chemical vapor deposition method and a low pressure chemical vapor deposition method;

s600, preparing a second passivation layer (160) on the N-type heavily doped polycrystalline layer (150);

in the specific implementation process, the second passivation layer 160 is prepared on the N-type heavily doped polycrystalline layer 150 by using a plasma enhanced chemical vapor deposition method and a thermal growth method;

s700, preparing a P-type heavily-doped polycrystalline layer (170) on the second passivation layer (160);

in the specific implementation process, the P-type heavily doped polycrystalline layer 170 is prepared on the second passivation layer 160 by using a plasma enhanced chemical vapor deposition method and a low pressure chemical vapor deposition method;

s800, preparing a hole transport layer (210) on the P-type heavily-doped polycrystalline layer (170);

in specific implementations, the hole transport layer 210 is prepared on the P-type heavily doped polycrystalline layer 170 by methods including, but not limited to, spin coating, evaporation, sputtering, spray coating, thermal spray decomposition, blade coating, printing, and slot coating;

s900, preparing a perovskite light absorption layer (220) on the hole transport layer (210);

in specific implementations, perovskite light absorbing layer 220 is prepared on hole transport layer 210 using methods including, but not limited to, spin coating, evaporation, sputtering, spray coating, thermal spray decomposition, blade coating, printing, and slot coating;

s1000, preparing an electron transport layer (230) on the perovskite light absorption layer (220);

in specific implementations, the electron transport layer 230 is prepared on the perovskite light absorbing layer 220 using methods including, but not limited to, spin coating, evaporation, sputtering, spray coating, thermal spray decomposition, blade coating, printing, and slot coating;

s1100, preparing a top electrode buffer layer (240) on the electron transport layer (230);

in specific implementations, the top electrode buffer layer 240 is prepared on the electron transport layer 230 by methods including, but not limited to, sputtering, atomic deposition, and evaporation;

s1200, preparing a transparent electrode (250) on the top electrode buffer layer (240);

in the specific implementation process, the transparent electrode 250 is prepared on the top electrode buffer layer 240 by methods including but not limited to sputtering, atomic deposition and evaporation;

s1300, preparing a metal grid line electrode layer (260) on the transparent electrode (250);

in the specific implementation process, the metal gate line electrode layer 260 is prepared on the transparent electrode 250 by methods including but not limited to evaporation, printing and electroplating;

s1400, preparing an antireflection layer (270) on the metal grid line electrode layer (260);

in a specific implementation, the anti-reflective layer 270 is formed on the metal gate line electrode layer 260 by using methods including, but not limited to, evaporation, sputtering, and atomic deposition.

It is further preferable that the N-type doped emitter layer 180 is formed on the top surface of the silicon wafer substrate 110 between steps S100 and S200, or between steps S300 and S400 by a method including, but not limited to, tube type boron diffusion or chain type boron diffusion, and then the first passivation layer 140 is formed on the surface of the N-type doped emitter layer 180.

It is further preferable to prepare a P-type silicon wafer having a resistivity of 1-5 ohm-cm by a suspension melting method before step S100.

Based on the above process steps, and preferred steps. In specific implementation, a P-type silicon wafer with the resistivity of 1-5 ohm-cm can be prepared by a suspension zone melting method; texturing is carried out on the bottom surface of the P-type silicon wafer, phosphorus is diffused on the top surface to form a PN homojunction, and an N-type doped emitter layer 180 with lower doping concentration is formed, wherein the doping concentration is 5 x 1018cm < -3 >. And preparing a passivation layer of Al2O3/SiNx on the bottom surface of the P-type silicon wafer by ALD and PECVD, namely the bottom passivation layer. The top surface of the P-type silicon wafer is grown with a 3nm SiO2 passivation layer by ALD, i.e., the first passivation layer 140. And growing a 60nm heavily-doped N-type polycrystalline silicon layer on the top surface of the P-type silicon wafer by LPCVD (low pressure chemical vapor deposition), namely an N-type heavily-doped polycrystalline layer 150 with the doping concentration of 1.5 x 1020cm & lt-3 & gt. And growing a 2nm SiO2 passivation layer on the surface of the heavily-doped N-type polycrystalline silicon layer by ALD, namely the second passivation layer 160. And growing 20nm heavily doped P-type polycrystalline silicon by LPCVD (low pressure chemical vapor deposition), namely a P-type heavily doped polycrystalline layer 170 with the doping concentration of 3 x 1020cm < -3 >. And screen printing a 2-micron silver electrode to prepare a metal bottom electrode, namely the metal bottom electrode layer 130. And treating the surface of the P heavily-doped polysilicon layer by using plasma, and then spin-coating the PTAA on the front surface of the silicon wafer to obtain the hole transport layer 210. The perovskite light absorbing layer 220 of FAMACs was prepared in a one-step process with a thickness of 600 nm. The 25 nm C60 electron transport layer 230 was prepared by evaporation. The top electrode buffer layer 240 of 15nm SnO2 was prepared using ALD. The AZO transparent electrode 250 is prepared by a sputtering method. And preparing a metal grid line electrode layer 260 and a LiF antireflection layer 270 by evaporation, wherein the thicknesses of the metal grid line electrode layer and the LiF antireflection layer are 300nm and 120nm respectively.

Through the IV performance test, the tandem solar cell device obtained an open circuit voltage of 1.85V and a photoelectric conversion efficiency of 24.1%.

Example two

Fig. 1 shows a perovskite-crystalline silicon tandem solar cell structure in an embodiment of the present invention, which is a layered structure and includes a bottom electrode unit 100 at the bottom and a top electrode unit 200 at the top, wherein the bottom electrode unit 100 and the top electrode unit 200 are stacked to form a whole; the bottom electrode unit 100 includes a silicon wafer substrate 110, the silicon wafer substrate 110 is made of P-type silicon, a bottom electrode opening passivation layer 120 is formed on the bottom surface of the silicon wafer substrate 110, and a metal bottom electrode layer 130 is disposed on the bottom surface of the bottom electrode opening passivation layer 120; a first passivation layer 140 is formed on the top surface of the silicon wafer substrate 110, an N-type heavily doped polycrystalline layer 150 is formed on the top surface of the first passivation layer 140, a second passivation layer 160 is formed on the top surface of the N-type heavily doped polycrystalline layer 150, and a P-type heavily doped polycrystalline layer 170 is formed on the top surface of the second passivation layer 160; the top electrode unit 200 includes a hole transport layer 210, a bottom surface of the hole transport layer 210 is connected to a top surface of the P-type heavily doped polycrystalline layer 170, a top surface of the hole transport layer 210 is provided with a perovskite light absorbing layer 220, a top surface of the perovskite light absorbing layer 220 is provided with an electron transport layer 230, a top surface of the electron transport layer 230 is provided with a top electrode buffer layer 240, a top surface of the top electrode buffer layer 240 is provided with a transparent electrode 250, a top surface of the transparent electrode 250 is provided with a metal gate line electrode layer 260, and a top surface of the metal gate line electrode layer 260 is provided with an anti-reflection layer 270.

In the above basic solution of the present invention, the bottom electrode unit 100 and the top electrode unit 200 can be used as independent solar cell structures.

P-type silicon is selected as the silicon wafer substrate 110, specifically, the resistivity of the silicon wafer substrate 110 is 0.1-50 ohm cm, the thickness is 100-800 μm, the bottom surface is a textured structure, and the top surface is a pyramid textured mechanism or/and a polishing structure. In addition, the bottom surface and the top surface of the silicon wafer substrate 110 may also be a diamond wire-cut back surface structure. The metal bottom electrode layer 130 is made of one or more materials of aluminum, silver, titanium, palladium, nickel, chromium or copper, and has a thickness of 1-2000 μm. The bottom electrode opening passivation layer 120 is made of one or more of SiO2, Al2O3, Si3N4, AlN, INSb, SiC, TiO2, microcrystalline silicon or amorphous silicon, and has a thickness of 0-20 nm.

Specifically, preferably, an N-type doped emitter layer 180 is formed between the silicon wafer substrate 110 and the first passivation layer 140, a bottom surface of the N-type doped emitter layer 180 is connected to a top surface of the silicon wafer substrate 110, and a top surface of the N-type doped emitter layer 180 is connected to a bottom surface of the first passivation layer 140. Further, the depth of the N-type doped emitter layer 180 is 0.5-10 μm, and the diffusion sheet resistance is 1-150 ohm/sq.

Specifically, the first passivation layer 140 and the second passivation layer 160 are silicon oxide passivation layers or amorphous passivation layers with a thickness of 0 to 50 nm.

Specifically, the doping concentration of the N-type heavily doped polycrystalline layer 150 is 8 × 1018 cm-3 to 1 × 1021 cm-3, and the thickness of the N-type heavily doped polycrystalline layer 150 may be 0-100 nm.

Specifically, the doping concentration of the P-type heavily doped polycrystalline layer 170 is 8 × 1018 cm-3 to 2 × 1021 cm-3, and the thickness of the P-type heavily doped polycrystalline layer 170 may be 0-100 nm.

The hole transport layer 210 is made of one or more of PTAA, Poly-TPD, NiOx, P3HT, V2O5, MoOx, PEDOT, PSS, WOx, Spiro-OMeTAD, CuSCN, Cu2O, CuI, Spiro-TTB, F4-TCNQ, F6-TCNNQ, m-MTDATA or TAPC, and SAM (Self-assembled monolayer, such as MeO-2 PACZ), and the thickness of the hole transport layer 210 may be 0-1000 nm.

Specifically, the perovskite light absorbing layer 220 material is made of the general formula ABX3, wherein: a is a monovalent cation including, but not limited to, one or more of lithium, sodium, potassium, cesium, rubidium, an amine, or an amidino; b is a divalent cation including, but not limited to, one or more cations of lead particles, tin particles, tungsten particles, copper particles, zinc particles, gallium particles, selenium particles, rhodium particles, germanium particles, arsenic particles, palladium particles, silver particles, gold particles, indium particles, antimony particles, mercury particles, iridium particles, thallium particles, bismuth particles; x is a monovalent anion, including but not limited to one or more anions of iodine particles, bromine particles, chlorine particles, or astatine particles; the thickness of the perovskite light absorption layer 220 is 0.05-100 μm.

Specifically, the perovskite light absorption layer 220 material has a chemical formula Cs0.05FA0.80MA0.15PbI2.55Br0.45, wherein Cs is cesium, FA is formamidino, MA is methylamino, and I is iodine. The thickness of the light absorbing layer is 0.05-100 μm.

Specifically, the material of which the electron transport layer 230 is made is one or more of SnO2, TiO2, ZnO, ZrO2, TiSnOx, SnZnOx, fullerene, and derivatives thereof; the electron transport layer 230 has a thickness of 0 to 500 nm.

Specifically, the material of which the top electrode buffer layer 240 is made is one or more of V2O5, MoOx, Ag, Au, Cu, SnO2, ZnO, TiO2, Al2O3, SiO2, Si3N4, PMMA, BCP, PEIE microcrystalline silicon or amorphous silicon; the top electrode buffer layer 240 has a thickness of 0-50 nm.

Specifically, the necessary materials for making the transparent electrode 250 are ITO, IZO, AZO, and graphene, and include, but are not limited to, one or more of Ag, Au, Cu, and Al metal nanowires; the thickness of the transparent electrode 250 is 0-500 nm.

Specifically, the metal gate line electrode layer 260 is made of one or more of ITO, IZO, AZO, graphene, and metal nanowires including but not limited to Ag, Au, Cu, or Al, and the thickness of the metal gate line electrode layer 260 is 0 to 500 nm.

Specifically, the antireflection layer 270 is made of one or more of LiF, MgF2, AlN, ZnS, Si3N4, SiO2, TiO2, or a flexible adhesive film having a textured structure, and the thickness of the antireflection layer 270 is 0-3 mm.

The names of the technical features and the letter expressions of the material names are all commonly used in the field.

The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.