阅读说明：本技术 一种多路Weil码发生方法及装置 (Multi-path Weil code generation method and device ) 是由 朱佳 丁杰 宋佳驹 傅东 翁秀梅 于 2021-10-25 设计创作，主要内容包括：本发明公开了一种多路Weil码发生方法和装置。通过引入两路Legendre序列模块,每个Legendre序列模块同时支持多个通道的Legendre序列控制器的访问请求；每个Legendre序列模块包括仲裁器单元和Legendre序列数组单元,仲裁器单元对读取请求进行轮询调度,并将读取的码值反馈至对应所述Legendre序列控制器；同时,通过相关器通道的共用相应设计读取Legendre序列的位宽,从而解决读取Legendre序列的带宽问题,通过Legendre序列控制器50增加预读的处理的步骤,解决读取Legendre序列的实时性问题。该方案能极大减少芯片面积和后端设计复杂度,降低功耗。(The invention discloses a method and a device for generating multi-path Weil codes. By introducing two Legendre sequence modules, each Legendre sequence module simultaneously supports access requests of Legendre sequence controllers of a plurality of channels; each Legendre sequence module comprises an arbiter unit and a Legendre sequence array unit, wherein the arbiter unit performs polling scheduling on a reading request and feeds back a read code value to the corresponding Legendre sequence controller; meanwhile, the bit width of the Legendre sequence is read through the common corresponding design of the correlator channels, so that the problem of bandwidth for reading the Legendre sequence is solved, and the problem of real-time performance for reading the Legendre sequence is solved by adding a pre-reading processing step through the Legendre sequence controller 50. The scheme can greatly reduce the chip area and the complexity of the back end design, and reduce the power consumption.)

1. A multi-channel Weil code generating device is characterized by comprising a plurality of Weil code generators corresponding to different correlator channels one by one, and at least one Legendre sequence module shared by a plurality of correlator channels;

each Legendre sequence module comprises an arbiter unit and a Legendre sequence array unit, and solidified Legendre sequences are stored in the Legendre sequence array unit;

each Weil code generator comprises a data Weil code generator and a pilot Weil code generator, each data Weil code generator comprises two Legendre sequence controllers, each pilot Weil code generator comprises two Legendre sequence controllers, and each Legendre sequence controller is used for reading a code value with a preset length in a Legendre sequence from the Legendre sequence module according to a preset reading rule;

the arbiter unit receives a reading request sent by the Legendre sequence controller, performs polling scheduling on the reading request, responds to the currently scheduled reading request, reads a code value with a preset length in the Legendre sequence from the Legendre sequence array unit according to the preset reading rule, and feeds the code value back to the Legendre sequence controller;

and the Legendre sequence controller of the pilot Weil code generator receives the fed back code value to calculate and then generates a corresponding pilot component Weil chip.

2. The multi-channel Weil code generator according to claim 1, wherein said correlator channels and said Weil code generators are 12 in number, said Legendre sequence modules are 2 in number, and each of said Legendre sequence modules corresponds to 6 of said correlator channels and said Weil code generators.

3. The multi-way Weil code generator according to claim 1, wherein said Legendre sequence array unit is a ROM storing said Legendre sequence.

4. A multi-way Weil code generating method for use with the multi-way Weil code generating device of any one of claims 1-3, comprising the steps of:

s1, the Legendre sequence controllers process in parallel and respectively initiate Legendre sequence reading requests;

s21, the arbiter unit receives the read request sent by the Legendre sequence controller, and performs polling scheduling on the read request, and responds to the currently scheduled read request;

s22, reading a code value with a preset length in the Legendre sequence from the Legendre sequence array unit according to the preset reading rule, and feeding the code value back to the controller corresponding to the Legendre sequence;

s3, the Legendre sequence controller of the data Weil code generator receives the fed back code value to calculate and then generates a corresponding data component Weil chip, and the Legendre sequence controller of the pilot Weil code generator receives the fed back code value to calculate and then generates a corresponding pilot component Weil chip.

5. The method of claim 4, wherein said step S1 includes: the Legendre sequence controllers perform parallel processing, and when each Legendre sequence controller updates a corresponding Weil chip, whether the code value currently used by the Legendre sequence controller is calculated is judged;

and when the currently used code value is not calculated, continuously using the currently used code value to generate the corresponding data component Weil chip or pilot component Weil chip after calculation.

6. The method of multiple Weil code generation as claimed in claim 5, wherein said code values obtained each time are 32 bits in length and said Legendre sequence is 312 x 32 bits in size.

7. The method for generating multi-way Weil code according to claim 5 or 6, wherein said step S1 is preceded by the steps of:

s01, when the Legendre sequence controllers are initialized, two Legendre sequence controllers in each Weil code generator perform parallel processing, and respectively initiate a first read request and a second read request for reading the Legendre sequence;

s02, the arbiter unit receives the first reading request and the second reading request sent by the Legendre sequence controller, performs polling scheduling on the first Legendre sequence reading request and the second Legendre sequence reading request, responds to the currently scheduled reading request, reads a code value with a preset length in the Legendre sequence from the Legendre sequence array unit according to the preset reading rule, and feeds the code value back to the corresponding Legendre sequence controller;

s03, the Legendre sequence controller records the code value obtained corresponding to the first reading request as a currently used code value Cur _ Legendre Dword, and records the code value obtained corresponding to the second reading request as a Pre-read code value Pre _ Legendre Dword;

wherein, the step S3 specifically includes: and the Legendre sequence controller of the pilot Weil code generator calculates according to the Cur _ Legendre Dword to generate a corresponding data component Weil code sheet, and the Legendre sequence controller of the pilot Weil code generator calculates according to the Cur _ Legendre Dword to generate a corresponding pilot component Weil code sheet.

8. The method of multi-way Weil code generation as claimed in claim 7, wherein said step S1 further comprises the steps of: and when the currently used code value is calculated, recording the current Pre _ Legendre Dword as Cur _ Legendre Dword, initiating the reading request by the Legendre sequence controller, and recording the newly received code value as a new Pre _ Legendre Dword.

9. The multi-way Weil-code generation method of claim 4, further comprising the step of reading initialization of a configuration request of said multi-way Weil-code generation device.

Technical Field

The invention relates to the technical field of satellite navigation, in particular to a multi-path Weil code generation method and a multi-path Weil code generation device.

Background

With the development of satellite navigation technology, Weil codes are introduced into new systems such as GPS L1C and Beidou B1C as satellite PRN code sequences. The Weil code sequence is increased from the common 1023 code length to 10230, the code rate is improved by ten times, so that the code autocorrelation and cross correlation are better, and the positioning precision is improved. However, the Weil code needs to read two independent chip values from the Legendre sequence, and needs to use a Random Access Memory (RAM) to store the Legendre sequence, so that a large amount of logic resources are occupied.

Due to the increase of the number of on-orbit satellites, new changes are brought to the Weil code generator of the multi-mode multi-frequency navigation chip. For example, in a multi-mode multi-frequency navigation chip, especially for the requirement of high-precision positioning of positioning and orientation, a plurality of tracking subsystems need to be introduced, each tracking subsystem needs to support 12-channel multi-channel characteristics, and when each channel supports data pilot frequency joint tracking, a 24-channel Weil code generator needs to be introduced altogether. Therefore, the design of the overall Weil code generator introduces a large amount of buffering, which results in large area and power consumption.

A block diagram of a typical scheme of a tracking subsystem 100 supporting multiple Weil codes is shown in fig. 1, in order to achieve better positioning accuracy and user experience, a satellite navigation system needs to support simultaneous tracking of multiple satellites, 12 correlator channels are generally introduced into the tracking subsystem, and can support tracking of 12 satellites at the same time, and a correlator can achieve tracking of 24 or more satellites through multiplexing.

In each correlator channel, to support data-pilot joint tracking, two way Weil code generators are introduced, respectively a data Weil code generator 110 and a pilot Weil code generator 120, for updating the chips of the data component and the pilot component, respectively. In each Weil code generator, two Legendre sequence controllers are designed to respectively obtain two independent Legendre chips; meanwhile, in order to meet the scene of acquiring the code slice in real time, two paths of matched Legendre sequence caches need to be introduced; the Legendre sequence controller reads Legendre sequences from a Legendre sequence buffer, and outputs Weil chips after calculation. For example, a Legendre sequence controller I111 and a Legendre sequence controller II 112, a Legendre sequence cache I113 and a Legendre sequence cache II 114 are respectively arranged in the data Weil code generator 110; a Legendre sequence controller I121 and a Legendre sequence controller II 122, a Legendre sequence buffer I123 and a Legendre sequence buffer II 124 are respectively arranged in the pilot Weil code generator 120.

The Legendre sequence cache generally uses an RAM, the system writes the calculated Legendre sequence into the RAM through a configuration bus in an initialization stage, and a controller reads the value of the RAM in the subsequent real-time tracking process; the Legendre sequence is about 10240 bits long, so each buffer size is approximately 10 kbit. The period of the Legendre sequence in the whole tracking subsystem is counted as 10223 and 10243, in order to support the Weil code generator of 12 correlators, the total capacity of Legendre cache needs to be increased to 480kbit, and the total quantity is 48, so that the area and the power consumption of a chip are greatly increased, and the complexity of back-end design is increased. The design of the multipath Weil code by using the traditional method can cause the difficulty of chip wiring, and simultaneously can cause the increase of area and power consumption, and the increase of the cost of the chip.

In view of this, it is necessary to introduce a new set of multi-path Weil code generation method and apparatus in the tracking subsystem supporting multi-path Weil code, so as to improve the efficiency of the Weil code generator and reduce the chip cost.

Disclosure of Invention

The present invention is directed to a method and an apparatus for generating multi-way Weil codes, so as to solve the above-mentioned problems.

In order to achieve the purpose, the invention provides a multi-path Weil code generating device, which comprises a plurality of Weil code generators corresponding to different correlator channels one by one, and at least one Legendre sequence module shared by a plurality of correlator channels;

each Legendre sequence module comprises an arbiter unit and a Legendre sequence array unit, and solidified Legendre sequences are stored in the Legendre sequence array unit;

each Weil code generator comprises a data Weil code generator and a pilot Weil code generator, each data Weil code generator comprises two Legendre sequence controllers, each pilot Weil code generator comprises two Legendre sequence controllers, and each Legendre sequence controller is used for reading a code value with a preset length in a Legendre sequence from the Legendre sequence module according to a preset reading rule;

the arbiter unit receives a reading request sent by the Legendre sequence controller, performs polling scheduling on the reading request, responds to the currently scheduled reading request, reads a code value with a preset length in the Legendre sequence from the Legendre sequence array unit according to the preset reading rule, and feeds the code value back to the Legendre sequence controller;

and the Legendre sequence controller of the pilot Weil code generator receives the fed back code value to calculate and then generates a corresponding pilot component Weil chip.

Furthermore, the number of the correlator channels and the Weil code generators is 12, the number of the Legendre sequence modules is 2, and each Legendre sequence module corresponds to 6 correlator channels and the Weil code generators.

Furthermore, the Legendre sequence array unit is a ROM in which the Legendre sequence is stored.

The invention also provides a multi-way Weil code generating method for the multi-way Weil code generating device, which comprises the following steps:

s1, the Legendre sequence controllers process in parallel and respectively initiate Legendre sequence reading requests;

s21, the arbiter unit receives the read request sent by the Legendre sequence controller, and performs polling scheduling on the read request, and responds to the currently scheduled read request;

s22, reading a code value with a preset length in the Legendre sequence from the Legendre sequence array unit according to the preset reading rule, and feeding the code value back to the controller corresponding to the Legendre sequence;

s3, the Legendre sequence controller of the data Weil code generator receives the fed back code value to calculate and then generates a corresponding data component Weil chip, and the Legendre sequence controller of the pilot Weil code generator receives the fed back code value to calculate and then generates a corresponding pilot component Weil chip.

Further, the step S1 includes: the Legendre sequence controllers perform parallel processing, and when each Legendre sequence controller updates a corresponding Weil chip, whether the code value currently used by the Legendre sequence controller is calculated is judged;

and when the currently used code value is not calculated, continuously using the currently used code value to generate the corresponding data component Weil chip or pilot component Weil chip after calculation.

Further, the length of the code value obtained each time is 32 bits, and the size of the Legendre sequence is 312 × 32 bits.

Further, the step S1 is preceded by the steps of:

s01, when the Legendre sequence controllers are initialized, two Legendre sequence controllers in each Weil code generator perform parallel processing, and respectively initiate a first read request and a second read request for reading the Legendre sequence;

s02, the arbiter unit receives the first reading request and the second reading request sent by the Legendre sequence controller, performs polling scheduling on the first Legendre sequence reading request and the second Legendre sequence reading request, responds to the currently scheduled reading request, reads a code value with a preset length in the Legendre sequence from the Legendre sequence array unit according to the preset reading rule, and feeds the code value back to the corresponding Legendre sequence controller;

s03, the Legendre sequence controller records the code value obtained corresponding to the first reading request as a currently used code value Cur _ Legendre Dword, and records the code value obtained corresponding to the second reading request as a Pre-read code value Pre _ Legendre Dword;

wherein, the step S3 specifically includes: and the Legendre sequence controller of the pilot Weil code generator calculates according to the Cur _ Legendre Dword to generate a corresponding data component Weil code sheet, and the Legendre sequence controller of the pilot Weil code generator calculates according to the Cur _ Legendre Dword to generate a corresponding pilot component Weil code sheet.

Further, the step S1 further includes the steps of: and when the currently used code value is calculated, recording the current Pre _ Legendre Dword as Cur _ Legendre Dword, initiating the reading request by the Legendre sequence controller, and recording the newly received code value as a new Pre _ Legendre Dword.

Further, the method also comprises the step of reading the initialization of the configuration request of the multi-path Weil code generation device.

According to the multi-path Weil code generation method and the multi-path Weil code generation device, the Legendre sequence is cached and extracted, and two Legendre sequence modules are introduced; each Legendre sequence module can simultaneously support access requests of 24 Legendre sequence controllers of 6 channels. Using the solidified nature of the Legendre sequence, a parameter array was used instead of RAM/ROM to store the Legendre sequence. By reducing the number of caches, the total area of the caches can be reduced to 1/30 for the conventional approach, which can greatly reduce the chip area and complexity of the back-end design.

Meanwhile, the bit width of the Legendre sequence is read through the shared corresponding design of the correlator channels, so that the problem of bandwidth for reading the Legendre sequence is solved, and the problem of real-time performance for reading the Legendre sequence is solved by adding a pre-reading processing step through a Legendre sequence controller. Compared with the traditional calculation method, the scheme can greatly reduce the chip area and the complexity of rear end design, reduce the power consumption and has extremely high application value in the design of a multi-channel navigation chip.

Drawings

FIG. 1 is a block diagram of a tracking subsystem of a prior art multi-way Weil code;

FIG. 2 is a block diagram of a multi-way Weil code generator according to an embodiment of the present invention;

FIG. 3 is a flowchart illustrating a multi-way Weil code generation method applied to the multi-way Weil code generation apparatus of FIG. 2 according to an embodiment of the present invention.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Referring to fig. 2 and 3, the multi-way Weil code generating method and the multi-way Weil code generating apparatus according to an embodiment of the present invention.

The multi-way Weil code generating device 200 comprises a plurality of Weil code generators 300 corresponding to different correlator channels 301 in a one-to-one mode, and at least one Legendre sequence module 400 shared by a plurality of correlator channels 210; each Legendre sequence module 400 includes an arbiter unit 401 and a Legendre sequence array unit 402, and the Legendre sequence array unit 402 stores solidified Legendre sequences therein.

Each Weil code generator 300 comprises a data Weil code generator 301 and a pilot Weil code generator 302, wherein the data Weil code generator 301 comprises two Legendre sequence controllers 50, the pilot Weil code generator 302 comprises two Legendre sequence controllers 50, and the Legendre sequence controllers 50 are configured to read a code value of a preset length in the Legendre sequence from the Legendre sequence module 400 according to a preset reading rule.

The arbiter unit 401 receives the read request sent by the Legendre sequence controller 50, performs polling scheduling on the read request, responds to the currently scheduled read request, reads a code value with a preset length in the Legendre sequence from the Legendre sequence array unit 402 according to the preset read rule, and feeds the code value back to the Legendre sequence controller 50.

The Legendre sequence controller 50 of the data Weil code generator 401 receives the fed back code value to calculate and then generates a corresponding data component Weil chip, and the Legendre sequence controller 50 of the pilot Weil code generator 402 receives the fed back code value to calculate and then generates a corresponding pilot component Weil chip.

Specifically, in an embodiment, the number of the correlator channels 210 and the Weil code generator 300 may be 12, the number of the Legendre sequence modules 50 is 2, and each Legendre sequence module 400 corresponds to 6 correlator channels 210 and Weil code generators 300. While supporting 12 satellites, the correlator channel 210 can realize the tracking of 24 or more satellites by multiplexing. In each correlator channel 210, to support joint tracking of data pilots, a data Weil code generator 301 and a pilot Weil code generator 302 are introduced to update the chips of the data component and the pilot component, respectively.

Preferably, the Legendre sequence array unit is a ROM in which the Legendre sequence is stored.

In this embodiment, to solve the problem that the Legendre sequence has too many caches and a too large area, 48 caches in the conventional design are reduced to two caches, and two Legendre sequence modules 400 are introduced, each including one Legendre sequence. Each Legendre sequence module 400 can simultaneously support access requests for 24 Legendre sequence controllers 50 for 6 channels. Using the solidified nature of the Legendre sequence, a parameter array was used instead of RAM/ROM to store the Legendre sequence. By reducing the number of caches and the type of modification, the total area of the caches can be reduced to 1/30 for the conventional approach, which can greatly reduce the chip area and complexity of the back-end design.

In the Legendre sequence module 400, a 24-way read Legendre sequence read request is received, and the access requests are independent of each other. Therefore, a request arbiter 401 is introduced into the Legendre sequence module 400 to perform polling scheduling on the 24 paths of requests, select one path to initiate an access request to the Legendre sequence group, and return a response signal of the current path.

In the multi-way Weil code generating method of the multi-way Weil code generating device of the present embodiment, the method includes the steps of:

s1, the Legendre sequence controller 50 processes in parallel and respectively initiates Legendre sequence reading requests;

s2, the arbiter unit 401 receives the read request sent by the Legendre sequence controller 50, performs polling scheduling on the read request, responds to the currently scheduled read request, reads a code value with a preset length in the Legendre sequence from the Legendre sequence array unit 402 according to the preset read rule, and feeds back the code value to the Legendre sequence controller 50;

s3, the Legendre sequence controller 50 of the data Weil code generator 401 receives the fed back code value to calculate and generate a corresponding data component Weil chip, and the Legendre sequence controller 50 of the pilot Weil code generator 402 receives the fed back code value to calculate and generate a corresponding pilot component Weil chip.

Specifically, in an embodiment, the number of the correlator channels 210 and the Weil code generator 300 may be 12, the number of the Legendre sequence modules 400 is 2, and each Legendre sequence module 400 corresponds to 6 correlator channels 210 and Weil code generators 300. While supporting 12 satellites, the correlator channel 210 can realize the tracking of 24 or more satellites by multiplexing. In each correlator channel 210, to support joint tracking of data pilots, a data Weil code generator 301 and a pilot Weil code generator 302 are introduced to update the chips of the data component and the pilot component, respectively.

In this embodiment, the processing of the 24-way RR schedule results in the average access cycle to each Legendre sequence controller 50 becoming 24 clocks when arbitration is requested.

Specifically, in this embodiment, the length of the code value obtained each time is 32 bits, and the size of the Legendre sequence is 312 × 32 bits.

Preferably, the step S1 includes: the Legendre sequence controllers 50 perform parallel processing, and when each Legendre sequence controller 50 updates a corresponding Weil chip, whether the code value currently used by the Legendre sequence controller 50 is calculated is judged;

and when the currently used code value is not calculated, continuously using the currently used code value to generate the corresponding data component Weil chip or pilot component Weil chip after calculation.

Specifically, the step S1 is preceded by the step of:

s01, before the Legendre sequence controllers are initialized, two Legendre sequence controllers in each Weil code generator perform parallel processing, and respectively initiate a first read request and a second read request for reading the Legendre sequence;

s02, the arbiter unit 401 receives the first and second read requests sent by the Legendre sequence controller, performs polling scheduling on the first and second Legendre sequence read requests, responds to the currently scheduled read request, reads a code value with a preset length in the Legendre sequence from the Legendre sequence array unit according to the preset read rule, and feeds back the code value to the corresponding Legendre sequence controller;

s03, the Legendre sequence controller records the code value obtained corresponding to the first reading request as Cur _ Legendre Dword, and records the code value obtained corresponding to the second reading request as Pre _ Legendre Dword;

wherein, the step S3 specifically includes: and the Legendre sequence controller of the pilot Weil code generator calculates according to the Cur _ Legendre Dword to generate a corresponding data component Weil code sheet, and the Legendre sequence controller of the pilot Weil code generator calculates according to the Cur _ Legendre Dword to generate a corresponding pilot component Weil code sheet.

Further, the step S1 further includes the steps of: and when the currently used code value is calculated, recording the current Pre _ Legendre Dword as Cur _ Legendre Dword, initiating the reading request by the Legendre sequence controller, and recording the newly received code value as a new Pre _ Legendre Dword.

Further, the method also comprises the step of reading the initialization of the configuration request of the multi-path Weil code generation device.

A specific example of each step in the present embodiment is described below in a specific flow:

1) initialization: during the initialization phase of the Legendre sequence controller 50, the two Legendre sequence controllers 50 in the data Weil code generator 301 and the pilot Weil code generator 302 are divided into two parallel processing flows L1 and L2. Firstly, initiating a Weil reading configuration request, initiating a first reading request of the current Legendre Dword after all the configuration reading requests are completed, and recording a code value acquired corresponding to the first reading request as Cur _ Legendre Dword after the current reading request is completed (after the arbiter unit 401 feeds back the corresponding code value); and meanwhile, initiating a second reading request for reading the next address Legendre Dword, and after the current reading request is finished (after the arbiter unit 401 feeds back the corresponding code value), recording the code value acquired corresponding to the second reading request as Pre _ Legendre Dword. After both the L1 and L2 processes are completed, the initialization of the current Weil code generator is complete.

2) The controller, in the tracking phase: the method also comprises two parallel processing flows of L1 and L2. When the updated code chip is calculated, it is determined whether the currently used code value Cur _ Legendre Dword of the Legendre sequence controller 50 is calculated, specifically, after the code chip is updated each time, Cur _ bit of the currently used code value Cur _ Legendre Dword is accumulated, when Cur _ bit is accumulated to 32 or when Cur _ Legendre Dword is finished, it indicates that Cur _ Legendre Dword has been used up, Cur _ Legendre Dword needs to be replaced by Pre _ Legendre Dword, and meanwhile, Legendre sequence controller initiates a new read request to record the newly received code value as new Pre _ Legendre Dword. The return delay of the read request is not fixed but does not exceed 24 clock cycles, and curdword has 32 bits, and at least 32 clock cycles can be used. The problem of real-time update of the weil chips can be solved through the processing.

3) Chip updating: and calculating by using an Legendre sequence controller of the data Weil code generator according to Cur _ bit to generate a corresponding data component Weil chip after calculating according to the Cur _ Legendre Dword, and calculating by using the Cur _ Legendre sequence controller of the pilot Weil code generator according to Cur _ bit to generate a corresponding pilot component Weil chip.

According to the multi-path Weil code generation method and the multi-path Weil code generation device, the Legendre sequence is cached and extracted, and the two Legendre sequence modules 400 are introduced; each Legendre sequence module 400 can simultaneously support access requests for 24 Legendre sequence controllers 50 for 6 channels. Using the solidified nature of the Legendre sequence, a parameter array was used instead of RAM/ROM to store the Legendre sequence. By reducing the number of caches and the type of modification, the total area of the caches can be reduced to 1/30 for the conventional approach, which can greatly reduce the chip area and complexity of the back-end design.

Meanwhile, the bit width of the Legendre sequence is read by the common corresponding design of the number of the correlator channels, so that the bandwidth problem of reading the Legendre sequence is solved, and the real-time problem of reading the Legendre sequence is solved by adding the step of pre-reading processing through the Legendre sequence controller 50. Compared with the traditional calculation method, the scheme can greatly reduce the chip area and the complexity of rear end design, reduce the power consumption and has extremely high application value in the design of a multi-channel navigation chip.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.