阅读说明：本技术 半导体机台的气密性检测方法 (Airtightness detection method for semiconductor machine ) 是由 钱龙 于 2021-08-13 设计创作，主要内容包括：本申请涉及一种半导体机台的气密性检测方法。所述半导体机台的气密性检测方法包括如下步骤：形成测试芯片,所述测试芯片包括衬底以及位于所述衬底上的测试膜层,所述测试膜层中具有测试图案,所述测试膜层具有化学反应活性；获取所述测试图案的第一特征尺寸；放置所述测试芯片至半导体机台内部；于所述半导体机台内部建立真空环境；获取自所述半导体机台内部取出后的所述测试图案的第二特征尺寸；判断所述第一特征尺寸是否大于所述第二特征尺寸,若是,则确认所述半导体机台的气密性差。本申请缩短了半导体机台气密性检测的时间,降低了半导体机台气密性检测的成本,并提高了半导体机台气密性检测的准确度。(The application relates to a method for detecting the air tightness of a semiconductor machine. The method for detecting the air tightness of the semiconductor machine comprises the following steps: forming a test chip, wherein the test chip comprises a substrate and a test film layer positioned on the substrate, a test pattern is arranged in the test film layer, and the test film layer has chemical reaction activity; acquiring a first characteristic size of the test pattern; placing the test chip into the semiconductor machine; establishing a vacuum environment inside the semiconductor machine; obtaining a second characteristic dimension of the test pattern taken out from the inside of the semiconductor machine; and judging whether the first characteristic size is larger than the second characteristic size, and if so, determining that the airtightness of the semiconductor machine is poor. According to the method and the device, the time for detecting the air tightness of the semiconductor machine is shortened, the cost for detecting the air tightness of the semiconductor machine is reduced, and the accuracy for detecting the air tightness of the semiconductor machine is improved.)

1. A method for detecting the air tightness of a semiconductor machine is characterized by comprising the following steps:

forming a test chip, wherein the test chip comprises a substrate and a test film layer positioned on the substrate, a test pattern is arranged in the test film layer, and the test film layer has chemical reaction activity;

acquiring a first characteristic size of the test pattern;

placing the test chip into the semiconductor machine;

establishing a vacuum environment inside the semiconductor machine;

obtaining a second characteristic dimension of the test pattern taken out from the inside of the semiconductor machine;

and judging whether the difference value between the first characteristic dimension and the second characteristic dimension is larger than a preset value, and if so, confirming that the air tightness of the semiconductor machine is poor.

2. The method of claim 1, wherein the step of forming the test chip comprises:

providing a substrate;

forming a dielectric layer covering the surface of the substrate;

and forming the test film layer covering the surface of the dielectric layer.

3. The method of claim 2, wherein the step of forming the test film layer on the dielectric layer comprises:

depositing a reducing material on the surface of the dielectric layer to form the test film layer;

and etching the test film layer to form a groove extending along the direction of the dielectric layer pointing to the substrate, and taking the groove as the test pattern.

4. The method of claim 1, wherein the testing film is made of one or a combination of two or more of metal, metal compound, and polysilicon.

5. The method of claim 1, wherein the testing film is made of polysilicon.

6. The method of claim 1, wherein the thickness of the test film is 10nm to 50 nm.

7. The method of claim 1, wherein the number of the test chips is multiple; the specific steps of obtaining the first feature size of the test pattern include:

and acquiring a plurality of first characteristic sizes which correspond to the plurality of test chips one to one.

8. The method of claim 7, wherein the step of placing the test chip inside the semiconductor tool comprises:

and placing a plurality of test chips in a reaction chamber inside the semiconductor machine table at intervals.

9. The method as claimed in claim 8, wherein the step of placing the plurality of test chips at intervals in a reaction chamber inside the semiconductor machine comprises:

and placing a plurality of test chips in the reaction chamber in parallel along the axial direction of the reaction chamber.

10. The method of claim 8, wherein the number of the test chips is 2; the specific steps of placing a plurality of test chips in a reaction chamber inside the semiconductor machine at intervals comprise:

two test chips are respectively placed at the bottom and the top of the reaction chamber.

11. The method of claim 1, wherein the step of establishing a vacuum environment within the tool comprises:

reducing the pressure inside the semiconductor machine to be below a preset pressure;

and heating the inside of the semiconductor machine.

12. The method of claim 8, wherein the step of determining whether the difference between the first characteristic dimension and the second characteristic dimension is greater than a predetermined value comprises:

and judging that the difference value between the first characteristic dimension and the second characteristic dimension of each test chip is greater than the preset value, and if not, determining that the air tightness of the semiconductor machine is poor.

13. The method of claim 1, wherein the step of determining whether the difference between the first characteristic dimension and the second characteristic dimension is greater than a predetermined value comprises:

and judging whether the first characteristic size is larger than the second characteristic size or not and the difference value between the first characteristic size and the second characteristic size is larger than a preset value, and if so, confirming that the air tightness of the semiconductor machine is poor.

14. The method of claim 1, wherein the predetermined value is 0.1nm to 2 nm.

15. The method of claim 1, further comprising the following steps after obtaining a second feature size of the test pattern extracted from the inside of the semiconductor tool:

and removing the test film layer on the substrate.

Technical Field

The application relates to the technical field of semiconductor manufacturing, in particular to a method for detecting air tightness of a semiconductor machine.

Background

Dynamic Random Access Memory (DRAM) is a commonly used semiconductor structure in electronic devices such as computers, and is composed of a plurality of Memory cells, each of which typically includes a transistor and a capacitor. The transistor has a gate electrically connected to a word line, a source electrically connected to a bit line, and a drain electrically connected to the capacitor, wherein a word line voltage on the word line can control the transistor to be turned on and off, so that data information stored in the capacitor can be read or written into the capacitor through the bit line.

A semiconductor machine such as a furnace machine is one of important machines in the manufacturing process of semiconductor devices such as a dynamic random access memory, and is used for forming a film layer on the surface of a semiconductor structure. The airtightness of semiconductor machines such as furnace tube machine greatly affects the semiconductor process. When the gas tightness of the semiconductor machine such as a furnace machine is not good, defects are generated in the film layer deposited on the surface of the semiconductor structure. Therefore, the inspection of the gas tightness of the semiconductor equipment such as the furnace equipment is an important step for ensuring the continuous and stable semiconductor process and the yield of the semiconductor structure. However, the current method for detecting the gas tightness of semiconductor machines such as furnace tube machines has high cost, long testing time, narrow application range and low detection accuracy.

Therefore, how to improve the accuracy of the hermeticity test of the semiconductor device, reduce the cost of the hermeticity test of the semiconductor device, shorten the time for the hermeticity test of the semiconductor device, and ensure the yield of the semiconductor structure is a technical problem to be solved.

Disclosure of Invention

Some embodiments of the present application provide a method for detecting the air tightness of a semiconductor machine, which is used to solve the problem of low accuracy of the air tightness detection of the current semiconductor machine, reduce the cost of the air tightness detection of the semiconductor machine, and shorten the time of the air tightness detection of the semiconductor machine, so as to ensure the yield of semiconductor products.

According to some embodiments of the present application, a method for detecting the hermeticity of a semiconductor machine is provided, which includes the following steps:

forming a test chip, wherein the test chip comprises a substrate and a test film layer positioned on the substrate, a test pattern is arranged in the test film layer, and the test film layer has chemical reaction activity;

acquiring a first characteristic size of the test pattern;

placing the test chip into the semiconductor machine;

establishing a vacuum environment inside the semiconductor machine;

obtaining a second characteristic dimension of the test pattern taken out from the inside of the semiconductor machine;

and judging whether the difference value between the first characteristic dimension and the second characteristic dimension is larger than a preset value, and if so, confirming that the air tightness of the semiconductor machine is poor.

In some embodiments, the specific steps of forming the test chip include:

providing a substrate;

forming a dielectric layer covering the surface of the substrate;

and forming the test film layer covering the surface of the dielectric layer.

In some embodiments, the step of forming the test film layer overlying the surface of the dielectric layer comprises:

depositing a reducing material on the surface of the dielectric layer to form the test film layer;

and etching the test film layer to form a groove extending along the direction of the dielectric layer pointing to the substrate, and taking the groove as the test pattern.

In some embodiments, the material of the test film layer is any one of metal, metal compound, polysilicon, or a combination of two or more thereof.

In some embodiments, the material of the test membrane layer is polysilicon.

In some embodiments, the test film layer has a thickness of 10nm to 50 nm.

In some embodiments, the number of test chips is multiple; the specific steps of obtaining the first feature size of the test pattern include:

and acquiring a plurality of first characteristic sizes which correspond to the plurality of test chips one to one.

In some embodiments, the step of placing the test chip inside the semiconductor machine includes:

and placing a plurality of test chips in a reaction chamber inside the semiconductor machine table at intervals.

In some embodiments, the step of placing a plurality of test chips at intervals in a reaction chamber inside the semiconductor machine comprises:

and placing a plurality of test chips in the reaction chamber in parallel along the axial direction of the reaction chamber.

In some embodiments, the number of test chips is 2; the specific steps of placing a plurality of test chips in a reaction chamber inside the semiconductor machine at intervals comprise:

two test chips are respectively placed at the bottom and the top of the reaction chamber.

In some embodiments, the step of establishing a vacuum environment within the tool comprises:

reducing the pressure inside the semiconductor machine to be below a preset pressure;

and heating the inside of the semiconductor machine.

In some embodiments, the specific step of determining whether the difference between the first characteristic dimension and the second characteristic dimension is greater than a preset value includes:

and judging that the difference value between the first characteristic dimension and the second characteristic dimension of each test chip is greater than the preset value, and if not, determining that the air tightness of the semiconductor machine is poor.

In some embodiments, the specific step of determining whether the difference between the first characteristic dimension and the second characteristic dimension is greater than a preset value includes:

and judging whether the first characteristic size is larger than the second characteristic size or not and the difference value between the first characteristic size and the second characteristic size is larger than a preset value, and if so, confirming that the air tightness of the semiconductor machine is poor.

In some embodiments, the predetermined value is between 0.1nm and 2 nm.

In some embodiments, after obtaining the second feature size of the test pattern extracted from the inside of the semiconductor machine, the method further includes the following steps:

and removing the test film layer on the substrate.

According to the method for detecting the air tightness of the semiconductor machine, the test chip comprising the substrate and the test film layer is formed, the test film layer is provided with the test pattern, the change condition of the characteristic dimension of the test pattern of the test chip before and after the test chip enters the semiconductor machine is obtained, the air tightness of the semiconductor machine is judged, the method is simple to operate and low in test cost, the time for detecting the air tightness of the semiconductor machine is shortened, the cost for detecting the air tightness of the semiconductor machine is reduced, the accuracy for detecting the air tightness of the semiconductor machine is improved, and a foundation is laid for ensuring the yield of semiconductor products. The method for detecting the airtightness of the semiconductor machine, provided in some embodiments of the present application, is not limited by the type of the semiconductor machine, and has a wide application range.

Drawings

FIG. 1 is a flow chart of a method for detecting the hermeticity of a semiconductor device in an embodiment of the present application;

FIG. 2A is a schematic structural diagram of a test chip before entering a semiconductor machine according to an embodiment of the present disclosure;

FIG. 2B is a schematic structural diagram of a test chip taken out of a semiconductor machine according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a semiconductor device after a test chip is placed inside the semiconductor device in the embodiment of the present application.

Detailed Description

The following describes in detail a specific embodiment of a method for detecting the hermeticity of a semiconductor device according to the present application with reference to the accompanying drawings.

Fig. 1 is a flowchart of a method for detecting the airtightness of a semiconductor machine in an embodiment of the present application, fig. 2A is a schematic structural diagram of a test chip before entering the semiconductor machine in the embodiment of the present application, fig. 2B is a schematic structural diagram of the test chip after being taken out of the semiconductor machine in the embodiment of the present application, and fig. 3 is a schematic structural diagram of the test chip after being placed inside the semiconductor machine in the embodiment of the present application. As shown in fig. 1, fig. 2A-fig. 2B and fig. 3, the method for detecting the hermeticity of the semiconductor machine includes the following steps:

step S11, forming a test chip 30, where the test chip 30 includes a substrate 20 and a test film layer 22 on the substrate 20, the test film layer 22 has a test pattern 221 therein, and the test film layer 22 has chemical reactivity.

In this embodiment, the test film layer 22 is chemically reactive, which means that the test film layer 22 can chemically react with air, for example, can react with one or more components of air through oxidation-reduction reaction or other types of chemical reaction. The test pattern 221 may be a hole, a groove, or the like in the test film layer 22.

In some embodiments, the specific steps of forming the test chip 30 include:

providing a substrate 20;

forming a dielectric layer 21 covering the surface of the substrate 20;

and forming the testing film layer 22 covering the surface of the dielectric layer 21.

In some embodiments, the specific steps of forming the test film layer 22 covering the surface of the dielectric layer 21 include:

depositing a reducing material on the surface of the dielectric layer 21 to form the test film layer 22;

and etching the test film layer 22 to form a groove extending along the direction of the dielectric layer 21 pointing to the substrate 20, and taking the groove as the test pattern.

Specifically, the substrate 20 may be, but is not limited to, a silicon substrate, and the substrate 20 is exemplified as the silicon substrate in the present embodiment. In other examples, the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The dielectric layer 21 and the testing film layer 22 are formed outside the semiconductor machine to be tested. That is, the dielectric layer 21 and the test film layer 22 may be sequentially deposited on the surface of the substrate 20 by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. Then, the dielectric layer 21 is used as an etching stop layer, and the test film layer 22 is etched to form the trench penetrating through the test film layer 22 in a direction perpendicular to the top surface of the substrate 20 (i.e., the surface of the substrate 20 facing the test film layer 22). The material of the dielectric layer 21 may be, but is not limited to, an oxide material, such as silicon dioxide. In order to avoid over-etching and influence the accuracy of measuring the characteristic dimension of the test pattern, a high etching selection ratio should be provided between the dielectric layer 21 and the test film layer 22, for example, the etching selection ratio between the dielectric layer 21 and the test film layer 22 is greater than 3.

In the present embodiment, the formation process of the test chip 30 is completed outside the semiconductor machine to be tested, and the formation process of the test chip 30 or the test film 22 is not required to be performed inside the semiconductor machine, so that on one hand, the time for the airtightness test of the semiconductor machine is shortened, the efficiency for the airtightness test of the semiconductor machine is improved, the downtime of the semiconductor machine due to the airtightness test is reduced, and the productivity of the semiconductor machine is improved; on the other hand, the raw material gas for forming the test chip 30 or the test film layer 22 does not need to be transmitted to the inside of the semiconductor machine, so that the probability of pollution to the inside of the semiconductor machine is reduced, and the time for cleaning the semiconductor machine is saved.

In the present embodiment, the testing film layer 22 has a single-layer structure, so as to simplify the formation process of the testing chip 30. In other examples, the testing film 22 may also be a multi-layer structure, for example, the testing film 22 includes a plurality of sub-films stacked along a direction perpendicular to the top surface of the substrate 20 (i.e., the surface of the substrate 20 facing the testing film 22), so as to improve the chemical reactivity of the testing film 22, and thus improve the accuracy of the hermeticity detection of the semiconductor machine to be tested.

The reason why the testing film 22 is formed of a reducing material is that if the hermeticity of the semiconductor device is poor, external air enters the semiconductor device, and oxygen in the air easily reacts with the sidewall of the testing pattern 221 having high reducibility, so that the feature size of the testing pattern 221 is changed.

In some embodiments, the material of the test film layer 22 is any one of metal, metal compound, polysilicon, or a combination of two or more thereof. Wherein the metal compound may be, but is not limited to, a metal nitride, such as TiN.

In some embodiments, the material of the test membrane layer 22 is polysilicon.

The thickness of the testing film layer 22 should not be too large, otherwise, the small change of the characteristic dimension of the testing film layer 22 is not easy to be detected, thereby affecting the accuracy of the air tightness detection result. The thickness of the testing film layer 22 should not be too small, otherwise, the amount of the product generated after the reaction with the air entering the semiconductor machine is small, which also causes the change of the characteristic dimension of the testing film layer 22 to be small and difficult to detect, thereby also affecting the accuracy of the air tightness detection result. In some embodiments, the thickness H2 of the test film layer 22 is 10nm to 50 nm. For example, the test film layer 22 has a thickness H2 of 10nm, 15nm, 25nm, 30nm, or 40 nm. The thickness H1 of the dielectric layer 21 is 20 nm-80 nm. For example, the dielectric layer 21 has a thickness H1 of 20nm, 35nm, 50nm, 60nm, or 75 nm.

In step S12, a first feature size CD1 of the test pattern 221 is obtained.

Specifically, after the test chip 30 is formed, the first feature size CD1 of the test pattern 221 in the test chip 30 is obtained outside the semiconductor machine. The specific method for obtaining the first feature size CD1 of the test pattern 221 in the test chip 30 may be selected by one skilled in the art according to actual needs, as long as a specific value of the first feature size CD1 is obtained.

In some embodiments, the number of test chips 30 is multiple; the specific steps of obtaining the first feature size CD1 of the test pattern 221 include:

a plurality of the first feature sizes CD1 corresponding to a plurality of the test chips 30 one to one are obtained.

Specifically, by forming a plurality of test chips 30, a plurality of test chips 30 can be subsequently placed inside the semiconductor machine at the same time, so that the airtightness of a plurality of positions inside the semiconductor machine can be synchronously detected, which is helpful for further improving the airtightness detection efficiency of the semiconductor machine. The plurality of sheets in the present embodiment means two or more sheets.

Step S13, placing the test chip 30 inside the semiconductor machine.

The semiconductor machine may be, but is not limited to, a furnace machine. The present embodiment is described by taking the semiconductor machine as a furnace machine as an example. The furnace tube platform is structurally shown in fig. 3, and includes a shell 33, a furnace tube chamber 31 surrounded by the shell 33, a plurality of wafer grooves located in the furnace tube chamber 31, and a bottom cover 32 located at the bottom of the furnace tube chamber 31 and used for sealing the furnace tube chamber 31. The wafer grooves are used for bearing wafers, and the wafer grooves are arranged in parallel along the axis direction of the furnace tube chamber 31. The test chip 30 may be transferred to the furnace chamber 31 of the furnace platform by a transfer structure such as a robot arm, and placed on the wafer groove.

In some embodiments, the specific steps of placing the test chip 30 inside the semiconductor machine include:

a plurality of test chips 30 are placed in the reaction chamber inside the semiconductor machine at intervals.

In some embodiments, the specific steps of placing a plurality of test chips 30 at intervals in a reaction chamber inside the semiconductor machine include:

along the axial direction of the reaction chamber, a plurality of test chips 30 are placed in parallel in the reaction chamber.

In some embodiments, the number of test chips 30 is 2; the specific steps of placing a plurality of test chips 30 at intervals in the reaction chamber inside the semiconductor machine include:

two pieces of the test chip 30 are placed at the bottom and the top of the reaction chamber, respectively.

The semiconductor machine is a furnace machine, and the number of the test chips 30 is 2. One of the test chips 30 is placed in the wafer groove at the bottommost layer in the furnace tube chamber 31, and the other test chip 30 is placed in the wafer groove at the topmost layer in the furnace tube chamber 31 by a transmission structure such as a mechanical arm, as shown in fig. 3. This is because the bottom of the furnace chamber 31 is a passage for wafer to enter and exit, and after the wafer enters the furnace chamber 31, the bottom cover 32 closes the furnace chamber 31, so the bottom of the furnace chamber 31 is a part that is liable to affect the airtightness of the whole furnace chamber. The top of the furnace tube chamber 31 is a channel for discharging the waste gas, and is also a part which is liable to affect the air tightness of the whole furnace tube chamber. The two test chips 30 are respectively placed at the bottom and the top of the furnace tube cavity 31, so that the airtightness conditions of a plurality of positions in the furnace tube cavity 31 can be synchronously detected, and the airtightness detection efficiency of the semiconductor machine can be further improved.

Step S14, a vacuum environment is established inside the semiconductor machine.

In some embodiments, the step of establishing a vacuum environment within the tool comprises:

reducing the pressure inside the semiconductor machine to be below a preset pressure;

and heating the inside of the semiconductor machine.

For example, after the test chip 30 is placed in the furnace chamber 31, the furnace chamber 31 is closed by the bottom cover 32. Then, the furnace chamber 31 is evacuated, so that the pressure in the furnace chamber 31 is reduced below the preset pressure. Wherein the preset pressure is 1 torr. Next, the furnace tube chamber 31 is stopped from being evacuated, the furnace tube chamber 31 is heated, all the valves connected to the furnace tube chamber 31 are closed, and a preset time (for example, 1 minute to 10 minutes) is maintained.

In step S15, the second feature size CD2 of the test pattern 221 extracted from the inside of the semiconductor machine is obtained.

Step S16, determining whether a difference between the first CD1 and the second CD2 is greater than a predetermined value, and if so, determining that the hermeticity of the semiconductor apparatus is poor.

In some embodiments, the specific step of determining whether the difference between the first characteristic dimension CD1 and the second characteristic dimension CD2 is greater than a predetermined value includes:

and judging whether the difference value between the first characteristic dimension CD1 and the second characteristic dimension CD2 of each test chip 30 is larger than the preset value, and if not, confirming that the air tightness of the semiconductor machine is poor.

In some embodiments, the specific step of determining whether the difference between the first characteristic dimension CD1 and the second characteristic dimension CD2 is greater than a predetermined value includes:

determining whether the first CD1 is greater than the second CD2 and whether the difference between the first CD1 and the second CD2 is greater than a predetermined value, and if so, determining that the hermeticity of the semiconductor apparatus is poor.

In some embodiments, the predetermined value is between 0.1nm and 2 nm. For example, the predetermined value is 0.1nm, 0.5nm, 1nm, or 1.5 nm.

The following description will be given by taking the material of the testing film 22 as polysilicon and the semiconductor machine as a furnace machine. When the furnace platen has good air tightness, the step of establishing the vacuum environment inside the furnace platen is equivalent to heating the test film layer 22, and the feature size of the test pattern 221 is not changed or slightly changed due to the removal of impurities in the polysilicon or the difference in measurement precision, for example, the difference between the first feature size CD1 and the second feature size CD2 is less than 0.1 nm.

When the furnace platen has poor air tightness, in the process of establishing a vacuum environment inside the furnace platen and heating the furnace platen, the oxygen entering the furnace platen reacts with the test pattern 221 in the test film layer 22 as follows:

Si+O₂＝SiO₂

SiO₂the generation of (1) may cause the feature size of the test pattern 221 to be reduced, for example, the difference between the first feature size CD1 and the second feature size CD2 is greater than a predetermined value.

And if the gas tightness of the semiconductor machine is determined to be poor, maintaining the semiconductor machine after performing gas purging on the semiconductor machine. After the maintenance, the airtightness of the semiconductor machine is detected again by means of resistance detection until the first characteristic dimension CD1 is larger than the second characteristic dimension CD2, and the difference between the first characteristic dimension CD1 and the second characteristic dimension CD2 is larger than the preset value.

In some embodiments, after obtaining the second feature size CD2 of the test pattern 221 extracted from the inside of the semiconductor machine, the method further comprises the following steps:

the test film layer 22 on the substrate 20 is removed.

Specifically, after the hermeticity test of the semiconductor machine is completed, the test film layer 22 on the substrate 20 may be removed by wet cleaning, so as to realize the recycling of the substrate 20, thereby further reducing the hermeticity test cost of the semiconductor machine. For example, when the material of the test film layer 22 is polysilicon, after the hermetic sealing test of the semiconductor machine is completed, an alkaline solution (e.g., an ammonia solution) may be used to remove the test film layer 22 on the substrate 20.

In some embodiments of the present invention, the method for detecting the air tightness of the semiconductor machine, which is provided by the embodiments of the present invention, includes forming a test chip including a substrate and a test film layer, where the test film layer has a test pattern, and obtaining a change condition of a characteristic dimension of the test pattern before and after the test chip enters the semiconductor machine, to determine whether the air tightness of the semiconductor machine is good or bad, and the method is simple in operation and low in test cost, and shortens the time for detecting the air tightness of the semiconductor machine, reduces the cost for detecting the air tightness of the semiconductor machine, improves the accuracy for detecting the air tightness of the semiconductor machine, and lays a foundation for ensuring the yield of semiconductor products. The method for detecting the airtightness of the semiconductor machine, provided in some embodiments of the present application, is not limited by the type of the semiconductor machine, and has a wide application range.

The foregoing is only a preferred embodiment of the present application and it should be noted that, for a person skilled in the art, several modifications and refinements can be made without departing from the principle of the present application, and these modifications and refinements should also be regarded as the protection scope of the present application.