Gallium nitride hot electron transistor device with upper collector and preparation method thereof

文档序号：345109 发布日期：2021-12-03 浏览：29次中文

阅读说明：本技术 一种集电极上置的氮化镓热电子晶体管器件及其制备方法 (Gallium nitride hot electron transistor device with upper collector and preparation method thereof ) 是由祝杰杰马晓华赵旭张颖聪杨凌郝跃于 2021-07-29 设计创作，主要内容包括：本发明涉及一种集电极上置的氮化镓热电子晶体管器件及其制备方法,该氮化镓热电子晶体管器件包括：GaN自支撑衬底、n+GaN层、Al-(x)Ga-(1-x)N发射区、发射极、GaN基区、Al-(y)Ga-(1-y)N集电区、基极、n+GaN帽层、集电极和钝化层。该氮化镓热电子晶体管器件具有集电极上置结构,其集电区电容小,可以降低寄生电容效应,有利于器件在高频电路中的应用。(The invention relates to a gallium nitride hot electron transistor device with an upper collector and a preparation method thereof, wherein the gallium nitride hot electron transistor device comprises: GaN self-supporting substrate, n + GaN layer, Al x Ga 1‑x N emitter region, emitter electrode, GaN base region, and Al y Ga 1‑y The N collector region, the base electrode, the N + GaN cap layer, the collector electrode and the passivation layer. The gallium nitride hot electron transistor device has a collector electrode overhead structure, and the collector region of the gallium nitride hot electron transistor device has small capacitance, so that the parasitic capacitance effect can be reduced, and the gallium nitride hot electron transistor device is favorable for application of the device in a high-frequency circuit.)

1. A collector-top gallium nitride hot electron transistor device, comprising: GaN self-supporting substrate (1), n + GaN layer (2), Al_xGa_1-xN emitter region (3), emitter (4), GaN base region (5), Al_yGa_1-yAn N collector region (6), a base electrode (7), an N + GaN cap layer (8), a collector electrode (9) and a passivation layer (10), wherein,

the GaN self-supporting substrate (1), the n + GaN layer (2), and the Al_xGa_1-xN emitter region (3), GaN base region (5), and Al_yGa_1-yThe N collector region (6) and the N + GaN cap layer (8) are sequentially stacked, the GaN self-supporting substrate (1) and the N + GaN layer (2) form a first step, and the Al layer is formed_xGa_1-xThe N emitter region (3) and the GaN base region (5) form a second step, and the Al_yGa_1-yThe N collector region (6) and the N + GaN cap layer (8) form a third step;

the passivation layer (10) is positioned on the upper surface of the n + GaN layer (2) and Al_xGa_1-xThe side surface of the N emitter region (3), the side surface and the upper surface of the GaN base region (5), and the Al_yGa_1-yThe side surface of the N collector region (6) and the side surface and the upper surface of the N + GaN cap layer (8);

the lower end of the emitter (4) is positioned in the passivation layer (10) and is in contact with the n + GaN layer (2), and the upper end of the emitter is positioned on the surface of the passivation layer (10) on the first step and surrounds the passivation layer (10) on the side face of the second step;

the lower end of the base electrode (7) is positioned in the passivation layer (10) and is in contact with the GaN base region (5), and the upper end of the base electrode is positioned on the surface of the passivation layer (10) on the second step and surrounds the passivation layer (10) on the side face of the third step;

the lower end of the collector (9) is positioned in the passivation layer (10) and is in contact with the n + GaN cap layer (8), and the upper end of the collector is positioned on the surface of the passivation layer (10) on the third step.

2. The GaN thermionic transistor device as claimed in claim 1, wherein the GaN free-standing substrate (1) has an n-type doping concentration of 1e¹⁸cm^-3～8e¹⁸cm^-3The thickness is 200-400 μm.

3. The GaN thermionic transistor device as claimed in claim 1, wherein the n + GaN layer (2) has an n-type doping concentration of 3e¹⁸cm^-3～8e¹⁸cm^-3And the thickness is 15 nm-40 nm.

4. The overhead collector gallium nitride hot electron transistor device of claim 1, wherein the Al is_xGa_1-xN-type doping concentration 1e of N emitter region (3)¹⁸cm^-3～1e¹⁹cm^-3The thickness is 25nm to 40nm, and the Al component x is 25 percent to 40 percent.

5. The GaN thermionic transistor device with top-collector according to claim 1, wherein the GaN base region (5) has an n-type doping concentration of 8e¹⁸cm^-3～1.5e¹⁹cm^-3And the thickness is 8 nm-12 nm.

6. The top-collector gallium nitride hot electron transistor device according to claim 1,the Al is_yGa_1-yN-type doping concentration 5e of N collector region (6)¹⁷cm^-3～5e¹⁸cm^-3The thickness is 40 nm-60 nm, and the Al component y is 5% -10%.

7. The collector-top GaN thermionic transistor device according to claim 1, wherein the lower end of the base (7) is located in the passivation layer (10) and embedded in the GaN base region (5).

8. The device according to claim 1, wherein the n + GaN cap layer (8) has an n-type doping concentration of 5e¹⁸cm^-3～1e¹⁹cm^-3And the thickness is 10 nm-20 nm.

9. A method for preparing a gallium nitride hot electron transistor device with an upper collector is characterized by comprising the following steps:

s1, etching the n + GaN cap layer (8) at the periphery of the epitaxial substrate, and Al_yGa_1-yAn N collector region (6), a GaN base region (5) and Al_xGa_1-xAn N emitter region (3) forming an emitter region (41), wherein the epitaxial substrate comprises a GaN self-supporting substrate (1), an N + GaN layer (2), and Al, which are sequentially stacked_xGa_1-xN emitter region (3), GaN base region (5), Al_yGa_1-yAn N collector region (6), an N + GaN cap layer (8), the emitter region (41) being located on the N + GaN layer (2);

s2, etching the n + GaN cap layer (8) and the Al_yGa_1-yAn N collector region (6) forming a base region (71) and a collector region (81), wherein the base region (71) is located on the GaN base region (5) and the collector region (81) is located on the N + GaN cap layer (8);

s3, the Al being on the upper surface of the n + GaN layer (2)_xGa_1-xThe side surface of the N emitter region (3), the side surface and the upper surface of the GaN base region (5), and the Al_yGa_1-yA passivation layer (10) is grown on the side surface of the N collector region (6) and the side surface and the upper surface of the N + GaN cap layer (8);

s4, etching the passivation layer (10) and the n + GaN layer (2) of the emitter region (41), the passivation layer (10) and the GaN base region (5) of the base region (71), the passivation layer (10) and the n + GaN cap layer (8) of the collector region (81), forming an emitter opening (43), a base opening (73) and a collector opening (83);

s5, evaporating metal in the emitter opening (43), in the base opening (73), in the collector opening (81) and on the passivation layer (10) to form an emitter (4), a base (7) and a collector (9).

10. The method of claim 9, wherein step S4 comprises:

s41, simultaneously etching the passivation layer (10) of the emitter region (41), the passivation layer (10) of the base region (71) and the passivation layer (10) of the n + GaN cap layer (8) to form a first opening (42), a second opening (72) and a third opening (82) penetrating through the passivation layer (10);

s42, over-etching the n + GaN layer (2) in the first opening (42), the GaN base region (5) in the second opening (72) and the n + GaN cap layer (8) in the third opening (82) simultaneously to form an emitter opening (43), a base opening (73) and a collector opening (83), wherein the over-etching depth is 0-5 nm.

Technical Field

The invention belongs to the technical field of semiconductor devices, and particularly relates to a gallium nitride thermionic transistor device with an upper collector and a preparation method thereof.

Background

Gallium nitride is used as a third-generation wide-band-gap semiconductor material, has the excellent characteristics of large forbidden band width, high saturation velocity, high electron mobility, high-concentration Two-dimensional electron gas (2 DEG for short) generated by AlGaN/GaN heterojunction interface due to polarization, and the like, and is very suitable for being applied to the field of manufacturing high-frequency high-power devices.

Currently, in the field of nitride High-frequency High-power devices, a High Electron Mobility Transistor (HEMT) device with a transverse structure is mainly used, and the HEMT device has High carrier mobility and current density because 2DEG generated by an AlGaN/GaN heterojunction interface polarization effect is used as a carrier channel. However, with the further improvement of the performance requirements of the devices, the lateral structure HEMT device mainly faces the problems that the frequency characteristics are limited by the electron saturation speed and the integration degree is limited by the lateral dimension, and the vertical structure device does not need to consider the horizontal direction when the size is reduced, so that the integration degree can be greatly improved, and the vertical structure device has a larger current per unit area compared with the lateral structure device, which makes the vertical structure device begin to be concerned.

Heterojunction bipolar transistor (HBT for short) devices are the mainstream application in the field of nitride-based vertical structure devices at present, and HBTs have the advantages of high linearity, large current, high power density and the like compared with lateral devices such as HEMTs and the like, but HBT devices are used as minority carrier devices and have the problems of low base P-type conductivity, large base resistance caused by high acceptor activation energy and the like, so that further development of HBTs in the high-frequency field is limited.

On the premise that the HEMT device and the HBT device have the above disadvantages, a Thermo electronic transistor device (HET for short) has certain advantages as a vertical structure unipolar high-frequency power device, and the structure composition of the HET device is similar to that of the HBT device, but the HET device is a multi-sub device, and compared with the HBT device, the HBT device does not have a minority carrier storage effect, so that high-speed application is facilitated, and in addition, the N-type base region can enable the thickness of the base region to be only about a few nanometers, so that electrons can be transported in a near-ballistic channel.

In the HBT device, the HBT device can be divided into two types according to different capacitances of a collector region of the device; one type is a large collector area capacitor device that is structurally laid out with the emitter on top and the area minimized. The other is to invert the structure so that the collector is on top, so that a smaller collector capacitance can be achieved, and the reason for the inversion of the structure is that the existence of large collector capacitance can cause a parasitic oscillation phenomenon, thereby having a negative effect on high-frequency application of the device.

As a high-frequency device with a structure similar to that of an HBT device, an HET device with a small collector capacitance and a collector-overlying structure is also a research topic of interest, and related research on the HET device has been slow due to the quality problem of epitaxial materials for a long time in the past, but as the current nitride epitaxial material preparation technology is continuously mature, the HET device will certainly gain more extensive attention in the future high-frequency field. Therefore, designing a HET device with a small collector region with a collector-overlying structure is a problem to be solved urgently.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a gan thermionic transistor device with a top-mounted collector and a method for fabricating the same. The technical problem to be solved by the invention is realized by the following technical scheme:

the embodiment of the invention provides a gallium nitride hot electron transistor device with an upper collector, which comprises: GaN self-supporting substrate, n + GaN layer, Al_xGa_1-xN emitter region, emitter electrode, GaN base region, and Al_yGa_1-yAn N collector region, a base electrode, an N + GaN cap layer, a collector electrode and a passivation layer,

the GaN self-supporting substrate, the n + GaN layer, and the Al_xGa_1-xN emitter region, the GaN base region, and the Al_yGa_1-yThe N collector region and the N + GaN cap layer are sequentially stacked, the GaN self-supporting substrate and the N + GaN layer form a first step, and the Al layer_xGa_1-xThe N emitter region and the GaN base region form a second step, and the Al is_yGa_1-yThe N collector region and the N + GaN cap layer form a third step;

the passivation layer is positioned on the upper surface of the n + GaN layer and Al_xGa_1-xSide surface of N emitter region, side surface and upper surface of GaN base region, and Al_yGa_1-yThe side surface of the N collector region, the side surface of the N + GaN cap layer and the upper surface of the N + GaN cap layer are respectively provided with a plurality of N collector regions;

the lower end of the emitter is located in the passivation layer and is in contact with the n + GaN layer, and the upper end of the emitter is located on the surface of the passivation layer on the first step and surrounds the passivation layer on the side face of the second step;

the lower end of the base electrode is positioned in the passivation layer and is in contact with the GaN base region, and the upper end of the base electrode is positioned on the surface of the passivation layer on the second step and surrounds the passivation layer on the side face of the third step;

the lower end of the collector electrode is located in the passivation layer and is in contact with the n + GaN cap layer, and the upper end of the collector electrode is located on the surface of the passivation layer on the third step.

In one embodiment of the invention, the GaN free-standing substrate has an n-type doping concentration of 1e¹⁸cm^-3～8e¹⁸cm^-3The thickness is 200-400 μm.

In one embodiment of the present invention, the n-type doping concentration of the n + GaN layer is 3e¹⁸cm^-3～8e¹⁸cm^-3And the thickness is 15 nm-40 nm.

In one embodiment of the present invention, the Al_xGa_1-xN-type doping concentration 1e of N emitter region¹⁸cm^-3～1e¹⁹cm^-3The thickness is 25 nm-40 nm, and the Al component is 25% -40%.

In one embodiment of the invention, the n-type doping concentration 8e of the GaN base region¹⁸cm^-3～1.5e¹⁹cm^-3And the thickness is 8 nm-12 nm.

In one embodiment of the present invention, the Al_yGa_1-yN-type doping concentration of N collector region 5e¹⁷cm^-3～5e¹⁸cm^-3Thickness of 40nm to 60nmnm, 5-10% of Al component y.

In one embodiment of the present invention, the lower end of the base is located in the passivation layer and embedded in the GaN base region.

In one embodiment of the present invention, the n-type doping concentration of the n + GaN cap layer is 5e¹⁸cm^-3～1e¹⁹cm^-3And the thickness is 10 nm-20 nm.

Another embodiment of the present invention provides a method for fabricating a gan thermionic transistor device with a top-mounted collector, comprising:

s1, etching the n + GaN cap layer on the periphery of the epitaxial substrate, and Al_yGa_1-yN collector region, GaN base region and Al_xGa_1-xAn N emitter region forming an emitter region, wherein the epitaxial substrate comprises a GaN self-supporting substrate, an N + GaN layer and Al which are sequentially laminated_xGa_1-xN emitter region, GaN base region, and Al_yGa_1-yThe emitter region is positioned on the N + GaN layer;

s2, etching the n + GaN cap layer and the Al_yGa_1-yThe N collector region forms a base region and a collector region, wherein the base region is positioned on the GaN base region, and the collector region is positioned on the N + GaN cap layer;

s3, the Al is arranged on the upper surface of the n + GaN layer_xGa_1-xSide surface of N emitter region, side surface and upper surface of GaN base region, and Al_yGa_1-yA passivation layer is grown on the side surface of the N collector region, the side surface of the N + GaN cap layer and the upper surface of the N + GaN cap layer;

s4, etching the passivation layer and the n + GaN layer of the emitter region, the passivation layer and the GaN base region of the base region, and the passivation layer and the n + GaN cap layer of the collector region to form an emitter opening, a base opening and a collector opening;

s5, evaporating metal in the emitter opening, the base opening, the collector opening and the passivation layer to form an emitter, a base and a collector.

In one embodiment of the present invention, step S4 includes:

s41, simultaneously etching the passivation layer of the emitter region, the passivation layer of the base region and the passivation layer of the n + GaN cap layer to form a first opening, a second opening and a third opening which penetrate through the passivation layer;

s42, performing over-etching on the n + GaN layer in the first opening, the GaN base region in the second opening and the n + GaN cap layer in the third opening simultaneously to form an emitter opening, a base opening and a collector opening, wherein the over-etching depth is 0-5 nm.

Compared with the prior art, the invention has the beneficial effects that:

the gallium nitride thermionic transistor device has a collector electrode overhead structure, and the collector region of the gallium nitride thermionic transistor device has small capacitance, so that the parasitic capacitance effect can be reduced, and the gallium nitride thermionic transistor device is favorable for application in a high-frequency circuit.

Drawings

Fig. 1 is a schematic structural diagram of a gan thermionic transistor device with a top-mounted collector according to an embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating a basic principle of a GaN hot electron transistor device with a top-mounted collector according to an embodiment of the present invention;

fig. 3 is a schematic flow chart of a method for fabricating a gan thermionic transistor device with a top-collector in accordance with an embodiment of the present invention;

fig. 4 a-4 i are schematic process diagrams of a method for manufacturing a gan hot electron transistor device with a top-mounted collector according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

Referring to fig. 1, fig. 1 is a schematic structural diagram of a gan hot electron transistor device with a top-mounted collector according to an embodiment of the present invention.

The gallium nitride thermal electron crystalThe tube device is of a vertical structure and comprises a GaN self-supporting substrate 1, an n + GaN layer 2 and Al_xGa_1-xN emitter region 3, emitter 4, GaN base region 5, Al_yGa_1-yAn N collector region 6, a base electrode 7, an N + GaN cap layer 8, a collector electrode 9 and a passivation layer 10.

Wherein, GaN self-supporting substrate 1, n + GaN layer 2, Al_xGa_1-xN emitter region 3, GaN base region 5, Al_yGa_1-yThe N collector region 6 and the N + GaN cap layer 8 are sequentially laminated, the GaN self-supporting substrate 1 and the N + GaN layer 2 form a first step, and Al is arranged on the first step_xGa_1-xThe N emitter region 3 and the GaN base region 5 form a second step, Al_yGa_1-yThe N collector region 6 and the N + GaN cap layer 8 form a third step; a passivation layer 10 on the upper surface of the n + GaN layer 2 and Al_xGa_1-xSide surface of N emitter region 3, side surface and upper surface of GaN base region 5, and Al_yGa_1-yThe side surface of the N collector region 6 and the side surface and the upper surface of the N + GaN cap layer 8; the lower end of the emitter 4 is positioned in the passivation layer 10 and is in contact with the n + GaN layer 2, and the upper end of the emitter is positioned on the surface of the passivation layer 10 on the first step and surrounds the passivation layer 10; the lower end of the base electrode 7 is positioned in the passivation layer 10 and is in contact with the GaN base region 5, and the upper end of the base electrode 7 is positioned on the surface of the passivation layer 10 on the second step and surrounds the passivation layer 10 on the side face of the third step; the lower end of the collector 9 is located in the passivation layer 10 and contacts the n + GaN cap layer 8, and the upper end is located on the surface of the passivation layer 10 on the third step.

Specifically, the width of the GaN self-supporting substrate 1 is equal to that of the n + GaN layer 2, so as to form a first step; al (Al)_xGa_1-xThe N emitter region 3 and the GaN base region 5 are equal in width to form a second step; al (Al)_yGa_1-yThe widths of the N collector region 6 and the N + GaN cap layer 8 are equal to form a third step; the first step on the n + GaN layer 2 serves as an emitter region, the second step on the GaN base region 5 serves as a base region, and the third step on the n + GaN cap layer 8 serves as a collector region. The passivation layer 10 covers the upper surface and the side surfaces of the step-shaped structure, i.e. the passivation layer is positioned on the upper surface of the n + GaN layer 2 and is Al_xGa_1-xSide surface of N emitter region 3, side surface and upper surface of GaN base region 5, and Al_yGa_1-yThe side surfaces of the N collector region 6 and the side surfaces and the upper surface of the N + GaN cap layer 8.

Further, a first opening is penetrated through the passivation layer 10 on the emitter region, and the lower end of the emitter 4 is disposed in the first opening, so that the lower end of the emitter 4 is in contact with the n + GaN layer 2; the upper end of the emitter 4 is positioned on the surface of the passivation layer 10 on the first step and contacts the passivation layer 10 at the side of the second step, thereby forming a structure surrounding the passivation layer 10. A second opening penetrates through the passivation layer 10 on the base region, and the lower end of the base 7 is arranged in the second opening, so that the lower end of the base 7 is in contact with the GaN base region 5; the upper end of the base electrode 7 is positioned on the passivation layer 10 on the second step and is in contact with the passivation layer 10 at the side of the third step, thereby forming a structure surrounding the passivation layer 10. A third opening penetrates through the passivation layer 10 on the collector region, and the lower end of the collector 9 is arranged in the third opening, so that the lower end of the collector 9 is positioned in the passivation layer 10 and is in contact with the n + GaN cap layer 8; the upper end of the collector electrode 9 is disposed on the passivation layer 10 on the third step.

Furthermore, the lower end of the emitter 4 may be located on the surface of the n + GaN layer 2, or may be embedded in the n + GaN layer 2; the lower end of the base 7 can be positioned on the surface of the GaN base region 5, and can also be embedded in the GaN base region 5; the lower end of the collector 9 may be located on the surface of the n + GaN cap layer 8, or may be embedded in the n + GaN cap layer 8. Preferably, the lower end of the base electrode 7 is embedded in the GaN base region 5, so that a good current control effect can be realized; meanwhile, because the base electrode 7, the emitter electrode 4 and the collector electrode 9 are simultaneously prepared during preparation, the lower end of the emitter electrode 4 is also embedded into the n + GaN layer 2 and the lower end of the collector electrode 9 is also embedded into the n + GaN cap layer 8 for the sake of simple process.

Specifically, the GaN free-standing substrate 1 has an n-type doping concentration of 1e¹⁸cm^-3～8e¹⁸cm^-3The thickness is 200-400 μm. n-type doping concentration 3e of n + GaN layer 2¹⁸cm^-3～8e¹⁸cm^-3And the thickness is 15 nm-40 nm. Al (Al)_xGa_1-xN-type doping concentration 1e of N emitter region 3¹⁸cm^-3～1e¹⁹cm^-3The thickness is 25 nm-40 nm, and the Al component is 25% -40%. N-type doping concentration 8e of GaN base region 5¹⁸cm^-3～1.5e¹⁹cm^-3And the thickness is 8 nm-12 nm. Al (Al)_yGa_1-yN-type doping concentration 5e of N collector region 6¹⁷cm^-3～5e¹⁸cm^-3The thickness is 40 nm-60 nm, and the Al component y is 5% -10%. n-type doping concentration 5e of n + GaN cap layer 8¹⁸cm^-3～1e¹⁹cm^-3And the thickness is 10 nm-20 nm.

The device of this embodiment has two important considerations in design:

1. the base region must be controlled to a thickness of several nanometers to prevent elastic scattering and relaxation of hot electrons during transport, which reduces transport efficiency. Therefore, in this embodiment, the thickness of GaN base region 5 is set to 8nm to 12 nm.

2. Base-collector barrier (phi B-C)>>25meV prevents leakage from base electrons entering the collector region, while the emitter-base barrier (Φ E-B) is larger than the base-collector barrier (Φ B-C) in order to allow injected electrons with higher energy to relax to the base fermi level without being reflected by the B-C barrier. Therefore, the present embodiment sets Al according to this principle_xGa_1-xN emitter region 3, GaN base region 5, and Al_yGa_1-yThe relevant parameters of the N collector region 6.

Referring to fig. 2, fig. 2 is a schematic diagram illustrating a basic principle of a gan hot electron transistor device with a top collector according to an embodiment of the present invention, wherein E is an emitter, B is a base, and C is a collector. Hot Electron Transistors (HETs) are devices consisting of three electrodes, an emitter E, a base B and a collector C, which are separated by two barriers as shown in fig. 2. The working principle is as follows: when the emitter-base region is forward biased, electrons are injected into the base and gain kinetic energy; as the electron passes through the base region, part of the energy is lost through the inelastic scattering process; when the energy loss is small, electrons can overcome the base-collector barrier to reach the collector, otherwise they will relax to the bottom of the base and be collected by the base; the injected electrons can almost pass through the base region like a trajectory along with the reduction of the thickness of the base electrode in the base region transition process, so that the device has high working speed; the collector acts as an energy filter at the collector edge of the base, which allows hot electrons (high-energy electrons) to pass through, but blocks cold electrons (low-energy electrons), creating an imbalance over a large range, so that electrons scattered in the base are not high enough in energy to pass through the collector and be reflected back, which eventually become part of the group of cold electrons in the base and contribute to the base current. Electrons at the edge of the base collector have sufficient energy to cause them to form a collector current through the collector.

In this embodiment, the HET belongs to the multi-and single-pole type devices, and since the electron mobility is higher than the corresponding hole mobility in most semiconductor systems, the Rb (base resistance) of the HET device is low, and the low Rb value helps to reduce the RC delay associated with the charging of the base-emitter capacitance, thereby increasing the associated frequency characteristic f of the operating transistor_t/f_max。

In the embodiment, the substrate is a GaN self-supporting substrate, so that the problem of high-density dislocation in the material caused by a heterogeneous substrate is greatly reduced, and the carrier mobility and the thermal conductivity of a device are ensured; a passivation layer is introduced into the device and can be used as a field plate medium at the same time, so that the breakdown voltage of the device is improved; in addition, the collector electrode upper structure is adopted, the capacitance of a collector region is small, the parasitic capacitance effect can be reduced, and the application of the device in a high-frequency circuit is facilitated.

In summary, the gan thermionic transistor device of the present embodiment has the advantages of large collector current, high breakdown field strength, low defect density of the epitaxial material, and the like, and improves the current gain, common emitter output characteristics, and the like of the conventional thermionic transistor, so that the gan thermionic transistor device can perform better working performance.

Example two

On the basis of the first embodiment, please refer to fig. 3 and fig. 4a to 4i, fig. 3 is a schematic flow chart of a method for manufacturing a gan hot electron transistor device with an upper collector according to an embodiment of the present invention, and fig. 4a to 4i are schematic process diagrams of a method for manufacturing a gan hot electron transistor device with an upper collector according to an embodiment of the present invention.

In this embodiment, a GaN self-supporting substrate 1, an n + GaN layer 2 and a are selected and stacked in sequence from bottom to topl_xGa_1-xN emitter region 3, GaN base region 5, Al_yGa_1-yThe structure of the N collector region 6 and the N + GaN cap layer 8 serves as an epitaxial substrate, as shown in fig. 4 a.

Specifically, the preparation method of the gallium nitride hot electron transistor device comprises the following steps:

s1, manufacturing the electrical isolation of the active region of the device, wherein the specific manufacturing method comprises the following steps:

s11, lithography of electrically isolated regions of the active region on the n + GaN cap layer 8.

Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, coating photoresist and spin coating photoresist on the surface of the n + GaN cap layer 8 at a spin coating speed of 3500 rpm, and baking the sample on a hot plate at 90 ℃ for 1 min; and finally, putting the sample into a photoetching machine to expose the photoresist in the electric isolation area, putting the exposed sample into a developing solution to remove the photoresist in the electric isolation area, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist.

S12, etching the n + GaN cap layer 8 and the Al of the electric isolation region in sequence by utilizing an inductively coupled plasma etching process ICP_yGa_1-yN collector region 6, GaN base region 5 and Al_xGa_1-xN emitter region 3 and N + GaN layer 2, forming an electrical isolation 11 of the active region of the device, as shown in fig. 4 b.

Firstly, etching the n + GaN cap layer 8 and Al of the electric isolation region in sequence by utilizing an ICP (inductively coupled plasma) process_yGa_1-yN collector region 6, GaN base region 5 and Al_xGa_1-xAn N emitter region 3 and an N + GaN layer 2 to realize mesa isolation of the active region; then, the sample is sequentially put into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning so as to remove the photoresist outside the electrical isolation region, and then the sample is rinsed with ultrapure water and dried by nitrogen gas to form the electrical isolation 11 of the active region of the device.

S2, etching the n + GaN cap layer 8 at the periphery of the epitaxial substrate, and Al_yGa_1-yN collector region 6, GaN base region 5 and Al_xGa_1-xN emitter region 3, forming emitter region 41.

S21, carrying out photoetching on the target pattern area on the n + GaN cap layer 8.

Firstly, placing an epitaxial substrate on a hot plate at 200 ℃ for baking for 5 min; then, glue coating and spin coating of the stripping glue are carried out on the n + GaN cap layer 8, the spin coating thickness is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; and finally, putting the sample subjected to glue coating and spin coating into a photoetching machine to expose the coated surface, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue, and then carrying out ultra-pure water washing and nitrogen purging on the sample to form a target pattern area.

S22, etching the n + GaN cap layer 8 of the target pattern area, and Al_yGa_1-yN collector region 6, GaN base region 5 and Al_xGa_1-xAn N emitter region 3 forming an emitter region 41, wherein the emitter region 41 is located on the N + GaN layer 2, the N + GaN cap layer 8, and Al_yGa_1-yN collector region 6, GaN base region 5 and Al_xGa_1-xThe N emitter region 3 forms a mesa around which the emitter region 41 surrounds, as is shown in fig. 4 c.

Firstly, etching the n + GaN cap layer 8 and Al of the target pattern region in sequence by utilizing an ICP (inductively coupled plasma) process_yGa_1-yN collector region 6, GaN base region 5 and Al_xGa_1-xAn N emission region 3; specifically, the etching depth is 83nm to 132 nm. Then, the sample is sequentially placed into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the etching region, and the sample is rinsed with ultrapure water and dried with nitrogen gas to form the emitter region 41.

S3, etching the n + GaN cap layer 8 and Al_yGa_1-yAnd an N collector region 6 forming a base region 71 and a collector region 81.

S31, photoetching is carried out on the target pattern area on the periphery of the n + GaN cap layer 8.

S32, etching the n + GaN cap layer 8 and Al of the target pattern area by the ICP process_yGa_1-yAn N collector region 6 forming a base region 71 and a collector region 81, wherein the base region 71 is located on the GaN base region 5, the collector region 81 is located on the N + GaN cap layer 8, and the base region 71 surrounds the N + GaN cap layer 8 and the Al_yGa_1-yN collector region 6, as shown in fig. 4 d.

Firstly, etching the n + GaN cap layer 8 of the base region and Al in sequence by utilizing an ICP (inductively coupled plasma) process_yGa_1-yThe total etching depth of the N collector region 6 is 50 nm-80 nm; then, the sample is sequentially placed into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist and the stripping glue outside the etching area, the sample is washed by ultrapure water and dried by nitrogen gas, and the base region 71 and the collector region 81 are formed.

S4, on the upper surface of the n + GaN layer 2, Al_xGa_1-xSide surface of N emitter region 3, side surface and upper surface of GaN base region 5, and Al_yGa_1-yAnd a passivation layer 10 is grown on the side surface of the N collector region 6 and the side surface and the upper surface of the N + GaN cap layer 8.

And S41, cleaning the surface of the device after the base region etching is finished.

Firstly, putting a sample into an acetone solution for ultrasonic cleaning for 3mim, wherein the ultrasonic intensity is 3.0; then, putting the sample into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min; then, the sample is sequentially placed into an acetone solution and an ethanol solution for ultrasonic cleaning for 3min, and the ultrasonic intensity is 3.0; finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.

S42, forming Al on the upper surface (i.e. the emitter region 41) of the n + GaN layer 2 by using ALD or PECVD process_xGa_1-xLateral surface of N emitter region 3, GaN base region 5Side and top surfaces (i.e., base region 71), Al_yGa_1-yThe side faces of the N collector region 6 and the side faces and upper surface (i.e., collector region) of the N + GaN cap layer 8 are deposited to form a passivation layer 10, as shown in fig. 4 e. Specifically, the material of the passivation layer 10 includes SiN or Al₂O₃And the thickness is 30 nm.

S5, the passivation layer 10 and n + GaN layer 2 of emitter region 41, the passivation layer 10 and GaN base region 5 of base region 71, and the passivation layer 10 and n + GaN cap layer 8 of collector region 81 are etched to form emitter opening 43, base opening 73, and collector opening 83.

S51, lithographically printing an emitter opening region on the surface of the passivation layer 10 on the emitter region 41, a base opening region on the surface of the passivation layer 10 on the base region 71, and a collector opening region on the surface of the passivation layer 10 on the collector region 81.

Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, coating and spin coating the photoresist at a spin coating speed of 3500 rpm/mim, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample into a photoetching machine to expose the photoresist in the emitter electrode open hole region, the base electrode open hole region and the collector electrode open hole region; finally, the exposed sample is placed into a developing solution to remove the photoresist in the interconnected opening area, and the photoresist is subjected to ultra-pure water washing and nitrogen blow-drying.

S52, the passivation layer 10 of the emitter region 41, the passivation layer 10 of the base region 71 and the passivation layer 10 of the n + GaN cap layer 8 are simultaneously etched to form the first opening 42, the second opening 72 and the third opening 82 penetrating through the passivation layer 10, as shown in fig. 4 f.

By utilizing ICP etching process, the reaction gas is CF₄And O₂Under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, the passivation layer 10 of the emitter opening region, the base opening region and the collector opening region is etched away simultaneously, and a first opening 42, a second opening 72 and a third opening 82 penetrating through the passivation layer 10 are formed.

S53, over-etching n + GaN layer 2 in first opening 42, GaN base region 5 in second opening 72, and n + GaN cap layer 8 in third opening 82 simultaneously to form emitter opening 43, base opening 73, and collector opening 83, and to form emitter opening 43, base opening 73, and collector opening 83, as shown in fig. 4 g.

Specifically, the ICP etching process is utilized to perform the reaction gas of Cl₂The pressure of the reaction chamber is 10mTorr, the n + GaN cap layer 8, the GaN base region 5 and the n + GaN layer 2 are simultaneously etched under the conditions that the radio frequency power of the upper electrode and the radio frequency power of the lower electrode are 100W and 10W respectively, an emitter opening 43 embedded into the n + GaN layer 2, a base opening 73 embedded into the GaN base region 5 and a collector opening 83 embedded into the n + GaN cap layer 8 are formed, and the over-etching depth is 0-5 nm.

It is to be understood that when the over-etching depth is 0, emitter opening 43 is located on n + GaN layer 2, base opening 73 is located on GaN base region 5, and collector opening 83 is located on n + GaN cap layer 8, that is, first opening 42, second opening 72, and third opening 82 are emitter opening 43, base opening 73, and collector opening 83. When the over-etch depth is greater than 0, emitter opening 43 is embedded in n + GaN layer 2, base opening 73 is embedded in GaN base region 5, and collector opening 82 is embedded in n + GaN cap layer 8. Preferably, the over-etching depth is greater than 0, and the lower end of the formed base electrode 7 is embedded into the GaN base region 5, so that a good current control effect can be achieved.

And after etching is finished, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the open pore etching area, washing the sample with ultrapure water and drying with nitrogen.

S6, metal is evaporated in emitter opening 43, base opening 73 and collector opening 81 and on passivation layer 10 to form emitter 4, base 7 and collector 9.

S61, photoetching a collector patterned region on the surface of the passivation layer 10 on the n + GaN cap layer 8, photoetching a base patterned region on the surface of the passivation layer 10 on the GaN base region 5, and photoetching an emitter patterned region on the surface of the passivation layer 10 on the n + GaN layer 2.

Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, glue spreading and spin coating of the stripping glue are carried out on the n + GaN cap layer 8, the GaN base region 5 and the n + GaN layer 2, the thickness of the spin coating is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the emitter region, the base region and the collector region; and finally, putting the exposed sample into a developing solution to remove the photoresist and the stripper in the emitter, base and collector regions, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist and the stripper, thereby forming a collector patterned region, a base patterned region and an emitter patterned region.

S62, using electron beam evaporation process, metal is evaporated in the collector patterned region, the base patterned region, the emitter patterned region, the first opening 43, the second opening 73, and the third opening 81, thereby forming the emitter 4, the base 7, and the collector 9.

Firstly, putting a sample into an electron beam evaporation table, and waiting for the vacuum degree of a reaction chamber of the electron beam evaporation table to reach 2 multiplied by 10^-6And after Torr, evaporating a metal layer on the photoresist outside the emitter patterning region, the base region 5 in the base patterning region, the n + GaN layer 2 in the collector patterning region and the emitter patterning region, the base patterning region and the collector patterning region, wherein the metal layer is a stack structure sequentially consisting of three layers of Ni, Au and Ni from bottom to top.

And then, stripping the sample after the metal evaporation of the emitter 4, the base 7 and the collector 9 is finished to remove the metal, the photoresist and the stripping glue outside the areas of the emitter 4, the base 7 and the collector 9, washing the sample with ultrapure water and drying the sample with nitrogen to form the emitter 4, the base 7 and the collector 9, as shown in fig. 4h or 4i, wherein fig. 4h is a device structure when the over-etching depth is 0, and fig. 4i is a device structure when the over-etching depth is greater than 0.

The preparation process of the gallium nitride hot electron transistor device is compatible with the existing process, has low cost and is beneficial to realizing the large-scale preparation of the gallium nitride hot electron transistor device.

EXAMPLE III

On the basis of the first and second embodiments, the present embodiment provides a gallium nitride hot electron transistor device including a GaN free-standing substrate 1, an n + GaN layer 2, and Al_xGa_1-xN emitter region 3, emitter 4, GaN base region 5, Al_yGa_1-yThe specific structure of the device is shown in the first embodiment, and details of the device are not repeated in this embodiment.

Wherein, the GaN thermionic transistor device selects a GaN self-supporting substrate 1, an n + GaN layer 2 and Al which are sequentially laminated from bottom to top_xGa_1-xN emitter region 3, GaN base region 5, Al_yGa_1-yThe N collector region 6 and the N + GaN cap layer 8 are used as epitaxial substrates, wherein the thickness of the N + GaN cap layer 8 is 10nm, and the doping concentration is 5e¹⁸cm^-3，Al_yGa_1-yDoping concentration 5e of N collector region 6¹⁷cm^-35% of Al component, 40nm of thickness, and 8e of doping concentration of GaN base region 4¹⁸cm^-38nm thick, Al_xGa_1-xDoping concentration 1e of N emitter region 3¹⁸cm^-325% Al component, 25nm thickness, n-type doping concentration 3e of n + GaN layer 2¹⁸cm^-3Thickness of 15nm, doping concentration of GaN free-standing substrate 1 of 5e¹⁸cm^-3。

The preparation method of the gallium nitride hot electron transistor device comprises the following steps:

and S1, manufacturing the electrical isolation of the active region of the device.

S11, lithography of electrically isolated regions of the active region on the n + GaN cap layer 8.

S12, etching the n + GaN cap layer 8 and the Al of the electric isolation region in sequence by utilizing an inductively coupled plasma etching process ICP_yGa_1-yN collector region 6, GaN base region 5 and Al_xGa_1-xAn N emitter region 3 and an N + GaN layer 2, forming an electrical isolation of the active region of the device.

S2, etching the n + GaN cap layer 8 at the periphery of the epitaxial substrate, and Al_yGa_1-yN collector region 6, GaN base region 5 and Al_xGa_1-xN emitter region 3, forming emitter region 41.

S21, photoetching is carried out on the target pattern area on the periphery of the n + GaN cap layer 8.

S22, etching the n + GaN cap layer 8 and Al of the target pattern area by utilizing the ICP process_yGa_1-yN collector region 6, GaN base region 5 and Al_xGa_1-xN emitter region 3, forming emitter region 41. Wherein the etching depth is 83 nm.

S3, etching the n + GaN cap layer 8 and Al_yGa_1-yAnd an N collector region 6 forming a base region 71 and a collector region 81.

S31, photoetching is carried out on the target pattern area on the periphery of the n + GaN cap layer 8.

S32, etching the n + GaN cap layer 8 and Al of the target pattern area by the ICP process_yGa_1-yAnd an N collector region 6 forming a base region 71 and a collector region 81. Wherein the etching depth is 50 nm.

And S41, cleaning the surface of the device after the base region etching is finished.

S42, on the upper surface of the n + GaN layer 2, Al_xGa_1-xSide surface of N emitter region 3, side surface and upper surface of GaN base region 5, and Al_yGa_1-yThe side surface of the N collector region 6 and the side surface and the upper surface of the N + GaN cap layer 8 are subjected to PECVD (plasma enhanced chemical vapor deposition) process to grow a SiN passivation layer with the thickness of 30nm, wherein the growth process conditions are as follows: by NH₃And SiH₄As the reaction gas, the substrate temperature was 250 ℃, the reaction chamber pressure was 600mTorr, and the RF power was 22W.

In this embodiment, the n + GaN cap layer 8, the GaN base region 5, and the n + GaN layer 2 are not over-etched, that is, the over-etching depth is 0, and at this time, the first opening 42, the second opening 72, and the third opening 82 are the emitter opening 43, the base opening 73, and the collector opening 83.

S6, metal is evaporated in emitter opening 43, base opening 73 and collector opening 81 and on passivation layer 10 to form emitter 4, base 7 and collector 9.

Please refer to embodiment two for the detailed implementation of steps S1-S6, which is not described in detail in this embodiment.

Example four

Wherein, the GaN thermionic transistor device selects a GaN self-supporting substrate 1, an n + GaN layer 2 and Al which are sequentially laminated from bottom to top_xGa_1-xN emitter region 3, GaN base region 5, Al_yGa_1-yThe structure of the N collector region 6 and the N + GaN cap layer 8 is used as an epitaxial substrate, wherein the thickness of the N + GaN cap layer 8 is 15nm, and the doping concentration is 8e¹⁸cm^-3，Al_yGa_1-yDoping concentration 1e of N collector region 6¹⁸cm^-3Al component of 8%, thickness of 50nm, doping concentration of GaN base region 4 of 1e¹⁹cm^-310nm thick, Al_xGa_1-xDoping concentration 5e of the N emitter region 3¹⁸cm^-3An Al component of 30%, a thickness of 35nm, and an n-type doping concentration of 5e in the n + GaN layer 2¹⁸cm^-3Thickness of 30nm, doping concentration of GaN free-standing substrate 12 e¹⁸cm^-3。