阅读说明：本技术 运算电路、芯片和板卡 (Arithmetic circuit, chip and board card ) 是由 不公告发明人 于 2021-09-10 设计创作，主要内容包括：本披露公开了一种运算电路、芯片和板卡。该运算电路可以实现为计算装置包括在组合处理装置中,该组合处理装置还可以包括接口装置和其他处理装置。该计算装置与其他处理装置进行交互,共同完成用户指定的计算操作。组合处理装置还可以包括存储装置,该存储装置分别与计算装置和其他处理装置连接,用于存储该计算装置和其他处理装置的数据。本披露的方案对运算电路进行优化,实现多种模式的乘加运算,增加了运算器件的灵活性。(The disclosure discloses an arithmetic circuit, a chip and a board card. The arithmetic circuitry may be implemented as computing means included in a combined processing means, which may also include interface means and other processing means. The computing device interacts with other processing devices to jointly complete computing operations specified by a user. The combined processing device may further comprise a storage device connected to the computing device and the other processing device, respectively, for storing data of the computing device and the other processing device. The scheme disclosed by the invention optimizes the operation circuit, realizes multiply-add operation in multiple modes, and increases the flexibility of an operation device.)

1. An arithmetic circuit, comprising:

a multiplier configured to perform a multiplication operation;

an adder configured to perform an addition operation; and

a plurality of selectors configured to control the selection paths according to respective enable signals to communicate input data with the multipliers and/or adders to perform a specified operation mode and output corresponding results;

wherein the operation mode has an operation rule including a multiplication operation and/or an addition operation.

2. The operational circuit of claim 1, wherein the plurality of selectors comprises:

a first selector having a first input coupled to the first data input, a second input coupled to the output of the adder, and an output coupled to the first input of the multiplier;

a second selector having a first input coupled to the first data input, a second input coupled to the output of the multiplier, and an output coupled to the first input of the adder;

a third selector having a first input connected to the second data input, a second input connected to the third data input, and an output connected to the second input of the multiplier;

a fourth selector having a first input connected to the second data input, a second input connected to the third data input, and an output connected to the second input of the adder; and

and a fifth selector, a first input end of which is connected with the output end of the adder, a second input end of which is connected with the output end of the multiplier, and an output end of which is the output end of the arithmetic circuit.

3. The arithmetic circuit of claim 2, further comprising:

a logic circuit configured to generate corresponding enable signals to be respectively transferred to the plurality of selectors according to the operation mode indication signal.

4. The operation circuit according to claim 3, wherein the operation mode indication signal comprises a two-bit mode indication bit for indicating four operation modes:

(a + b) + c; (a + b) c; a and b; and a + b;

wherein a, b, c are the first input data, the second input data and the third input data of the arithmetic circuit, respectively.

5. The arithmetic circuit of claim 4, wherein a first bit of the two-bit pattern indication bits is used to indicate an operation order of multiplication and addition between the first input data a and the second input data b, and a second bit is used to indicate whether the third input data c participates in the operation.

6. The operational circuit of claim 5, wherein the logic circuit is further to:

determining respective enable signals of the first, second, third, and fourth selectors based on a value of a first bit; and

determining an enable signal of the fifth selector based on values of the first bit and the second bit.

7. The arithmetic circuit according to claim 6, wherein the enable signal of the first selector is the same as the enable signal of the third selector, the enable signal of the second selector is the same as the enable signal of the fourth selector, and the enable signal of the first selector is opposite to the enable signal of the second selector.

8. The operational circuit of claim 7, wherein the logic circuit is further to:

and according to the corresponding relation between the two-bit mode indication bit and the four operation modes, setting the enabling signal of the first selector to be equal to or opposite to the value of the first bit in the two-bit mode indication bit, and setting the enabling signal of the fifth selector to be equal to the exclusive-or result or the exclusive-or result of the first bit and the second bit.

9. A chip comprising an arithmetic circuit according to any of claims 1-8.

10. A board comprising the chip of claim 9.

Technical Field

The present disclosure relates generally to the field of electrical circuits. More particularly, the present disclosure relates to an arithmetic circuit, a chip and a board.

Background

At present, Deep Learning (Deep Learning) has become an important branch in machine Learning, and the development of Artificial Intelligence (AI) is also greatly promoted. The core technology of deep learning, Deep Neural Network (DNN), has been widely used in many industries.

There are a large number of multiplications, additions, and a mixture of multiplications and additions in the neural network model, which can be implemented by corresponding operational circuits. However, the input data sources of the computing devices (such as multipliers) in the current computing circuit are often fixed, such that one computing circuit can only execute a predetermined computing mode, thereby resulting in poor flexibility of the computing devices.

Disclosure of Invention

To solve at least one or more of the above-mentioned technical problems, the present disclosure proposes an arithmetic circuit that can implement multiple modes of multiplication and/or addition operations by introducing multiple selectors and selectively controlling the operation data of multipliers and adders.

In a first aspect, an embodiment of the present disclosure provides an arithmetic circuit, including: a multiplier configured to perform a multiplication operation; an adder configured to perform an addition operation; and a plurality of selectors configured to control the selection paths according to respective enable signals to communicate input data with the multipliers and/or adders to perform a specified operation mode and output corresponding results; wherein the operation mode has an operation rule including a multiplication operation and/or an addition operation.

In a second aspect, embodiments of the present disclosure provide a chip including the operational circuit of the first aspect.

In a third aspect, the disclosed embodiments provide a board card comprising the chip of the second aspect.

Through the arithmetic circuit, the chip and the board card provided above, the scheme of the embodiment of the disclosure can control each selector to communicate with different paths through the configuration of the enable signal, thereby controlling to input different operation data to the multiplier and the adder, and further realizing multiplication and/or addition operation in multiple modes. Therefore, the arithmetic circuit is optimized, and the optimized arithmetic circuit can realize multiply-add operation in multiple modes, so that the flexibility of an arithmetic device is improved.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

fig. 1 shows a block diagram of a board card of an embodiment of the present disclosure;

FIG. 2 shows a block diagram of a combined processing device of an embodiment of the disclosure;

FIG. 3 illustrates an internal structural diagram of a processor core of a single or multi-core computing device of an embodiment of the present disclosure;

FIG. 4 shows a schematic block diagram of an arithmetic circuit of one embodiment of the present disclosure;

FIG. 5 shows a schematic block diagram of an arithmetic circuit of another embodiment of the present disclosure;

FIG. 6 shows a schematic block diagram of a logic circuit of one embodiment of the present disclosure; and

fig. 7 a-7 d show simplified circuit diagrams of four modes of operation, respectively.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, not all embodiments of the present disclosure. All other embodiments, which can be derived by one skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the scope of protection of the present disclosure.

It should be understood that the terms "first," "second," "third," and "fourth," etc. as may appear in the claims, specification, and drawings of the present disclosure, are used for distinguishing between different objects and not for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection".

Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

Fig. 1 shows a schematic structural diagram of a board card 10 according to an embodiment of the disclosure. As shown in fig. 1, the board card 10 includes a Chip 101, which is a System-on-Chip (SoC) or System-on-Chip, and is integrated with one or more combined processing devices, which are artificial intelligence arithmetic units, for supporting various deep learning and machine learning algorithms, and meeting the intelligent processing requirements in the fields of computer vision, speech, natural language processing, data mining, and the like under complex scenes. Especially, the deep learning technology is widely applied to the field of cloud intelligence, and one remarkable characteristic of the cloud intelligence application is that the input data size is large, and the requirements on the storage capacity and the computing capacity of the platform are high.

The chip 101 is connected to an external device 103 through an external interface device 102. The external device 103 is, for example, a server, a computer, a camera, a display, a mouse, a keyboard, a network card, a wifi interface, or the like. The data to be processed may be transferred by the external device 103 to the chip 101 through the external interface device 102. The calculation result of the chip 101 may be transmitted back to the external device 103 via the external interface device 102. The external interface device 102 may have different interface forms, such as a PCIe interface, according to different application scenarios.

The card 10 also includes a memory device 104 for storing data, which includes one or more memory cells 105. The memory device 104 is connected and data-transferred with the control device 106 and the chip 101 through a bus. The control device 106 in the board 10 is configured to regulate the state of the chip 101. For this purpose, in an application scenario, the control device 106 may include a single chip Microcomputer (MCU).

Fig. 2 is a structural diagram showing a combined processing device in the chip 101 of this embodiment. As shown in fig. 2, the combination processing device 20 includes a computing device 201, an interface device 202, a processing device 203, and a storage device 204.

The computing device 201 is configured to perform user-specified operations, mainly implemented as a single-core smart processor or a multi-core smart processor, to perform deep learning or machine learning computations, which may interact with the processing device 203 through the interface device 202 to collectively perform the user-specified operations.

The interface device 202 is used for transmitting data and control instructions between the computing device 201 and the processing device 203. For example, the computing device 201 may obtain input data from the processing device 203 via the interface device 202, and write to a storage device on the computing device 201. Further, the computing device 201 may obtain the control instruction from the processing device 203 via the interface device 202, and write the control instruction into a control cache on the computing device 201. Alternatively or optionally, the interface device 202 may also read data from a storage device of the computing device 201 and transmit the data to the processing device 203.

The processing device 203, as a general purpose processing device, performs basic control including, but not limited to, data transfer, starting and/or stopping of the computing device 201, and the like. Depending on the implementation, the processing device 203 may be one or more types of Central Processing Unit (CPU), Graphics Processing Unit (GPU) or other general purpose and/or special purpose processor, including but not limited to a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc., and the number thereof may be determined according to actual needs. As previously mentioned, the computing device 201 of the present disclosure may be viewed as having a single core structure or an isomorphic multi-core structure only. However, when considered collectively, the computing device 201 and the processing device 203 are considered to form a heterogeneous multi-core structure.

The storage device 204 is used to store data to be processed, which may be a DRAM, a DDR memory, and is typically 16G or larger in size, and is used to store data of the computing device 201 and/or the processing device 203.

Fig. 3 shows a schematic diagram of an internal structure of a processing core when the computing device 201 is a single-core or multi-core device. The computing device 301 is used for processing input data such as computer vision, voice, natural language, data mining, and the like, and the computing device 301 includes three major modules: a control module 31, an operation module 32 and a storage module 33.

The control module 31 is used for coordinating and controlling the operations of the operation module 32 and the storage module 33 to complete the task of deep learning, and includes an Instruction Fetch Unit (IFU) 311 and an Instruction Decode Unit (IDU) 312. The instruction fetch unit 311 is used for obtaining an instruction from the processing device 203, and the instruction decode unit 312 decodes the obtained instruction and sends the decoded result to the operation module 32 and the storage module 33 as control information.

The operation module 32 includes a vector operation unit 321 and a matrix operation unit 322. The vector operation unit 321 is used for performing vector operations, and can support complex operations such as vector multiplication, addition, nonlinear transformation, and the like; the matrix operation unit 322 is responsible for the core calculation of the deep learning algorithm, i.e., matrix multiplication and convolution.

The storage module 33 is used to store or transport related data, and includes a neuron storage unit (neuron RAM, NRAM)331, a weight storage unit (weight RAM, WRAM)332, and a Direct Memory Access (DMA) 333. NRAM 331 is used to store input neurons, output neurons, and intermediate results after computation; WRAM 332 is used to store the convolution kernel of the deep learning network, i.e. the weight; the DMA 333 is connected to the DRAM 204 via the bus 34 and is responsible for data transfer between the computing device 301 and the DRAM 204.

The hardware architecture and its internal structure of the present disclosure are described in detail above in conjunction with fig. 1-3. It is to be understood that the above description is intended to be illustrative, and not restrictive. According to different application scenarios and hardware specifications, those skilled in the art may also change the board card and the internal structure of the present disclosure, and these changes still fall into the protection scope of the present disclosure. Embodiments of the present disclosure provide a multi-mode arithmetic circuit based on the aforementioned hardware environment, which can be used to implement various circuits in the arithmetic module 32 in fig. 3, for example, including but not limited to a vector arithmetic unit 321 and a matrix element unit 322.

Fig. 4 shows a schematic block diagram of an arithmetic circuit 400 of one embodiment of the present disclosure. As shown in fig. 4, the arithmetic circuit 400 may include a multiplier 402, an adder 403, and a plurality of selectors, such as a selector 401 and a selector 404. Multiplier 402 may be configured to perform a multiplication operation and adder 403 may be configured to perform an addition operation.

In one implementation scenario, the multiplier 402 may be an analog multiplier, a hardware multiplier, or a harmonic multiplier, the adder 403 may be a full adder or a half adder, and the selector 401 and the selector 404 may be a data selector or a multiplexer, etc. In one implementation, the data selector may be a 1-from-2 data selector, a 1-from-3 data selector, or a 1-from-4 data selector, so that requirements of different operation scenarios may be met.

In one embodiment, the selector 401 and the selector 404 may be configured to control the selection path according to the corresponding enable signal to communicate the first input data a, the second input data b, and the third input data c with the multiplier 402 and/or the adder 403 to execute a specified operation mode and output a corresponding result. The number of selectors may be determined according to specific operation requirements (e.g., operation modes to be implemented), and may be, for example, 3, 4, 5, or 6. In addition, the number of inputs may be set to other numbers, for example, 2, 3, or 4, for different operation modes. It will be appreciated that these modes of operation have operation rules that include multiplication operations and/or addition operations. For example, the calculation of a fully-connected layer, a convolutional layer, a pooling layer, and the like, which are common in neural network models, can be generalized to an operation of multiplying two numbers and adding a third number.

FIG. 5 shows a schematic block diagram of an arithmetic circuit 500 for three input data, including five selectors, according to one embodiment of the present disclosure.

As can be seen from fig. 5, the arithmetic circuit 500 includes five selectors, namely a first selector 501, a second selector 502, a third selector 503, a fourth selector 504 and a fifth selector 505. A first selector 501 has a first input coupled to the first data input, a second input coupled to the output of adder 511, and an output coupled to a first input of multiplier 510. A second selector 502 has a first input coupled to the first data input, a second input coupled to the output of the multiplier 510, and an output coupled to a first input of the adder 511. In addition, the third selector 503 has a first input connected to the second data input, a second input connected to the third data input, and an output connected to the second input of the multiplier 510. A fourth selector 504 has a first input coupled to the second data input, a second input coupled to the third data input, and an output coupled to a second input of the adder 511. Further, a first input terminal of the fifth selector 505 is connected to the output terminal of the adder 511, a second input terminal thereof is connected to the output terminal of the multiplier 510, and an output terminal thereof is the output terminal of the arithmetic circuit 500.

The first data input terminal is set to receive first input data a from the outside, the second data input terminal is set to receive second input data b from the outside, and the third data input terminal is set to receive third input data c from the outside. The enable signal of the first selector 501 is en1, the enable signal of the second selector 502 is en2, the enable signal of the third selector 503 is en3, the enable signal of the fourth selector 504 is en4, and the enable signal of the fifth selector 505 is en 5.

Based on the structure of the operation circuit 500 and the three external input data, the scheme disclosed by the present disclosure can selectively communicate different paths through the control of the enable signals, thereby executing different operations and finally realizing corresponding operation modes. For example, for the first selector 501, it may be set that when its enable signal en1 is 0, it may communicate the path between the first data input terminal and the multiplier 510, so that the first input data a may be input to the multiplier 510. It can be set that when the enable signal en1 is 1, it can connect the path between the output terminal of the adder 511 and the multiplier 510, so that the output data of the adder 511 can be input to the multiplier 510.

For the second selector 502, it may be set that when the enable signal en2 is 0, it may communicate a path between the first data input terminal and the adder 511, so that the first input data a may be input to the adder 511. In addition, when the enable signal en2 is set to 1, it may connect the path between the output terminal of the multiplier 510 and the adder 511, so that the output data of the multiplier 510 may be input to the adder 511.

For the third selector 503, it may be set that when the enable signal en3 is 0, it may connect the path between the second data input terminal and the multiplier 510, so that the second input data b may be input to the multiplier 510. In addition, it may be set that when the enable signal en3 is 1, it may communicate a path between the third data input terminal and the multiplier 510, so that the third input data c may be input to the multiplier 510.

For the fourth selector 504, it may be set that when the enable signal en4 is 0, it may communicate the path between the second data input terminal and the adder 511, so that the second input data b may be input to the adder 511. It may also be provided that when the enable signal en4 is 1, it may communicate the path between the third data input terminal and the adder 511, so that the third input data c may be input to the adder 511.

The fifth selector 505 connected to the output terminal of the arithmetic circuit 500 is set so as to connect the output terminal of the adder 511 and the output terminal of the arithmetic circuit 500 when the enable signal en5 is 0, thereby outputting the output data of the adder 511 as the arithmetic result of the arithmetic circuit. Correspondingly, it can be set that when the enable signal en5 is 1, it can connect the output terminal of the multiplier 510 and the output terminal of the arithmetic circuit 500, so that the output data of the multiplier 510 can be output as the arithmetic result of the arithmetic circuit.

Based on the above-mentioned structure of the arithmetic circuit 500, the selectors can be configured to different selection modes by configuring the enable signals of the selectors differently, so that the arithmetic circuit 500 executes the corresponding operation mode. For example, when en1 is set to 0, en2 is set to 1, en3 is set to 0, en4 is set to 1, and en5 is set to 0, the first selector 501 controls a path communicating between the first data input terminal and the multiplier 510, and the third selector 503 controls a path communicating between the second data input terminal and the multiplier 510. The second selector 502 controls a path connecting between the output of the multiplier 510 and the adder 511, the fourth selector 504 controls a path connecting between the third data input terminal and the adder 511, and the fifth selector 505 controls a path connecting between the output of the adder 511 and the output of the arithmetic circuit 500. It can be seen that the operation mode of (a × b) + c can be realized by configuring the operation circuit.

When en1 is set to 1, en2 is set to 0, en3 is set to 1, en4 is set to 0, and en5 is set to 1, the second selector 502 controls a path communicating between the first data input and the adder 511, and the fourth selector 504 controls a path communicating between the second data input and the adder 511. The first selector 501 controls a path connecting between the output terminal of the adder 511 and the multiplier 510, the third selector 503 controls a path connecting between the third data input terminal and the multiplier 510, and the fifth selector 505 controls a path connecting between the output terminal of the multiplier 510 and the output terminal of the arithmetic circuit 500. It can be seen that the operational mode of (a + b) × c can be realized by configuring the operational circuit.

In addition, when en1 is set to 0, en3 is set to 0, and en5 is set to 1, the first selector 501 controls a path communicating between the first data input terminal and the multiplier 510, the third selector 503 controls a path communicating between the second data input terminal and the multiplier 510, and the fifth selector 505 controls a path communicating between the output terminal of the multiplier 510 and the output terminal of the arithmetic circuit 500. It can be seen that the operational mode of a x b can be realized by configuring the operational circuit.

Further, when en2 is set to 0, en4 is set to 0, and en5 is set to 0, the second selector 502 controls a path communicating between the first data input terminal and the adder 511, the fourth selector 504 controls a path communicating between the second data input terminal and the adder 511, and the fifth selector 505 controls an output terminal of the adder 511 and an output terminal of the arithmetic circuit 500. Therefore, the operational mode of a + b can be realized by the configuration operational circuit.

As can be seen from the above description, the embodiment of the present disclosure may control each selector in the operation circuit to communicate with different paths through configuration of the enable signal, so as to control input of different operation data to the multiplier and the adder, thereby implementing multiple modes of multiplication and/or addition operations. Therefore, the embodiment of the scheme realizes the optimization of the arithmetic circuit, and the arithmetic circuit can realize multiply-add operation in various modes through the optimization, so that the flexibility of an arithmetic device is improved.

In one embodiment, the enable signals for the various selectors of fig. 5 described above may be generated by hardware circuitry. In one implementation, the hardware circuit may be a logic circuit, and the logic circuit may be configured to generate corresponding enable signals to be respectively transmitted to the plurality of selectors according to the operation mode indication signal.

Fig. 6 shows a schematic block diagram of a logic circuit 600 of one embodiment of the present disclosure. In the embodiment shown in the figure, the logic circuit 600 can generate the enable signals en1, en2, en3, en4 and en5 of the five selectors in fig. 5 described above according to the operation mode indication signals mode1 and mode2 (two-bit mode indication bits of the operation mode indication signals, which will be described in detail later), and transfer them to the corresponding selectors, respectively.

In one implementation scenario, the logic circuit 600 may be implemented by a combination of one or more of a variety of logic gate circuits, such as and gates, or gates, not gates, and xor gates. For example, a logic circuit may be formed by and gates, not gates, and exclusive or gates, so that, for example, and operations, not operations, and exclusive or operations may be performed on the two-bit mode indicating bits mode1 and mode2 in the operation mode indicating signal and corresponding enable signals may be generated. In addition, the operation mode indication signal may be from a control module, such as a processor, for controlling the operation of the operation circuit.

In another implementation scenario, the enable signal may also be generated by a software algorithm. The software algorithm may be a logic operation method corresponding to the logic circuit 600, i.e., a combination operation method of one or more of a plurality of logic operations, such as an and operation, an or operation, a non-operation, and an xor operation, and will not be described in detail herein.

The above description only illustrates some logic circuits and logic operation methods, and those skilled in the art can select other logic circuits or logic operation methods according to different operation scenarios (for example, different corresponding relationships between the operation mode indication signal and the enable signal), which will not be described in detail herein.

In the exemplary operational circuit of fig. 5, it supports four operational modes, whereby the operational mode indication signal may comprise two bits of mode indication bits (e.g. mode1 and mode2 in the above described embodiments) for indicating, for example, the aforementioned four operational modes.

Fig. 7 a-7 d show simplified circuit diagrams of the four operational modes, respectively, where fig. 7a corresponds to the (a × b) + c mode, fig. 7b corresponds to the (a + b) × c mode, fig. 7c corresponds to the a × b mode, and fig. 7d corresponds to the a + b mode. In fig. 7 a-7 d, reference numeral 701 denotes a multiplier and reference numeral 702 denotes an adder.

There are various ways to indicate the four operation modes by the operation mode indication signal. For example, in one embodiment, a first bit of the two-bit mode indication bit may be set to indicate an operation order of multiplication and addition between the first input data a and the second input data b, and a second bit may be set to indicate whether the third input data c participates in the operation. Further, it may be arranged that the multiplication operation is performed first when the first bit is 0, and that the addition operation is performed first when the first bit is 1, or vice versa. In addition, it may be set to indicate that the third input data c participates in the operation when the second bit is 0, and to accordingly set to indicate that the third input data c does not participate in the operation when the second bit is 1, or vice versa.

Based on the above setting, when both the first bit and the second bit are 0, the (a × b) + c pattern shown in fig. 7a can be performed. When the first bit is 1 and the second bit is 0, the (a + b) × c pattern shown in fig. 7b may be performed. When the first bit is 0 and the second bit is 1, the a × b pattern shown in fig. 7c may be performed. Further, when both the first bit and the second bit are 1, the a + b mode shown in fig. 7d may be performed. Therefore, the indicating function of the two-bit mode indicating bit can be set to control the operation circuit to execute different operation modes.

It will be understood by those skilled in the art that the indication function of the two-bit mode indication bit is merely exemplary and not restrictive, and those skilled in the art may set the indication function to be different indication functions according to different operation scenarios, so as to implement different operation modes.

To facilitate the generation of the corresponding enable signal according to the two-bit mode indicator bit in the operation mode indicator signal, in one embodiment, when the first bit mode1 in the operation mode indicator signal indicates the operation order of multiplication and addition between the first input data a and the second input data b, the logic circuit 600 may be configured to determine the enable signals of the first selector 501, the second selector 502, the third selector 503 and the fourth selector 504, respectively, based on the value of the first bit. Further, the logic circuit 600 may be configured to determine the enable signal of the fifth selector 505 based on the values of the first bit and the second bit.

Further, based on the specific connection relationship of the selector with the multiplier and adder shown in fig. 5, the respective enable signals may be set as follows: the enable signal of the first selector 501 is set to be the same as the enable signal of the third selector 503, the enable signal of the second selector 502 is set to be the same as the enable signal of the fourth selector 504, and the enable signal of the first selector 501 is set to be opposite to the enable signal of the second selector 502, and accordingly, the enable signal of the third selector 503 is also opposite to the enable signal of the fourth selector 504. Based on the above setting, the logic circuit 600 is further configured to set the enable signal of the first selector 501 to be equal to or opposite to the value of the first bit of the two-bit mode indication bits, and set the enable signal of the fifth selector 505 to be equal to the exclusive-or result or the exclusive-or result of the first bit and the second bit, according to the correspondence relationship between the two-bit mode indication bits and the four operation modes.

To further illustrate the correspondence between the two-bit mode indicator bits in the operation mode indicator signal and the respective enable signals, the following provides a truth table with three different configurations, as shown in tables 1-3. In tables 1-3, mode1 is the first bit of the two-bit mode indicator bit, mode2 is the second bit of the two-bit mode indicator bit, and en1-en5 are the enable signals of the aforementioned first selector 501-fifth selector 505, respectively. In the table, "-" indicates an arbitrary value.

In table 1, it is set that when mode1 is 0, it indicates that multiplication is calculated first; when mode1 is 1, it indicates that the addition is calculated first. When mode2 is 0, third input data c is indicated to participate in the operation, and when mode2 is 1, third input data c is indicated not to participate in the operation.

TABLE 1

mode2	mode1	Operation mode	en1	en2	en3	en4	en5
								0	0	(a*b)+c	0	1	0	1	0
0	1	(a+b)*c	1	0	1	0	1
								1	0	a*b	0	-	0	-	1
1	1	a+b	-	0	-	0	0

From this table 1, it can be derived that the logical relationship between the five enable signals and the mode indication bit is as follows:

en1＝mode1，en2＝not mode1，

en3＝mode1，en4＝not mode1，

en5 — mode1 xor mode2, where not denotes a logical not and xor denotes a logical xor.

In table 2, it is set that when mode1 is 0, it indicates that multiplication is calculated first; when mode1 is 1, it indicates that the addition is calculated first. When mode2 is 0, it is indicated that the third input data c does not participate in the operation, and when mode2 is 1, it is indicated that the third input data c participates in the operation.

TABLE 2

mode2	mode1	Operation mode	en1	en2	en3	en4	en5
								0	0	a*b	0	-	0	-	1
0	1	a+b	-	0	-	0	0
								1	0	(a*b)+c	0	1	0	1	0
1	1	(a+b)*c	1	0	1	0	1

From this table 2, it can be derived that the logical relationship between the five enable signals and the mode indication bit is as follows:

en1＝mode1，en2＝not mode1，

en3＝mode1，en4＝not mode1，

en5 ═ mode1 xnor mode2, where xnor represents a logical "exclusive or" exclusive nor ".

In table 3, when mode1 is 0, it indicates that the addition is calculated first; when mode1 is 1, it is indicated that the multiplication is first calculated. When mode2 is 0, it is indicated that the third input data c does not participate in the operation, and when mode2 is 1, it is indicated that the third input data c participates in the operation.

TABLE 3

mode2	mode1	Operation mode	en1	en2	en3	en4	en5
								0	0	a+b	-	0	-	0	0
0	1	a*b	0	-	0	-	1
								1	0	(a+b)*c	1	0	1	0	1
1	1	(a*b)+c	0	1	0	1	0

From this table 3, it can be derived that the logical relationship between the five enable signals and the mode indication bit is as follows:

en1＝not mode1，en2＝mode1，

en3＝not mode1，en4＝mode1，

en5＝mode1 xor mode2。

it can be seen from the above three different corresponding relationships that, for the same arithmetic circuit, the operation mode indication signal can be associated with multiple (e.g. 4) operation modes, so that corresponding enable signals can be generated for each selector according to the operation mode indication signal to realize the operation mode indicated by the operation mode indication signal, thereby realizing flexibility of the configuration of the arithmetic circuit. It is understood that other correspondences may also be contemplated by those skilled in the art, and the present disclosure is not limited in this respect.

The implementation method of the arithmetic circuit to implement multiple operation modes is exemplarily described above in connection with the arithmetic circuit shown in fig. 5. It is understood that, under the teaching of the foregoing embodiments, a person skilled in the art may also modify the structure of the operation circuit and configure the corresponding parameters, so as to implement the corresponding operation mode, and therefore, the detailed description is omitted here.

The disclosed embodiments also provide a chip that may include the operational circuit of any of the embodiments described above in connection with the figures. Further, the disclosure also provides a board card, which may include the aforementioned chip.

According to different application scenarios, the electronic device or apparatus of the present disclosure may include a server, a cloud server, a server cluster, a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a PC device, a terminal of the internet of things, a mobile terminal, a mobile phone, a vehicle recorder, a navigator, a sensor, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a visual terminal, an autopilot terminal, a vehicle, a household appliance, and/or a medical device. The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph. The electronic device or apparatus of the present disclosure may also be applied to the fields of the internet, the internet of things, data centers, energy, transportation, public management, manufacturing, education, power grid, telecommunications, finance, retail, construction site, medical, and the like. Further, the electronic device or apparatus disclosed herein may also be used in application scenarios related to artificial intelligence, big data, and/or cloud computing, such as a cloud end, an edge end, and a terminal. In one or more embodiments, a computationally powerful electronic device or apparatus according to the present disclosure may be applied to a cloud device (e.g., a cloud server), while a less power-consuming electronic device or apparatus may be applied to a terminal device and/or an edge-end device (e.g., a smartphone or a camera). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and/or the edge device are compatible with each other, so that appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and/or the edge device according to the hardware information of the terminal device and/or the edge device, and uniform management, scheduling and cooperative work of end-cloud integration or cloud-edge-end integration can be completed.

It is noted that for the sake of brevity, the present disclosure describes some methods and embodiments thereof as a series of acts and combinations thereof, but those skilled in the art will appreciate that the aspects of the present disclosure are not limited by the order of the acts described. Accordingly, one of ordinary skill in the art will appreciate that certain steps may be performed in other sequences or simultaneously, in accordance with the disclosure or teachings of the present disclosure. Further, those skilled in the art will appreciate that the embodiments described in this disclosure are capable of alternative embodiments, in which acts or modules are involved, which are not necessarily required to practice one or more aspects of the disclosure. In addition, the present disclosure may focus on the description of some embodiments, depending on the solution. In view of the above, those skilled in the art will understand that portions of the disclosure that are not described in detail in one embodiment may also be referred to in the description of other embodiments.

In particular implementation, based on the disclosure and teachings of the present disclosure, one skilled in the art will appreciate that the several embodiments disclosed in the present disclosure may be implemented in other ways not disclosed herein. For example, as for the units in the foregoing embodiments of the electronic device or apparatus, the units are split based on the logic function, and there may be another splitting manner in the actual implementation. Also for example, multiple units or components may be combined or integrated with another system or some features or functions in a unit or component may be selectively disabled. The connections discussed above in connection with the figures may be direct or indirect couplings between the units or components in terms of connectivity between the different units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection utilizing an interface, where the communication interface may support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

In the present disclosure, units described as separate parts may or may not be physically separate, and parts shown as units may or may not be physical units. The aforementioned components or units may be co-located or distributed across multiple network elements. In addition, according to actual needs, part or all of the units can be selected to achieve the purpose of the solution of the embodiment of the present disclosure. In addition, in some scenarios, multiple units in embodiments of the present disclosure may be integrated into one unit or each unit may exist physically separately.

In other implementation scenarios, the integrated unit may also be implemented in hardware, that is, a specific hardware circuit, which may include a digital circuit and/or an analog circuit, etc. The physical implementation of the hardware structure of the circuit may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors, among other devices. In this regard, the various devices described herein (e.g., computing devices or other processing devices) may be implemented by suitable hardware processors, such as central processing units, GPUs, FPGAs, DSPs, ASICs, and the like. Further, the aforementioned storage unit or storage device may be any suitable storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), and may be, for example, a variable Resistive Memory (RRAM), a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), an Enhanced Dynamic Random Access Memory (EDRAM), a High Bandwidth Memory (HBM), a Hybrid Memory Cube (HMC), a ROM, a RAM, or the like.

The foregoing may be better understood in light of the following clauses:

clause 1, an arithmetic circuit, comprising:

a multiplier configured to perform a multiplication operation;

an adder configured to perform an addition operation; and

a plurality of selectors configured to control the selection paths according to respective enable signals to communicate input data with the multipliers and/or adders to perform a specified operation mode and output corresponding results;

wherein the operation mode has an operation rule including a multiplication operation and/or an addition operation.

Clause 2, the operational circuit of clause 1, wherein the plurality of selectors comprises:

a first selector having a first input coupled to the first data input, a second input coupled to the output of the adder, and an output coupled to the first input of the multiplier;

a second selector having a first input coupled to the first data input, a second input coupled to the output of the multiplier, and an output coupled to the first input of the adder;

a third selector having a first input connected to the second data input, a second input connected to the third data input, and an output connected to the second input of the multiplier;

a fourth selector having a first input connected to the second data input, a second input connected to the third data input, and an output connected to the second input of the adder; and

and a fifth selector, a first input end of which is connected with the output end of the adder, a second input end of which is connected with the output end of the multiplier, and an output end of which is the output end of the arithmetic circuit.

Clause 3, the arithmetic circuit of clause 2, further comprising:

a logic circuit configured to generate corresponding enable signals to be respectively transferred to the plurality of selectors according to the operation mode indication signal.

Clause 4, the operational circuit according to clause 3, wherein the operational mode indication signal includes a two-bit mode indication bit for indicating four operational modes:

(a + b) + c; (a + b) c; a and b; and a + b;

wherein a, b, c are the first input data, the second input data and the third input data of the arithmetic circuit, respectively.

Clause 5, the operation circuit according to clause 4, wherein a first bit of the two-bit pattern indication bits is used to indicate an operation order of multiplication and addition between the first input data a and the second input data b, and a second bit is used to indicate whether the third input data c participates in the operation.

Clause 6, the operational circuit of clause 5, wherein the logic circuit is further to:

determining respective enable signals of the first, second, third, and fourth selectors based on a value of a first bit; and

determining an enable signal of the fifth selector based on values of the first bit and the second bit.

Clause 7, the arithmetic circuit according to clause 6, wherein the enable signal of the first selector is the same as the enable signal of the third selector, the enable signal of the second selector is the same as the enable signal of the fourth selector, and the enable signal of the first selector is opposite to the enable signal of the second selector.

Clause 8, the operational circuit of clause 7, wherein the logic circuit is further to:

and according to the corresponding relation between the two-bit mode indication bit and the four operation modes, setting the enabling signal of the first selector to be equal to or opposite to the value of the first bit in the two-bit mode indication bit, and setting the enabling signal of the fifth selector to be equal to the exclusive-or result or the exclusive-or result of the first bit and the second bit.

Clause 9, a chip comprising the arithmetic circuit of any of clauses 1-8.

Clause 10, a board comprising the chip of clause 9.

The foregoing detailed description of the embodiments of the present disclosure has been presented for purposes of illustration and description and is intended to be exemplary only and is not intended to be exhaustive or to limit the invention to the precise forms disclosed; meanwhile, for the person skilled in the art, based on the idea of the present disclosure, there may be variations in the specific embodiments and the application scope, and in summary, the present disclosure should not be construed as limiting the present disclosure.