阅读说明：本技术 氮化物半导体装置及其制造方法 (Nitride semiconductor device and method for manufacturing the same ) 是由 大岳浩隆 近松健太郎 高堂真也 长濑和也 于 2020-03-06 设计创作，主要内容包括：本发明的氮化物半导体装置1包含：第1氮化物半导体层4,构成电子移行层；第2氮化物半导体层5,形成在第1氮化物半导体层上,且构成电子供给层；及栅极部20,形成在第2氮化物半导体层上；栅极部20包含：隆脊形状的半导体栅极层21,形成在第2氮化物半导体层上,包括包含受体型杂质的氮化物半导体；及栅极电极22,形成在半导体栅极层上。半导体栅极层包括形成在第2氮化物半导体层上的栅极层主体部211、及形成在栅极层主体部的上表面的宽度中间部上的上方突出部212,在上方突出部的顶面上形成着栅极电极。(The nitride semiconductor device 1 of the present invention includes: a 1 st nitride semiconductor layer 4 constituting an electron transit layer; a 2 nd nitride semiconductor layer 5 formed on the 1 st nitride semiconductor layer and constituting an electron supply layer; and a gate portion 20 formed on the 2 nd nitride semiconductor layer; the gate portion 20 includes: a ridge-shaped semiconductor gate layer 21 formed on the 2 nd nitride semiconductor layer and including a nitride semiconductor containing acceptor-type impurities; and a gate electrode 22 formed on the semiconductor gate layer. The semiconductor gate layer includes a gate layer main body portion 211 formed on the 2 nd nitride semiconductor layer, and an upper protruding portion 212 formed on a width intermediate portion of an upper surface of the gate layer main body portion, and a gate electrode is formed on a top surface of the upper protruding portion.)

1. A nitride semiconductor device, comprising:

a 1 st nitride semiconductor layer constituting an electron transit layer;

a 2 nd nitride semiconductor layer formed on the 1 st nitride semiconductor layer, having a larger band gap than the 1 st nitride semiconductor layer, and constituting an electron supply layer; and

a gate portion formed on the 2 nd nitride semiconductor layer;

the gate portion includes:

a ridge-shaped semiconductor gate layer formed on the 2 nd nitride semiconductor layer, including a nitride semiconductor containing acceptor-type impurities; and

a gate electrode formed on the semiconductor gate layer; and is

The semiconductor gate layer includes a gate layer main body portion formed on the 2 nd nitride semiconductor layer, and an upper protruding portion formed on a width intermediate portion of an upper surface of the gate layer main body portion,

the gate electrode is formed on a top surface of the upper protruding portion.

2. The nitride semiconductor device according to claim 1, further comprising: a 1 st dielectric film covering a side surface of the upper protruding portion and an upper surface of the gate layer main body portion connected to a lower edge of the side surface; and

and a 2 nd dielectric film covering a side surface of the gate layer main body portion and a surface of the 2 nd nitride semiconductor layer.

3. The nitride semiconductor device according to claim 2, wherein a source contact hole and a drain contact hole penetrating the 2 nd dielectric film in a thickness direction are formed on the 2 nd dielectric film,

the nitride semiconductor device further includes a source electrode and a drain electrode that penetrate the source contact hole and the drain contact hole, respectively, and are in ohmic contact with the 2 nd nitride semiconductor layer.

4. The nitride semiconductor device according to any one of claims 1 to 3, wherein a thickness of the upper protruding portion is thinner than a thickness of the gate layer main body portion.

5. The nitride semiconductor device according to any one of claims 1 to 3, wherein a thickness of the upper protruding portion is thicker than a thickness of the gate layer main body portion.

6. The nitride semiconductor device according to any one of claims 1 to 5, wherein both side faces of the gate layer main body portion are formed as inclined faces in which a width of the gate layer main body portion gradually narrows toward the gate electrode side,

both side surfaces of the upper protruding portion are formed as inclined surfaces in which the width of the gate layer main body portion gradually decreases toward the gate electrode side.

7. The nitride semiconductor device according to claim 6, wherein an average inclination angle of a side surface of the gate layer main body portion is different from an average inclination angle of a side surface of the upper protruding portion.

8. The nitride semiconductor device according to any one of claims 1 to 7, wherein upper surfaces of both side portions of the gate layer main body portion, which connect lower edges of both side surfaces of the upper protruding portion and upper edges of corresponding side surfaces of the gate layer main body portion, respectively, are formed as inclined surfaces that gradually become thicker toward a center of a width of the gate layer main body portion.

9. The nitride semiconductor device according to any one of claims 1 to 8, wherein the gate electrode is formed in such a manner as to cover the entirety of the top surface of the upper protruding portion.

10. The nitride semiconductor device according to any one of claims 1 to 8, wherein both side edges of the lower surface of the gate electrode are receded more inward than corresponding side edges of the top surface of the upper protruding portion in a plan view.

11. The nitride semiconductor device according to any one of claims 1 to 10, wherein the 1 st nitride semiconductor layer is composed of a GaN layer,

the 2 nd nitride semiconductor layer is made of Al_xGa_1-xN (0 < x ≦ 1) layers,

the semiconductor gate layer is composed of a p-type GaN layer.

12. The nitride semiconductor device according to any one of claims 1 to 11, wherein when the semiconductor gate layer is set to a 1 st semiconductor gate layer, a 2 nd semiconductor gate layer containing a nitride semiconductor having a larger band gap than the 1 st semiconductor gate layer is interposed between the 1 st semiconductor gate layer and the gate electrode.

13. The nitride semiconductor device according to claim 11, wherein a 2 nd semiconductor gate layer comprising a nitride semiconductor is interposed between the 1 st semiconductor gate layer and the gate electrode when the semiconductor gate layer is set as a 1 st semiconductor gate layer,

the 2 nd semiconductor gate layer is made of Al_yGa_1-yN (0 ≦ y < 1, y ≦ x).

14. The nitride semiconductor device according to any one of claims 1 to 13, wherein the gate electrode is constituted of any one single film of a Ti film, a TiN film, and a TiW film or a composite film including any combination of 2 or more thereof.

15. The nitride semiconductor device according to any one of claims 1 to 14, further comprising a 3 rd dielectric layer formed on an upper surface of the gate electrode.

16. The nitride semiconductor device according to claim 2, further comprising a 3 rd dielectric layer formed on an upper surface of the gate electrode, a thickness of the 3 rd dielectric layer being thicker than a thickness of the 2 nd dielectric layer.

17. The nitride semiconductor device according to claim 2, wherein the 1 st and 2 nd dielectric layers are made of SiN film, SiO₂Film, SiON film, Al₂O₃Any one of a film, an AlN film, and an AlON film or a composite film including any combination of 2 or more of them.

18. The nitride semiconductor device according to claim 17, wherein the 1 st dielectric layer and the 2 nd dielectric layer are composed of the same material.

19. The nitride semiconductor device according to claim 17, wherein the 1 st dielectric layer and the 2 nd dielectric layer are composed of different materials.

20. A method for manufacturing a nitride semiconductor device, comprising the steps of:

forming a 1 st nitride semiconductor layer constituting an electron transit layer, a 2 nd nitride semiconductor layer constituting an electron supply layer, and a semiconductor gate material film including a nitride semiconductor containing acceptor type impurities in this order on a substrate;

forming a gate electrode film on the semiconductor gate material film;

selectively forming a top dielectric film on the gate electrode film;

forming a gate electrode including the gate electrode film, a top wall disposed on the gate electrode and including the dielectric film for a cap, and the semiconductor gate material film having an upper protruding portion directly below the gate electrode by selectively removing the gate electrode film and the semiconductor gate material film by dry etching using the dielectric film for a cap as a mask until the thickness of the semiconductor gate material film is halfway;

forming a dielectric film for side portions covering exposed surfaces of the top wall, the gate electrode, and the semiconductor gate material film;

forming a side wall composed of the dielectric film for side portions and covering the top wall, the gate electrode, and the side surface of the upper protruding portion by removing portions of the dielectric film for side portions other than portions covering the top wall, the gate electrode film, and the side surface of the upper protruding portion by etching; and

and a semiconductor gate layer forming step of forming a semiconductor gate layer including a gate layer body formed on the 2 nd nitride semiconductor layer and the upper protruding portion formed on the width intermediate portion of the upper surface of the gate layer body by selectively removing the semiconductor gate material film by dry etching using the top wall and the side wall as masks until the surface of the 2 nd nitride semiconductor layer is exposed.

21. The method for manufacturing a nitride semiconductor device according to claim 20, further comprising the steps of: forming a passivation film covering the top wall, the side wall, and an exposed surface of the 2 nd nitride semiconductor layer after the semiconductor gate layer forming step;

forming a source contact hole and a drain contact hole which penetrate through the passivation film in the thickness direction on the passivation film; and

and forming a source electrode and a drain electrode which penetrate through the source contact hole and the drain contact hole and are in ohmic contact with the 2 nd nitride semiconductor layer.

Technical Field

The present invention relates to a nitride semiconductor device including a group III nitride semiconductor (hereinafter, sometimes simply referred to as "nitride semiconductor") and a method for manufacturing the same.

Background

The group III nitride semiconductor is a semiconductor in which nitrogen is used as a group V element in a group III-V semiconductor. Aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN) are typical examples. In general, it may be represented by Al_xIn_yGa_1-x-yN(0≦x≦1，0≦y≦1，0≦x+y≦1)。

A HEMT (High Electron Mobility Transistor) using such a nitride semiconductor has been proposed. Such HEMTs include, for example: an electron transit layer comprising GaN; and an electron supply layer including AlGaN epitaxially grown on the electron travel layer. A pair of source and drain electrodes are formed in contact with the electron supply layer, and a gate electrode is disposed between the source and drain electrodes.

Due to polarization caused by lattice mismatch between GaN and AlGaN, the polarization in the electron transit layer is counted from the interface between the electron transit layer and the electron supply layer toward the inner sideForming a two-dimensional electron gas. The two-dimensional electron gas is used as a channel to connect the source electrode and the drain electrode. When the two-dimensional electron gas is blocked by applying a control voltage to the gate electrode, the source and drain electrodes are blocked. In a state where the control voltage is not applied to the gate electrode, the source and the drain are turned on, and thus the device is a normally-on device.

A device using a nitride semiconductor has characteristics such as high withstand voltage, high-temperature operation, large current density, high-speed switching, and low on-resistance, and thus, for example, patent document 1 proposes application to a power device.

[ Prior art documents ]

[ patent document ]

[ patent document 1] Japanese patent laid-open publication No. 2017-73506

Disclosure of Invention

[ problems to be solved by the invention ]

Patent document 1 discloses the following configuration: a p-type GaN gate layer (nitride semiconductor gate layer) is laminated on an AlGaN electron supply layer, a gate electrode is disposed on the AlGaN electron supply layer, and a depletion layer diffused from the p-type GaN gate layer causes a channel to disappear, thereby achieving a constant off state.

In such a configuration, an electric field is likely to concentrate at a contact portion between the upper surface of the p-type GaN gate layer and the side edge of the lower surface of the gate electrode (end in the width direction of the lower surface of the gate electrode), which causes a problem of a large gate leakage current.

When the gate leakage current is large, there are problems such as a failure to secure a gate voltage necessary for obtaining a desired on-resistance, an increase in power consumption in the gate driver circuit, and the like, and there is a concern that efficiency in the power circuit and the control circuit portion is reduced and heat generation is increased. This is a major problem in the case of HEMT, which is proposed to switch high frequency to very long.

The invention provides a nitride semiconductor device and a method for manufacturing the same, which can reduce gate leakage current and restrain reduction of gate rated voltage which is the maximum value stably applied to a gate.

[ means for solving problems ]

One embodiment of the present invention provides a nitride semiconductor device including: a 1 st nitride semiconductor layer constituting an electron transit layer; a 2 nd nitride semiconductor layer formed on the 1 st nitride semiconductor layer, having a larger band gap than the 1 st nitride semiconductor layer, constituting an electron supply layer; and a gate portion formed on the 2 nd nitride semiconductor layer; the gate portion includes: a ridge-shaped semiconductor gate layer formed on the 2 nd nitride semiconductor layer, including a nitride semiconductor containing acceptor-type impurities; and a gate electrode formed on the semiconductor gate layer; the semiconductor gate layer includes a gate layer main body portion formed on the 2 nd nitride semiconductor layer, and an upper protruding portion formed on a width intermediate portion of an upper surface of the gate layer main body portion, the gate electrode being formed on a top surface of the upper protruding portion.

In this configuration, an electric field is concentrated at a portion where the upper surface of the gate layer main body portion of the semiconductor gate layer intersects with the side surface of the upper protruding portion. That is, in this configuration, the position where the electric field is concentrated can be made distant from the width direction end of the lower surface of the gate electrode. This can suppress a gate leakage current from the width direction end of the gate electrode. Thus, a nitride semiconductor device can be realized in which gate leakage current can be reduced and a reduction in gate rated voltage, which is the maximum value that can be stably applied to a gate, can be suppressed.

In one embodiment of the present invention, the method further includes: a 1 st dielectric film covering a side surface of the upper protruding portion and an upper surface of the gate layer main body portion connected to a lower edge of the side surface; and a 2 nd dielectric film covering a side surface of the gate layer main body portion and a surface of the 2 nd nitride semiconductor layer.

In one embodiment of the present invention, the 2 nd dielectric film is formed with a source contact hole and a drain contact hole penetrating the 2 nd dielectric film in a thickness direction, and the nitride semiconductor device further includes a source electrode and a drain electrode penetrating the source contact hole and the drain contact hole, respectively, and in ohmic contact with the 2 nd nitride semiconductor layer.

In one embodiment of the present invention, a thickness of the upper protruding portion is thinner than a thickness of the gate layer main body portion.

In one embodiment of the present invention, a thickness of the upper protruding portion is thicker than a thickness of the gate layer main body portion.

In one embodiment of the present invention, both side surfaces of the gate layer main body portion are formed as inclined surfaces in which the width of the gate layer main body portion gradually decreases toward the gate electrode side, and both side surfaces of the upper protruding portion are formed as inclined surfaces in which the width of the gate layer main body portion gradually decreases toward the gate electrode side.

In one embodiment of the present invention, an average inclination angle of a side surface of the gate layer main body portion is different from an average inclination angle of a side surface of the upper protruding portion.

In one embodiment of the present invention, the upper surfaces of the two side portions of the gate layer main body portion, which connect the lower edges of the two side surfaces of the upper protruding portion and the upper edges of the corresponding side surfaces of the gate layer main body portion, are formed as inclined surfaces that gradually increase in thickness toward the center of the width of the gate layer main body portion.

In one embodiment of the present invention, the gate electrode is formed to cover the entire top surface of the upper protruding portion.

In one embodiment of the present invention, both side edges of the lower surface of the gate electrode are retreated inward from the corresponding side edges of the top surface of the upper protruding portion in a plan view.

In one embodiment of the present invention, the 1 st nitride semiconductor layer is composed of a GaN layer, and the 2 nd nitride semiconductor layer is composed of Al_xGa_1-xN (0 < x ≦ 1) layer, and the semiconductor gate layer is composed of a p-type GaN layer.

In one embodiment of the present invention, if the semiconductor gate layer is set to a 1 st semiconductor gate layer, a 2 nd semiconductor gate layer having a larger band gap than the 1 st semiconductor gate layer and including a nitride semiconductor is interposed between the 1 st semiconductor gate layer and the gate electrode.

In one embodiment of the present invention, if the semiconductor gate layer is set to a 1 st semiconductor gate layer, a 2 nd semiconductor gate layer including a nitride semiconductor is interposed between the 1 st semiconductor gate layer and the gate electrode, the 2 nd semiconductor gate layer being made of Al_yGa_1-yN (0 ≦ y < 1, y ≦ x).

In one embodiment of the present invention, the gate electrode is formed of a single Ti film, a TiN film, or a TiW film, or a composite film including any combination of 2 or more of these films.

In one embodiment of the present invention, the semiconductor device further includes a 3 rd dielectric layer formed on an upper surface of the gate electrode.

In one embodiment of the present invention, the semiconductor device further includes a 3 rd dielectric layer formed on an upper surface of the gate electrode, wherein a thickness of the 3 rd dielectric layer is greater than a thickness of the 2 nd dielectric layer.

In one embodiment of the present invention, the 1 st dielectric layer and the 2 nd dielectric layer are made of SiN film or SiO film₂Film, SiON film, Al₂O₃Any one of a film, an AlN film, and an AlON film or a composite film including any combination of 2 or more of them.

In one embodiment of the present invention, the 1 st dielectric layer and the 2 nd dielectric layer are made of the same material.

In one embodiment of the present invention, the 1 st dielectric layer and the 2 nd dielectric layer are made of different materials.

One embodiment of the present invention provides a method for manufacturing a nitride semiconductor device, including the steps of: forming a 1 st nitride semiconductor layer constituting an electron transit layer, a 2 nd nitride semiconductor layer constituting an electron supply layer, and a semiconductor gate material film including a nitride semiconductor containing acceptor type impurities in this order on a substrate; forming a gate electrode film on the semiconductor gate material film; selectively forming a top dielectric film on the gate electrode film; forming a gate electrode including the gate electrode film, a top wall disposed on the gate electrode and including the dielectric film for a cap, and the semiconductor gate material film having an upper protruding portion directly below the gate electrode by selectively removing the gate electrode film and the semiconductor gate material film by dry etching using the dielectric film for a cap as a mask until the thickness of the semiconductor gate material film is halfway; forming a dielectric film for side portions covering exposed surfaces of the top wall, the gate electrode, and the semiconductor gate material film; forming a side wall composed of the dielectric film for side portions and covering side surfaces of the top wall, the gate electrode, and the upper protruding portion by removing portions of the dielectric film for side portions other than portions covering side surfaces of the top wall, the gate electrode film, and the upper protruding portion by etching; and a semiconductor gate layer forming step of forming a semiconductor gate layer including a gate layer body formed on the 2 nd nitride semiconductor layer and the upper protruding portion formed on the width intermediate portion of the upper surface of the gate layer body by selectively removing the semiconductor gate material film by dry etching using the top wall and the side wall as masks until the surface of the 2 nd nitride semiconductor layer is exposed.

According to this manufacturing method, it is possible to manufacture a nitride semiconductor device in which gate leakage current can be reduced and a decrease in gate rated voltage, which is the maximum value that can be stably applied to a gate, can be suppressed.

In an embodiment of the present invention, the method further includes the following steps: forming a passivation film covering the top wall, the side wall, and an exposed surface of the 2 nd nitride semiconductor layer after the semiconductor gate layer forming step; forming a source contact hole and a drain contact hole which penetrate through the passivation film in the thickness direction on the passivation film; and forming a source electrode and a drain electrode which penetrate the source contact hole and the drain contact hole, respectively, and are in ohmic contact with the 2 nd nitride semiconductor layer.

These and still other objects, features and effects of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings.

Drawings

Fig. 1 is a cross-sectional view for explaining the structure of a nitride semiconductor device according to embodiment 1 of the present invention.

Fig. 2A is a cross-sectional view showing an example of a manufacturing process of the nitride semiconductor device of fig. 1.

Fig. 2B is a sectional view showing the next step of fig. 2A.

Fig. 2C is a sectional view showing the next step of fig. 2B.

Fig. 2D is a sectional view showing the next step of fig. 2C.

Fig. 2E is a sectional view showing the next step of fig. 2D.

Fig. 2F is a sectional view showing the next step of fig. 2E.

Fig. 2G is a sectional view showing the next step of fig. 2F.

Fig. 2H is a sectional view showing the next step of fig. 2G.

Fig. 3 is a cross-sectional view showing a nitride semiconductor device of a comparative example.

Fig. 4 is a cross-sectional view for explaining the structure of the nitride semiconductor device according to embodiment 2 of the present invention.

Fig. 5 is a cross-sectional view for explaining the structure of the nitride semiconductor device according to embodiment 3 of the present invention.

Fig. 6 is a cross-sectional view for explaining the structure of the nitride semiconductor device according to embodiment 4 of the present invention.

Fig. 7 is a cross-sectional view for explaining the structure of the nitride semiconductor device according to embodiment 5 of the present invention.

Fig. 8 is a cross-sectional view for explaining the structure of the nitride semiconductor device according to embodiment 6 of the present invention.

Fig. 9 is a cross-sectional view for explaining the structure of the nitride semiconductor device according to embodiment 7 of the present invention.

Fig. 10 is a cross-sectional view for explaining the structure of the nitride semiconductor device according to embodiment 8 of the present invention.

Detailed Description

Fig. 1 is a cross-sectional view for explaining the structure of a nitride semiconductor device according to embodiment 1 of the present invention.

The nitride semiconductor device 1 includes: a substrate 2; a buffer layer 3 formed on the surface of the substrate 2; a 1 st nitride semiconductor layer 4 epitaxially grown on the buffer layer 3; a 2 nd nitride semiconductor layer 5 epitaxially grown on the 1 st nitride semiconductor layer 4; and a gate portion 20 formed on the 2 nd nitride semiconductor layer 5.

Further, the nitride semiconductor device 1 includes a 2 nd nitride semiconductor layer 5 and a passivation film (2 nd dielectric film) 6 covering the gate portion 20. Further, the nitride semiconductor device 1 includes a source electrode 9 and a drain electrode 10 that penetrate through a source contact hole 7 and a drain contact hole 8 formed in the passivation film 6 and make ohmic contact with the 2 nd nitride semiconductor layer 5. The source electrode 9 and the drain electrode 10 are disposed with a space therebetween. The source electrode 9 is formed so as to cover the gate portion 20.

The substrate 2 may be, for example, a low-resistance silicon substrate. The low-resistance silicon substrate may be a p-type substrate having a resistivity of 0.001 Ω mm to 0.5 Ω mm (more specifically, about 0.01 Ω mm to 0.1 Ω mm), for example. Substrate 2 may be a low-resistance SiC substrate, a low-resistance GaN substrate, or the like, in addition to a low-resistance silicon substrate. The thickness of the substrate 2 is, for example, about 650 μm in a semiconductor process, and is ground to about 300 μm or less in a pre-stage of chip formation. The substrate 2 is electrically connected to the source electrode 9.

In this embodiment, the buffer layer 3 is formed of a multilayer buffer layer in which a plurality of nitride semiconductor films are stacked. In this embodiment, the buffer layer 3 is composed of a 1 st buffer layer (not shown) including an AlN film in contact with the surface of the substrate 2, and a 2 nd buffer layer (not shown) including an AlN/AlGaN superlattice layer laminated on the surface of the 1 st buffer layer (the surface opposite to the substrate 2). The film thickness of the 1 st buffer layer is about 100nm to 500 nm. The film thickness of the 2 nd buffer layer is about 500nm to 2 μm. The buffer layer 3 may be formed of, for example, a single film or a composite film of AlGaN.

The 1 st nitride semiconductor layer 4 constitutes an electron travel layer. In this embodiment, the 1 st nitride semiconductor layer 4 is composed of a GaN layer and has a thickness of about 0.5 μm to 2 μm. In addition, in order to suppress the leakage current flowing through the 1 st nitride semiconductor layer 4, the leakage current is also suppressedImpurities for making the surface region other than the surface region semi-insulating may be introduced. In this case, the concentration of the impurity is preferably 4 × 10¹⁶cm^-3The above. The impurity is, for example, C or Fe.

The 2 nd nitride semiconductor layer 5 constitutes an electron supply layer. The 2 nd nitride semiconductor layer 5 includes a nitride semiconductor having a larger band gap than the 1 st nitride semiconductor layer 4. Specifically, the 2 nd nitride semiconductor layer 5 includes a nitride semiconductor having a higher Al composition than the 1 st nitride semiconductor layer 4. In the nitride semiconductor, the higher the Al composition, the larger the band gap. In this embodiment, the 2 nd nitride semiconductor layer 5 is made of Al_xGa_1-xN layer (x is more than 0 and less than or equal to 1) with a thickness of about 5nm to 15 nm.

Thus, the 1 st nitride semiconductor layer (electron transit layer) 4 and the 2 nd nitride semiconductor layer (electron supply layer) 5 include nitride semiconductors different in band gap (Al composition), and lattice mismatch is generated therebetween. Further, by the spontaneous polarization of the 1 st nitride semiconductor layer 4 and the 2 nd nitride semiconductor layer 5 and the piezoelectric polarization due to lattice mismatch therebetween, the energy level of the conduction band of the 1 st nitride semiconductor layer 4 at the interface between the 1 st nitride semiconductor layer 4 and the 2 nd nitride semiconductor layer 5 is lower than the fermi level. Thereby, in the 1 st nitride semiconductor layer 4, at a position close to the interface between the 1 st nitride semiconductor layer 4 and the 2 nd nitride semiconductor layer 5 (for example, the number of the interfaceLeft and right distance), the two-dimensional electron gas (2DEG)11 is diffused.

Gate portion 20 includes a semiconductor gate layer 21 in the shape of a ridge epitaxially grown on nitride-2 semiconductor layer 5, and a gate electrode 22 formed on semiconductor gate layer 21. The gate portion 20 is disposed biased against the source contact hole 7.

In this embodiment, the semiconductor gate layer 21 includes a gate layer main body portion 211 having a substantially rectangular cross section, and an upper protruding portion 212 formed on a widthwise intermediate portion of an upper surface of the gate layer main body portion 211 and having a substantially rectangular cross section. A step is formed between the top surface (upper surface) 212b of the upper protruding portion 212 and the upper surface 211b of one side of the gate layer main body portion 211, and a step is formed between the top surface 212b of the upper protruding portion 212 and the upper surface 211b of the other side of the gate layer main body portion 211.

The upper surface 211b of one side portion of the gate layer main body portion 211 connects the lower edge of one side surface 212a of the upper protruding portion 212 to the upper edge of one side surface 211a of the gate layer main body portion 211. The upper surface 211b of the other side portion of the gate layer main body portion 211 connects the lower edge of the other side surface 212a of the upper protruding portion 212 with the upper edge of the other side surface 211a of the gate layer main body portion 211.

A gate electrode 22 is formed on the top surface of the upper protruding portion 212. In this embodiment, the gate electrode 22 is formed so as to cover the entire top surface 212b of the upper protruding portion 212.

The semiconductor gate layer 21 includes a nitride semiconductor doped with acceptor-type impurities. In this embodiment, the semiconductor gate layer 21 is composed of a GaN layer (p-type GaN layer) doped with acceptor-type impurities. The film thickness of the semiconductor gate layer 21 is preferably 50nm or more, and more preferably 70nm or more, in order to set the threshold voltage to an appropriate value.

In this embodiment, the thickness of the upper protruding portion 212 is thinner than that of the gate layer main body portion 211. The thickness of the gate layer main body portion 211 is about 40nm to 60nm, and the thickness of the upper protruding portion 212 is about 10nm to 40 nm.

The concentration of the acceptor-type impurity implanted into the semiconductor gate layer 21 is preferably 1 × 10¹⁹cm^-3The above. In this embodiment, the acceptor-type impurity is Mg (magnesium). The acceptor-type impurity may be an acceptor-type impurity other than Mg, such as Zn (zinc). The semiconductor gate layer 21 is provided to cancel out the two-dimensional electron gas 11 generated in the vicinity of the interface between the 1 st nitride semiconductor layer 4 (electron transit layer) and the 2 nd nitride semiconductor layer 5 (electron supply layer) in the region directly below the gate portion 20.

The gate electrode 22 is schottky-bonded to the upper protruding portion 212 of the semiconductor gate layer 21. The gate electrode 22 comprises TiN. The thickness of the gate electrode 22 is about 50nm to 150 nm. The gate electrode 22 may be formed of a single Ti film, a TiN film, or a TiW film, or a composite film including any combination of 2 or more of these films.

The gate portion 20 further includes a top wall (3 rd dielectric film) 23 covering the upper surface of the gate electrode 22, and sidewalls (1 st dielectric film) 24 respectively covering the top wall 23 and both side surfaces 212a of the upper protruding portion 212. Each sidewall 24 also covers the upper surface 211b of the corresponding side portion in the gate layer main body portion 211. In this embodiment, the top wall 23 and the side wall 24 are made of SiN film.

The passivation film 6 covers the surface of the 2 nd nitride semiconductor layer 5 (excluding the regions facing the contact holes 7 and 8) and the side surfaces and the surface of the gate portion 20. In this embodiment, the passivation film 6 is composed of a SiN film.

The thickness of the top wall 23 is about 50nm to 200 nm. The thickness of the sidewall 24 is about 110nm to 390 nm. The thickness of the passivation film 6 is about 50nm to 200 nm. In order to suppress gate leakage current from the upper surface of the gate electrode 22, the thickness of the top wall 23 is preferably larger than the thickness of the passivation film 6.

The top wall 23, the side wall 24 and the passivation film 6 may be made of SiN film or SiO film₂Film, SiON film, Al₂O₃Any one of a film, an AlN film, and an AlON film or a composite film including any combination of 2 or more of them. The side wall 24 and the passivation film 6 may be formed of the same material or different materials.

The source electrode 9 and the drain electrode 10 include, for example, a 1 st metal layer (ohmic metal layer) in ohmic contact with the 2 nd nitride semiconductor layer 5, a 2 nd metal layer (main electrode metal layer) laminated on the 1 st metal layer, a 3 rd metal layer (adhesion layer) laminated on the 2 nd metal layer, and a 4 th metal layer (barrier metal layer) laminated on the 3 rd metal layer. The 1 st metal layer is, for example, a Ti layer having a thickness of about 10nm to 20 nm. The 2 nd metal layer is, for example, an Al layer having a thickness of about 100nm to 300 nm. The 3 rd metal layer is, for example, a Ti layer having a thickness of about 10nm to 20 nm. The 4 th metal layer is, for example, a TiN layer having a thickness of about 10nm to 50 nm.

In this nitride semiconductor device 1, a 2 nd nitride semiconductor layer 5 (electron supply layer) having a different band gap (Al composition) is formed on a 1 st nitride semiconductor layer 4 (electron transit layer) to form a heterojunction. Thereby, the two-dimensional electron gas 11 is formed in the 1 st nitride semiconductor layer 4 in the vicinity of the interface between the 1 st nitride semiconductor layer 4 and the 2 nd nitride semiconductor layer 5, and the HEMT using the two-dimensional electron gas 11 as a channel is formed. The gate electrode 22 faces the 2 nd nitride semiconductor layer 5 with the semiconductor gate layer 21 interposed therebetween.

The energy levels of the 1 st nitride semiconductor layer 4 and the 2 nd nitride semiconductor layer 5 are raised below the gate electrode 22 by the ionization acceptors included in the semiconductor gate layer 21 made of a p-type GaN layer. Therefore, the energy level of the conduction band at the heterojunction interface between the 1 st nitride semiconductor layer 4 and the 2 nd nitride semiconductor layer 5 is greater than the fermi level. Therefore, directly below the gate electrode 22 (gate portion 20), the two-dimensional electron gas 11 due to the spontaneous polarization of the 1 st nitride semiconductor layer 4 and the 2 nd nitride semiconductor layer 5 and the piezoelectric polarization due to the lattice mismatch thereof is not formed.

Thus, when no bias is applied to the gate electrode 22 (zero bias), the passage of the two-dimensional electron gas 11 is blocked directly below the gate electrode 22. Thus, a normally-off HEMT is realized. If an appropriate on-voltage (for example, 5V) is applied to the gate electrode 22, a channel is induced in the 1 st nitride semiconductor layer 4 directly below the gate electrode 22, connecting the two-dimensional electron gas 11 on both sides of the gate electrode 22. Thereby, the source-drain is conducted.

In use, for example, a specific voltage (for example, 10V to 500V) that is positive on the drain electrode 10 side is applied between the source electrode 9 and the drain electrode 10. In this state, an off voltage (0V) or an on voltage (5V) is applied to the gate electrode 22 with the source electrode 9 as a reference potential (0V).

Fig. 2A to 2I are cross-sectional views for explaining an example of the manufacturing process of the nitride semiconductor device 1, and show cross-sectional structures at a plurality of stages in the manufacturing process.

First, as shown in fig. 2A, a buffer layer 3, a 1 st nitride semiconductor layer (electron transit layer) 4, and a 2 nd nitride semiconductor layer (electron supply layer) 5 are epitaxially grown on a substrate 2 by MOCVD (Metal Organic Chemical Vapor Deposition) method. Further, a semiconductor gate material film 71, which is a material film of the semiconductor gate layer 21, is epitaxially grown on the 2 nd nitride semiconductor layer 5 by MOCVD.

Next, as shown in fig. 2B, a gate electrode film 72, which is a material film of the gate electrode 22, is formed by sputtering so as to cover the entire exposed surface. Then, on the gate electrode film 72, a 3 rd dielectric film 73 as a material of the top wall 23 is formed so as to cover a region where the gate electrode is to be formed. The 3 rd dielectric film 73 includes, for example, SiN.

Next, as shown in fig. 2C, the gate electrode film 72 and the semiconductor gate material film 71 are selectively removed by dry etching using the 3 rd dielectric film 73 as a mask until the thickness of the semiconductor gate material film 71 is halfway. And is etched. Thereby, the gate electrode 22 including the gate electrode film 72, the ceiling wall 23 disposed on the gate electrode 22 and including the 3 rd dielectric film 73, and the semiconductor gate material film 71 having the upper protruding portion 212 directly below the gate electrode 22 are formed.

Next, as shown in fig. 2D, the 1 st dielectric film 74 which is a material of the sidewall 24 is formed so as to cover the exposed surfaces of the top wall 23, the gate electrode 22, and the semiconductor gate material film 71. The 1 st dielectric film 74 includes, for example, SiN.

Next, as shown in fig. 2E, the portion of the 1 st dielectric film 74 other than the portion covering the top wall 23, the gate electrode 22, and the side surface 212a of the upper protruding portion 212 is removed by anisotropic dry etching. Thereby, the sidewall 24 including the 1 st dielectric film 74 and covering the top wall 23, the gate electrode 22, and the side surface 212a of the upper protruding portion 212 is formed.

Next, as shown in fig. 2F, semiconductor gate material film 71 is selectively removed by dry etching using top wall 23 and side wall 24 as masks until the surface of 2 nd nitride semiconductor layer 5 is exposed. Thereby, the semiconductor gate layer 21 including the gate layer main body portion 211 formed on the 2 nd nitride semiconductor layer 5 and the upper protruding portion 212 formed on the width intermediate portion of the upper surface of the gate layer main body is formed. Thereby, the gate portion 20 including the semiconductor gate layer 21, the gate electrode 22, the top wall 23, and the side wall 24 is formed.

Next, as shown in fig. 2G, the passivation film 6 is formed so as to cover the entire exposed surface. The passivation film 6 includes, for example, SiN. Then, source contact hole 7 and drain contact hole 8 reaching nitride semiconductor layer 2 are formed in passivation film 6.

Next, as shown in fig. 2H, a source/drain electrode film 75 is formed so as to cover the entire exposed surface.

Finally, the source/drain electrode film 75 is patterned by photolithography and etching, thereby forming a source electrode 9 and a drain electrode 10 in ohmic contact with the 2 nd nitride semiconductor layer 5. In this way, the nitride semiconductor device 1 having the structure shown in fig. 1 is obtained.

Fig. 3 is a cross-sectional view showing a nitride semiconductor device 101 of a comparative example. In fig. 3, the same reference numerals as in fig. 1 are given to parts corresponding to those in fig. 1. Nitride semiconductor device 101 of the comparative example is different in shape of semiconductor gate layer 21 from nitride semiconductor device 1 of embodiment 1. The cross-sectional shape of the semiconductor gate layer 21 of the comparative example is a rectangle having the same width as the main body portion 211 of fig. 1 and the same thickness as the semiconductor gate layer 21 of fig. 1. Further, a gate electrode 22 is formed entirely on the upper surface of the semiconductor gate layer 21. In this comparative example, a ceiling wall covering the upper surface of the gate electrode 22 was also formed, but the side wall 24 was not formed.

In the nitride semiconductor device 101 of the comparative example, since an electric field is likely to concentrate at the contact portion C between the upper surface of the semiconductor gate layer 21 and the side edge of the lower surface of the gate electrode 22, the gate leakage current from the width direction end C of the gate electrode 22 becomes large.

In contrast, in nitride semiconductor device 1 according to embodiment 1, the electric field is concentrated at a portion a of semiconductor gate layer 21 where upper surface 211b of gate layer main body portion 211 intersects with side surface 212a of upper protruding portion 212 (see fig. 1). That is, in nitride semiconductor device 1 according to embodiment 1, the position where the electric field is concentrated can be made distant from width direction end B of the lower surface of gate electrode 22. This can suppress a gate leakage current from the width direction end B of the gate electrode 22. Thus, a nitride semiconductor device can be realized in which gate leakage current can be reduced and a reduction in gate rated voltage, which is the maximum value that can be stably applied to a gate, can be suppressed.

Further, since the thickness of the upper protruding portion 212 of the semiconductor gate layer 21 is thinner than the thickness of the gate layer main body portion 211 of the semiconductor gate layer 21, the electric field is easily uniform over the entire lateral area in the semiconductor gate layer 21. Therefore, the density of the two-dimensional electron gas 11 immediately below the gate portion 20 is also easily made uniform, and therefore, an increase in on-resistance can be suppressed.

Since the gate electrode 22 is formed so as to cover the entire top surface 212b of the upper protruding portion 212, the electric field in the vicinity of the boundary between the gate electrode 22 and the upper protruding portion 212 is substantially uniform over the entire lateral direction. Thus, since there is no region where the schottky barrier at both sides of the gate electrode 22 is lowered, the gate leakage current can be reduced, and a reduction in the gate rated voltage, which is the maximum value that can be stably applied to the gate electrode, can be suppressed.

Fig. 4 to 10 are cross-sectional views for explaining the structures of nitride semiconductor devices 1A to 1F according to embodiments 2 to 8 of the present invention. In fig. 4 to 10, the same reference numerals as in fig. 1 are given to the parts corresponding to the parts of fig. 1.

Referring to fig. 4, in nitride semiconductor device 1A of embodiment 2, the width of gate electrode 22 is narrower than the width of protruding portion 212 above semiconductor gate layer 21. Further, the gate electrode 22 is formed on the width middle portion of the top surface 212b of the upper protruding portion 212. Therefore, both side edges of the lower surface of the gate electrode 22 are retreated inward from the corresponding side edges of the top surface 212b of the upper protruding portion 212 in a plan view.

In nitride semiconductor device 1A according to embodiment 2, since the resistance from both side edges of gate electrode 22 to the side surfaces of semiconductor gate layer 21 increases, the gate leakage current passing through the path near the side walls of semiconductor gate layer 21 can be reduced.

Referring to fig. 5, in nitride semiconductor device 1B according to embodiment 3, the thickness of upper protruding portion 212 of semiconductor gate layer 21 is greater than the thickness of gate layer main body portion 211 of semiconductor gate layer 21. In this case, the thickness of the gate layer main body portion 211 is about 20nm to 40nm, and the thickness of the upper protruding portion 212 is about 30nm to 60 m.

In nitride semiconductor device 1B according to embodiment 3, since portion a where the electric field can be concentrated is located farther from end B in the width direction of the lower surface of gate electrode 22 than in nitride semiconductor device 1 according to embodiment 1, an increase in gate leakage current at the junction between upper protruding portion 212 and gate electrode 22 can be suppressed.

Referring to fig. 6 and 7, in nitride semiconductor devices 1C and 1D according to embodiments 4 and 5 of the present invention, both side surfaces 211a of gate layer main body portion 211 are formed as inclined surfaces in which the width of gate layer main body portion 211 gradually decreases toward gate electrode 22. Both side surfaces 212a of the upper protruding portion 212 are formed as inclined surfaces in which the width of the upper protruding portion 212 gradually decreases toward the gate electrode 22.

In nitride semiconductor device 1C of embodiment 4, the average inclination angle of side surface 211a of gate layer main body portion 211 with respect to the surface of 2 nd nitride semiconductor layer 5 is larger than the average inclination angle of side surface 212a of upper protruding portion 212 with respect to the surface of 2 nd nitride semiconductor layer 5.

In nitride semiconductor device 1D of embodiment 5, the average inclination angle of side surface 211a of gate layer main body portion 211 with respect to the surface of 2 nd nitride semiconductor layer 5 is smaller than the average inclination angle of side surface 212a of upper protruding portion 212 with respect to the surface of 2 nd nitride semiconductor layer 5.

The larger one of the average inclination angle of the side surface 211a of the gate layer main body portion 211 and the average inclination angle of the side surface 212a of the upper protruding portion 212 means that etching conditions for forming the structure are different, but since a region where plasma damage is small (a region with high resistance) exists in the middle of the side surface of the gate layer, the gate leakage current can be reduced, and the decrease in the gate rated voltage which is the maximum value that can be stably applied to the gate electrode can be suppressed.

Referring to fig. 8, in nitride semiconductor device 1E according to embodiment 6 of the present invention, upper surfaces 211b of both side portions of gate layer main body portion 211, which connect lower edges of both side surfaces 212a of upper protruding portion 212 to upper edges of corresponding side surfaces 211a of gate layer main body portion 211, are formed as inclined surfaces in which the thickness of both side portions of gate layer main body portion 211 becomes thicker toward the center of the width of gate layer main body portion 211.

In nitride semiconductor device 1E according to embodiment 6, as compared with nitride semiconductor device 1 according to embodiment 1, the electric field concentration at site a where the electric field is concentrated can be relaxed, so that the gate leakage current can be reduced, and the decrease in the gate rated voltage, which is the maximum value stably applied to the gate, can be suppressed.

Referring to fig. 9, in nitride semiconductor device 1F according to embodiment 7 of the present invention, if semiconductor gate layer 21 is set to 1 st semiconductor gate layer 21, 2 nd semiconductor gate layer 25 including a nitride semiconductor is interposed between 1 st semiconductor gate layer 21 and gate electrode 22.

The 2 nd semiconductor gate layer 25 includes a nitride semiconductor having a larger band gap than the 1 st semiconductor gate layer 21. In embodiment 7, the 2 nd semiconductor gate layer 25 is made of Al_yGa_1-yN (0 ≦ y < 1, y ≦ x) layer having a thickness of about 10 nm. In the case where the acceptor-type impurity implanted into the 1 st semiconductor gate layer 21 is Mg, Mg is implanted into the 2 nd semiconductor gate layer 25 by the memory effect.

In nitride semiconductor device 1E according to embodiment 7, barriers for holes are formed in the valence band at the boundary between 1 st semiconductor gate layer (pGaN)21 and 2 nd semiconductor gate layer (AlGaN) 25. Thus, since injection of holes from the gate electrode 22 into the 1 st semiconductor gate layer (pGaN)21 can be suppressed, the gate leakage current can be further reduced, and a decrease in the gate rated voltage, which is the maximum value that can be stably applied to the gate, can be suppressed.

Referring to fig. 10, nitride semiconductor device 1G according to embodiment 8 of the present invention is different from nitride semiconductor device 1 of fig. 1 in that top wall 23 and side walls 24 are not formed. Which is composed of a semiconductor gate layer 21 including an upper protruding portion 211 and an upper protruding portion 212, and a gate electrode 22 formed on the upper protruding portion 212.

While the embodiments 1 to 7 of the present invention have been described above, the present invention may be further implemented in other embodiments. For example, in the above embodiment, silicon is exemplified as an example of the material of the substrate 2, but any substrate material such as a sapphire substrate or an insulating substrate may be applied.

The embodiments of the present invention have been described in detail, but these are merely specific examples used for clarifying technical contents of the present invention, and the present invention should not be construed as being limited to these specific examples, and the scope of the present invention is defined only by the appended claims.

The present application corresponds to application No. 2019-.

[ description of symbols ]

1. 1A-1G nitride semiconductor device

2 substrate

3 buffer layer

4 1 st nitride semiconductor layer

5 nd 2 nd nitride semiconductor layer

6 passivation film (No. 2 dielectric film)

7 source contact hole

8 drain contact hole

9 source electrode

10 drain electrode

11 two-dimensional electron gas (2DEG)

20 grid part

21 semiconductor gate layer (1 st semiconductor gate layer)

211 gate layer body part

211a side surface

211b upper surface

212 upper projection

212a side surface

212b Top surface (Upper surface)

22 gate electrode

23 ceiling wall

24 side wall

25 nd 2 nd semiconductor gate layer

71 film of semiconductor gate material

72 gate electrode film

73 rd 3 dielectric film

74 st dielectric film

75 a source/drain electrode film.