阅读说明：本技术 存储器及其操作方法 (Memory and operation method thereof ) 是由 金多厚 于 2021-04-16 设计创作，主要内容包括：本申请涉及存储器及其操作方法。一种操作存储器的方法包括读取包括第一数据和第一链接的第一节点；将第一数据写入数据采集区域；将写入数据采集区域中的第一数据的第一采集链接更新到数据采集区域中的位置；读取与第一链接对应的第二节点,第二节点包括第二数据和第二链接；以及将第二数据写入数据采集区域中的由第一采集链接指定的位置。(The present application relates to a memory and a method of operating the same. A method of operating a memory includes reading a first node including first data and a first link; writing the first data into a data acquisition area; updating a first acquisition link of first data written in the data acquisition area to a position in the data acquisition area; reading a second node corresponding to the first link, the second node including second data and a second link; and writing the second data to the location in the data acquisition area specified by the first acquisition link.)

1. A method of operating a memory, the method comprising:

reading a first node, the first node comprising first data and a first link;

writing the first data into a data acquisition area;

updating a first acquisition link written to the first data in the data acquisition area to a location in the data acquisition area;

reading a second node corresponding to the first link, the second node comprising second data and a second link; and

writing the second data to a location in the data acquisition area specified by the first acquisition link.

2. The method of claim 1, further comprising: updating a second acquisition link of the second data written in the data acquisition area to a location in the data acquisition area.

3. The method of claim 1, further comprising:

identifying that the second link does not specify a location in the memory; and

updating a second acquisition link of the second data written in the data acquisition area to the same value as the second link.

4. The method of claim 2, further comprising:

reading a third node corresponding to the second link, the third node including third data and a third link; and

writing the third data to a location in the data acquisition area specified by the second acquisition link.

5. The method of claim 4, further comprising: updating a third acquisition link written to the third data in the data acquisition area to a location in the data acquisition area.

6. The method of claim 4, further comprising:

identifying that the third link does not specify a location in the memory; and

updating a third acquisition link of the third data written in the data acquisition area to the same value as the third link.

7. The method of claim 1, further comprising:

ensuring the data acquisition area before reading the first data; and

it is determined to perform defragmentation.

8. A memory, comprising:

a normal region including a plurality of memory cells;

a data acquisition area comprising a plurality of storage cells; and

a defragmentation circuit which reads the linked plurality of data from the normal area, writes the plurality of data to the data acquisition area, and controls the normal area and the data acquisition area to update the link so that the plurality of data written to the data acquisition area are linked in the data acquisition area.

9. The memory of claim 8, wherein the defragmentation circuit:

reading a first node from the normal area, the first node including first data and a first link;

writing the first data into the data acquisition area;

updating a first acquisition link written to the first data in the data acquisition area to a location in the data acquisition area;

reading a second node corresponding to the first link from the normal area, the second node including second data and a second link; and

writing the second data to a location in the data acquisition area specified by the first acquisition link.

10. The memory according to claim 9, wherein the memory further comprises a first memory cell,

wherein the defragmentation circuit updates a second acquisition link written to the second data in the data acquisition area to a location in the data acquisition area.

11. The memory of claim 8, wherein the defragmentation circuit comprises:

a register circuit for storing information relating to a defragmentation operation;

an address translator for translating the link read from the normal area into a memory address; and

a controller for controlling the defragmentation operation.

12. The memory of claim 11, wherein the register circuitry comprises:

a configuration register for storing configuration information;

an operation control register for storing operation control information; and

and the result register is used for storing result information.

13. The memory of claim 12, wherein the configuration information comprises:

link header address information corresponding to an address of a header node among a plurality of nodes linked in the normal area;

node size information;

information indicating a link position in a node;

information indicating the size of an address in a link;

information indicating the number of nodes to be collected;

system memory address offset information; and

data collection area enabling information.

14. The memory of claim 12, wherein the operation control information comprises:

defragmentation start enable information; and

defragmentation termination enable information.

15. The memory of claim 12, wherein the result information comprises:

information indicating the number of nodes collected;

indicating the information of the completion of the acquisition; and

data acquisition area usage information.

16. The memory of claim 11, further comprising an address buffer to store memory addresses translated by the address translator.

17. A memory, comprising:

the storage unit array comprises a normal area and a data acquisition area, wherein the normal area stores a plurality of scattered nodes comprising a first node and a second node, the first node is linked to the second node, and the size of the data acquisition area is smaller than that of the normal area; and

circuitry configured to: reading data of the first node from the normal area, writing the data of the first node to a first area of the data acquisition area, linking the first area to a second area adjacent to the first area, reading data of the second node from the normal area, and writing the data of the second node to the second area.

Technical Field

The present disclosure relates to memory.

Background

Big data involves the analysis of large amounts of data, the processing of which involves more of various database applications. Data is managed in a data structure type suitable for its use. There are generally two types of data structures: array type and link type.

In the array type data structure, a certain size of area in the (secure) memory can be secured in advance, and data is stored only in the area for future use. Fig. 1 is a diagram illustrating an example in which data is stored in an array type data structure in a memory cell array. In fig. 1, 101 denotes an area in which data is stored.

In a linked data structure, information about the manner in which a data item is associated with its predecessor (predecessor) or successor (successor) data item is stored along with the data item. The linking data structure has data items linked together via the addresses of its predecessors or successors and allows more data items to be added simply by changing the addresses only, thereby eliminating the need to specify the size of the data for use in advance, while enabling data items to be added and deleted quickly. Thus, the linked data structure may be more suitable for handling large data whose domain is growing rapidly. Fig. 2 is a diagram illustrating an example in which data is stored in a link type data structure in a memory cell array. In fig. 2, 201 to 209 represent nodes linked together. As can be seen from fig. 2, the nodes 201 to 209 are dispersed in different areas of the memory. Fig. 3 is a diagram showing the internal contents of the nodes 201 to 209. The nodes 201 to 209 may include DATA items DATA1 to DATA9, respectively, and LINKs LINK1 to LINK9, respectively, each LINK indicating a location of its succeeding DATA item, respectively.

In the linked type, data items are scattered in different areas shown in fig. 2. Therefore, searching for subsequent data items by referencing links inside the node may take a long time, making it more likely that a cache miss (cache miss) will occur, thereby adversely affecting performance.

Disclosure of Invention

According to an embodiment of the present disclosure, there is provided a technique for preventing system performance from deteriorating using a link-type data structure.

According to an embodiment of the present disclosure, a method of operating a memory includes: reading a first node comprising first data and a first link; writing the first data into a data acquisition area; updating a first acquisition link of first data written in the data acquisition area to a position in the data acquisition area; reading a second node corresponding to the first link, the second node including second data and a second link; and writing the second data to the location in the data acquisition area specified by the first acquisition link.

According to an embodiment of the present disclosure, a memory includes: a normal region including a plurality of memory cells; a data acquisition area comprising a plurality of storage cells; and a defragmentation circuit which reads the linked plurality of data from the normal area, writes the plurality of data to the data acquisition area, and controls the normal area and the data acquisition area to update the link so that the plurality of data written to the data acquisition area are linked in the data acquisition area.

According to an embodiment of the present disclosure, a memory includes: a storage cell array including a normal area storing a plurality of distributed nodes including first nodes and second nodes, the first nodes being linked to the second nodes, and a data acquisition area having a size smaller than that of the normal area; and circuitry configured to: the method includes reading data of a first node from a normal area, writing the data of the first node to a first area of a data acquisition area, linking the first area to a second area adjacent to the first area, reading data of a second node from the normal area, and writing the data of the second node to the second area.

According to the embodiments of the present disclosure, it is possible to prevent the performance degradation of a system using a link-type data structure.

Drawings

Fig. 1 is a diagram showing an example in which data is stored in an array type data structure in a memory cell array;

fig. 2 is a diagram illustrating an example in which data is stored in a link type data structure in a memory cell array;

FIG. 3 is a diagram illustrating the internal contents of a node in a linked data structure;

fig. 4 is a diagram showing a configuration of a memory according to an embodiment of the present disclosure;

fig. 5 is a diagram showing a configuration of a register circuit;

FIG. 6 is a diagram illustrating an example defragmentation operation of a memory; and

fig. 7 is a diagram showing an example in which three nodes dispersed in a normal area are collected into a data collection area.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings to allow those of ordinary skill in the art to easily practice the present invention. Well-known components and information may be omitted from the following description. Throughout the specification and drawings, the same or substantially the same reference numerals are used to designate the same or substantially the same elements. Moreover, references throughout this specification to "an embodiment," "another embodiment," etc., do not necessarily refer to only one embodiment, and different references to any such phrases are not necessarily referring to the same embodiment. The term "embodiments" as used herein does not necessarily refer to all embodiments.

Fig. 4 is a diagram illustrating a configuration of a memory 400 according to an embodiment of the present disclosure.

Referring to fig. 4, the memory 400 may include a cell array 410 including a normal area 420 and a data acquisition area 430, a defragmentation circuit 440, an address buffer 450, a row circuit 460, and a column circuit 470.

The cell array 410 may include a normal area 420 and a data acquisition area 430. The data collection area 430 may be an area into which the defragmentation circuit 440 collects data scattered and stored in the normal area 420 through the defragmentation operation. The remaining area not designated as the data collection area 430 may belong to the normal area 420.

The row circuit 460 and the column circuit 470 may be circuits for accessing a memory cell selected by an address ADD in the cell array 410. In the cell array 410, memory cells corresponding to a row selected by the row circuit 460 and a column selected by the column circuit 470 can be accessed.

Defragmentation circuit 440 may perform defragmentation operations to collect data scattered and stored in normal area 420 and transfer or move such data to data collection area 430. Defragmentation circuit 440 may include register circuit 441, address translator 443, and controller 445.

Register circuitry 441 may store information related to defragmentation operations. Fig. 5 shows an example of the register circuit 441. Referring to fig. 5, register circuit 441 may include a configuration register 510, an operation control register 520, and a result register 530.

Configuration registers 510 may store configuration information. The configuration register 510 may include header address information (link header address) 511, node size information (node size) 512, information indicating the location of a link in a node (i.e., link location 513 in a node), information indicating the address size of a link (i.e., address size 514), information indicating the number of nodes to be collected (i.e., collection node number 515), system memory address offset information (i.e., system memory address offset 516), and data collection region enable information (i.e., collection region enable 517). The header address information 511 is associated with the address of the first one of the nodes to be acquired into the data acquisition area 430. The node size information 512 may indicate the size of one node. A node may include data and links. The node size information 512 may indicate the total size of the nodes including the data and the links. Link location information 513 in a node may indicate the location of the link in the node. Address size information 514 may indicate the size of the effective address in the link in the location indicated by information 513. The acquisition node number information 515 may indicate the number of nodes to be acquired by the defragmentation circuit 440. System memory address offset information 516 may indicate an offset between an address stored in a link and an address of memory 400. The address stored in the link may be a system address, and may include addresses of all devices capable of storing data in the system, such as a memory, a Hard Disk Drive (HDD), or a Solid State Drive (SSD). System memory address offset information 516 may indicate the range of addresses of memory 400 in the system address. The acquisition region enable information 517 is information that can secure (secure) the data acquisition region 430. When information 517 is enabled, data collection area 430 may be ensured. When the information 517 is disabled, the data acquisition region 430 may not exist in the cell array 410, and all regions in the cell array 410 may belong to the normal region 420. The information 511 to 517 of the configuration register 510 may be configured by the memory controller to control the memory 400.

The operation control register 520 may store operation control information. The operation control register 520 may store defragmentation start enable information 521 and defragmentation termination enable information 522. The defragmentation start enable information 521 may be information capable of starting a defragmentation operation of the memory 400. When the defragmentation start enable information 521 is enabled, the memory 400 may start the defragmentation operation. The defragmentation start enable information 521 may be configured by the memory controller. The memory controller may enable the defragmentation start enable information 521 during periods when access to the memory 400 is not required, thereby enabling the defragmentation operation to start. Defragmentation termination enable information 522 may be information that terminates the defragmentation operation of memory 400. When the defragmentation termination enable information 522 is enabled while the defragmentation operation of the memory 400 is performed, the defragmentation operation may be stopped. Defragmentation termination enable information 522 may be configured by the memory controller. When access to the memory 400 is required while performing a defragmentation operation of the memory 400, the memory controller may enable the defragmentation termination enable information 522.

Result register 530 may store result information. The result register 530 may store information (indicating the number of nodes acquired, i.e., the number of acquisition nodes 531, acquisition end information, i.e., acquisition completion 532, and data acquisition area usage information, i.e., acquisition area occupation size 533). The collection node number information 531 may indicate how many nodes the defragmentation operation has collected. In other words, information 531 may indicate the progress of the defragmentation operation. The end of acquisition information 532 may indicate whether the defragmentation operation has ended. The data collection area usage information 533 may indicate the usage amount of the data collection area 430. The result register 530 may store information 531, 532, and 533 related to the result of the progress of the defragmentation operation. Since the defragmentation operation is performed under the control of the controller 445, the controller 445 may update the information 531, 532, and 533 stored in the result register 530.

Referring back to fig. 4, the address translator 443 of the defragmentation circuit 440 may translate system addresses into memory addresses. The link included in the node read from the normal area 420 is a system address. Thus, these system addresses may need to be translated (or mapped) to memory addresses to access memory 440. The header address information 511 is also a system address. Therefore, in order to access the first node in the normal area 420 using the head address, it may be necessary to translate the head address, which is a system address, into a memory address using the address translator 443.

Controller 445 may control components within defragmentation circuit 440, as well as components external thereto, to perform defragmentation operations. In fig. 4, CONTROL may represent CONTROL of the controller 445. How the defragmentation operation is performed under the control of the controller 445 will be described below with reference to the drawings.

The address buffer 450 may store a memory address resulting from the translation by the address translator 443. The address ADD stored in the address buffer 450 may be used to access the cell array 410.

The memory 400 may be a main memory, such as a Dynamic Random Access Memory (DRAM). However, in another embodiment, the memory 400 may be a different class of memory.

Fig. 6 is a diagram illustrating an example of a defragmentation operation of the memory 400.

Referring to fig. 6, the configuration register 510 and the operation control register 520 of the register circuit 441 may be configured by the memory controller (601). In particular, when the defragmentation start enable information 521 in the operation control register 520 is enabled, the defragmentation operation can be started.

The address buffer 450 may be updated (603). Header address information 511 of configuration register 510 may be translated to a memory address by address translator 443 and address buffer 450 may be updated with the memory address.

The node of the normal area 420 can be read using the address ADD stored in the address buffer 450 (605). The nodes may include data and links.

The node data read in operation 605 may be written to the data acquisition region 430 (607). The link corresponding to the data stored in the data acquisition area may be updated (or written) (609). The link updated in operation 609 may specify a location, preferably an immediate location, in the data collection area 430. When the link included in the node read in operation 605 does not specify any location in the memory 400, the link updated in operation 609 may be the same as the link read in operation 605.

It may be determined whether the acquisition is complete (or finished) (611). The end of acquisition may be determined when any one of the following three conditions is satisfied: (1) the same number of nodes as the number of nodes indicated by the collection node number information 515 are collected into the data collection area 430; (2) defragmentation termination enable information 522 of the operation control register 520 is enabled; and/or (3) the link in the node read in operation 605 does not specify a location in memory 400. Since (1) indicates that all data has been collected, (2) indicates that the memory controller has instructed to stop the defragmentation operation, and (3) indicates that no further data can be collected, when any of the conditions (1) to (3) is satisfied, it can be determined that the collection is finished.

If it is determined that the acquisition is not completed ("no" in 611), operations 603 through 611 may be performed again. When operation 603 is performed again, the node link read in operation 605 may be translated by the address translator 443 and then updated to the address buffer 450.

When it is determined that the acquisition is complete (yes in 611), the result register 530 may be updated by the controller 445 (613).

Fig. 7 is a diagram showing an example in which three nodes dispersed in the normal area 420 are collected into the data collection area 430. The process of the acquisition node is described with reference to fig. 6 and 7.

The header address information 511 may be translated by the address translator 443 and updated to the address buffer 450(603), and the node 711 of the normal area 420 may be read by the address ADD stored in the address buffer 450 (605). DATA1 of node 711 may be written into node 721(607) of DATA acquisition area 430. The LINK N _ LINK1 of node 721 may be updated to specify the immediate area within the data collection area 430 (609). As seen in FIG. 7, LINK LINK1 of node 711 is different from LINK N _ LINK1 of node 721. Although the nodes 711 are collected from the data collection area 430, the nodes 711 may remain in the normal area 420 as they are.

Thereafter, the LINK1 of the node 711 may be translated and updated to the address buffer 450(603) by the address translator 443, and the node 712 of the normal area 420 may be read by the address ADD stored in the address buffer 450 (605). The DATA2 of node 712 may be written to nodes 722(607) of the DATA acquisition area 430. The LINK N _ LINK2 of node 722 may be updated to specify the immediate area within the data collection area 430 (609). The LINK2 of the node 712 is different from the LINK N _ LINK2 of the node 722, and although the node 712 is collected from the data collection area 430, the node 712 may remain in the normal area 420 as it is.

Thereafter, the LINK2 of the node 712 may be translated and updated by the address translator 443 to the address buffer 450(603), and the node 713 of the normal area 420 may be read by the address ADD stored in the address buffer 450 (605). DATA3 of node 713 may be written to node 723(607) of DATA acquisition area 430. The LINK3 of node 713 is marked NULL, meaning that LINK3 does not specify any region in memory 400. In other words, in this case, the LINK3 may specify an area other than the memory 400, such as an HDD or an SDD, or may not specify an area (in this case, the node 713 is the last node of the LINK nodes). In this case, the LINK LINK3 of node 723 of the data collection area 430 may be updated in the same manner as the LINK LINK3 of node 713. Since the LINK3 does not specify any area in the memory 400, the defragmentation operation may be terminated.

As can be seen from fig. 7, the nodes 711 to 713 once scattered in the normal area 420 are collected (or collected) in the data collection area 440. Such defragmentation operations may reduce the time to search for data collected in data collection area 430 while increasing the chance of a cache hit.

While the invention has been shown and described in connection with various embodiments, the description is provided as an example; and are not intended to limit the invention. Those of ordinary skill in the art will recognize that various modifications of any of the disclosed embodiments can be made within the spirit and scope of the disclosure. The invention is intended to cover all such modifications as fall within the scope of the claims.