阅读说明：本技术 半导体装置、数字控制振荡器以及半导体装置的控制方法 (Semiconductor device, numerically controlled oscillator, and method for controlling semiconductor device ) 是由 丸山龙彦 于 2020-08-26 设计创作，主要内容包括：实施方式涉及半导体装置、数字控制振荡器以及半导体装置的控制方法。本实施方式涉及的半导体装置具备多个开关元件和多个可变电容元件。多个开关元件是串联连接在第一控制端子与第二控制端子之间的多个开关元件,并能够向第一控制端子和第二控制端子供给多个种类的电容控制信号。多个可变电容元件在多个开关元件的对应的一端连接电容控制端子。(Embodiments relate to a semiconductor device, a digitally controlled oscillator, and a method of controlling a semiconductor device. The semiconductor device according to this embodiment includes a plurality of switching elements and a plurality of variable capacitance elements. The plurality of switching elements are connected in series between the first control terminal and the second control terminal, and can supply a plurality of kinds of capacitance control signals to the first control terminal and the second control terminal. The plurality of variable capacitance elements are connected to capacitance control terminals at corresponding one ends of the plurality of switching elements.)

1. A semiconductor device is characterized by comprising:

a plurality of switching elements connected in series between a first control terminal and a second control terminal, and capable of supplying a plurality of types of capacitance control signals to the first control terminal and the second control terminal; and

and a plurality of variable capacitance elements, one end of each of the plurality of switching elements being connected to a capacitance control terminal.

2. The semiconductor device according to claim 1,

one of the plurality of switching elements is supplied with a first connection signal for bringing the one switching element into a non-conductive state, and the remaining switching elements are supplied with a second connection signal for bringing the remaining switching elements into a conductive state.

3. The semiconductor device according to claim 2,

one of the first control terminal and the second control terminal is supplied with a first capacitance signal for causing the variable capacitance element to have a first capacitance, and the other of the first control terminal and the second control terminal is supplied with a second capacitance signal for causing the variable capacitance element to have a second capacitance different from the first capacitance.

4. The semiconductor device according to claim 2,

the plurality of switching elements and the plurality of variable capacitance elements are formed by a plurality of elements in a column shape in which elements having the variable capacitance elements and the switching elements are arranged in a column shape,

a plurality of the elements in the form of a plurality of columns are arranged, and the elements are arranged in rows and columns.

5. The semiconductor device according to claim 4,

control terminals of the plurality of switching elements arranged in the corresponding rows are connected in series to a common control line to which the first connection signal or the second connection signal is supplied.

6. The semiconductor device according to claim 1,

the variable capacitance element is a gate capacitance of an NMOS transistor.

7. The semiconductor device according to claim 1,

the switching element is a transistor.

8. The semiconductor device according to claim 1,

the plurality of variable capacitance elements are connected in parallel.

9. A digitally controlled oscillator is provided with:

a plurality of switching elements connected in series between a first control terminal and a second control terminal, and capable of supplying a plurality of types of capacitance control signals to the first control terminal and the second control terminal; and

a plurality of variable capacitance elements, one end of each of the plurality of switching elements being connected to a capacitance control terminal,

the oscillation frequency varies according to the total capacitance value of the plurality of variable capacitance elements.

10. The numerically controlled oscillator according to claim 9,

one of the plurality of switching elements is supplied with a first connection signal for bringing the one switching element into a non-conductive state, and the remaining switching elements are supplied with a second connection signal for bringing the remaining switching elements into a conductive state.

11. The numerically controlled oscillator according to claim 10,

one of the first control terminal and the second control terminal is supplied with a first capacitance signal for causing the variable capacitance element to have a first capacitance, and the other of the first control terminal and the second control terminal is supplied with a second capacitance signal for causing the variable capacitance element to have a second capacitance different from the first capacitance.

12. The numerically controlled oscillator according to claim 10,

the plurality of switching elements and the plurality of variable capacitance elements are formed by a plurality of elements in a column shape in which elements having the variable capacitance elements and the switching elements are arranged in a column shape,

a plurality of the elements in the form of a plurality of columns are arranged, and the elements are arranged in rows and columns.

13. The numerically controlled oscillator according to claim 12,

control terminals of the plurality of switching elements arranged in the corresponding rows are connected in series to a common control line to which the first connection signal or the second connection signal is supplied.

14. The numerically controlled oscillator according to claim 9,

the variable capacitance element is a gate capacitance of an NMOS transistor.

15. The numerically controlled oscillator according to claim 9,

the switching element is a transistor.

16. The numerically controlled oscillator according to claim 9,

the plurality of variable capacitance elements are connected in parallel.

17. A method for controlling a semiconductor device,

the semiconductor device includes:

a plurality of switching elements connected in series between a first control terminal and a second control terminal, and capable of supplying a plurality of types of capacitance control signals to the first control terminal and the second control terminal; and

a plurality of variable capacitance elements, one end of each of the plurality of switching elements being connected to a capacitance control terminal,

the control method of the semiconductor device comprises the following steps:

a step of bringing at least one of the plurality of switching elements into a non-conductive state; and

and a step of supplying a first capacitance signal for making the variable capacitance element a first capacitance to one of the first control terminal and the second control terminal, and supplying a second capacitance signal for making the variable capacitance element a second capacitance different from the first capacitance to the other of the first control terminal and the second control terminal.

18. The method according to claim 17, wherein the control unit is further configured to control the semiconductor device,

a first capacitance signal for causing the variable capacitance element to have a first capacitance is supplied to one of the first control terminal and the second control terminal, and a second capacitance signal for causing the variable capacitance element to have a second capacitance different from the first capacitance is supplied to the other of the first control terminal and the second control terminal.

19. The method according to claim 18, wherein the control unit is further configured to control the semiconductor device,

the plurality of switching elements and the plurality of variable capacitance elements are formed by a plurality of elements in a column shape in which elements having the variable capacitance elements and the switching elements are arranged in a column shape,

a plurality of the elements in the form of a plurality of columns are arranged, and the elements are arranged in rows and columns.

20. The method according to claim 19, wherein the control unit is further configured to control the semiconductor device,

control terminals of the plurality of switching elements arranged in the corresponding rows are connected in series to a common control line, and the first connection signal or the second connection signal is supplied to the control line.

Technical Field

Embodiments relate to a semiconductor device, a digitally controlled oscillator, and a method of controlling a semiconductor device.

Background

The digitally controlled oscillator is generally configured as an LC oscillation circuit by connecting an inductor in parallel with a plurality of variable capacitance elements. Then, each variable capacitance element is controlled to either a high capacitance value or a low capacitance value by a digital control signal, whereby the digitally controlled oscillator is oscillated at a predetermined frequency.

In this digitally controlled oscillator, in order to widen the oscillation frequency range while keeping the frequency variation with respect to the unit control signal small and constant, it is necessary to increase the number of control bits and also to increase the number of variable capacitive elements. However, the increase in the number of control bits and the number of variable capacitance elements increases the area occupied by the control lines for controlling the variable capacitance elements, and further increases the parasitic capacitance of the control lines.

Disclosure of Invention

Embodiments provide a semiconductor device, a digitally controlled oscillator, and a method for controlling a semiconductor device, in which the number of variable capacitance elements can be increased while suppressing the occupied area of control lines and parasitic capacitance.

The semiconductor device of the embodiment includes: a plurality of switching elements connected in series between a first control terminal and a second control terminal, and capable of supplying a plurality of types of capacitance control signals to the first control terminal and the second control terminal; and a plurality of variable capacitance elements, one end of each of the plurality of switching elements being connected to a capacitance control terminal.

Drawings

Fig. 1 is a block diagram of a wireless communication device.

Fig. 2 is a block diagram showing the configuration of the frequency synthesizer.

Fig. 3 is a band diagram showing a frequency bandwidth that can be used by the frequency synthesizer.

Fig. 4 is a conceptual diagram of a frequency hopping spectrum spreading scheme in communication conforming to the Bluetooth standard.

Fig. 5 is a diagram showing an example of the configuration of the second element group.

Fig. 6 is a diagram showing a part of the capacitor element of fig. 5 in detail.

Fig. 7 shows a circuit example of an NMOS transistor.

Fig. 8 is a diagram showing a relationship between a voltage and a capacitance of the NMOS transistor of fig. 7.

Fig. 9 is a diagram showing an example of a range in which the variable capacitance element has a high capacitance.

Fig. 10 is a diagram showing an example of transition of the oscillation frequency of the frequency synthesizer.

Detailed Description

Hereinafter, a semiconductor device, a numerically controlled oscillator, and a method for controlling a semiconductor device according to embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below are merely examples of the embodiments of the present invention, and the present invention is not limited to these embodiments. In the drawings referred to in the present embodiment, the same reference numerals or similar reference numerals are given to the same portions or portions having the same functions, and redundant description thereof may be omitted. In addition, the dimensional ratio of the drawings may be different from the actual ratio for convenience of explanation, and a part of the configuration may be omitted from the drawings.

(first embodiment)

Fig. 1 is a block diagram of a wireless communication apparatus 1. As shown in fig. 1, the wireless communication device 1 includes a frequency synthesizer 100, an antenna 200, a switch 201, a low noise Amplifier 202, a mixer 203, a filter 204, a Variable Gain Amplifier (VGA) 205, an a/D converter 206, a signal processing unit 207, a D/a converter 208, a filter 209, a mixer 210, and a power Amplifier 211.

The frequency synthesizer 100 generates the local signal LO, for example, based on the frequency bandwidth signal. Details of the frequency synthesizer 100 will be described later using fig. 2.

The antenna 200 receives a reception signal of a radio frequency and transmits a transmission signal of a radio frequency. Upon reception, the switch 201 supplies a reception signal received by the antenna 200 to the low noise amplifier 202. The low noise amplifier 202 amplifies the reception signal supplied from the switch 201 with low noise. The mixer 203 performs frequency conversion on the output signal of the low noise amplifier 202 based on the local signal LO to reduce the frequency of the received signal. The filter 204 performs bandwidth limitation on the output signal of the mixer 203. The variable gain amplifier 205 amplifies the output signal of the filter 204. The gain of the variable gain amplifier 205 is variable, and the amplitude of the output signal of the variable gain amplifier 205 is adjusted to be substantially constant. The a/D converter 206 converts the output signal of the variable gain amplifier 205 into a digital signal. The signal processing unit 207 performs signal processing on the digital signal supplied from the a/D converter 206 to obtain reception data.

The signal processing unit 207 outputs a digital signal obtained by signal processing the transmission data. The D/a converter 208 converts the digital signal output from the signal processing section 207 into an analog signal. The filter 209 band-limits the analog signal output from the D/a converter 208. The mixer 210 frequency-converts the output signal of the filter 209 in accordance with the local signal LO, and outputs the converted signal as a signal of a radio frequency. The power amplifier 211 supplies the transmission signal, which has been power-amplified by the output signal of the mixer 210, to the switch 201. The switch 201 supplies the transmission signal supplied from the power amplifier 211 to the antenna 200 at the time of transmission.

Here, a detailed configuration of the frequency synthesizer 100 will be described with reference to fig. 2.

Fig. 2 is a block diagram showing the configuration of the frequency synthesizer 100 according to the present embodiment. The frequency synthesizer 100 according to the present embodiment includes a control circuit 110 and a digitally controlled oscillator 120. For example, the frequency synthesizer 100 is a Phase Locked Loop (PLL) circuit that performs Loop control of the oscillation frequency of the digitally controlled oscillator 120 by the control circuit 110.

The control circuit 110 includes a reference signal generation unit 112, a comparison signal generation unit 114, a comparison unit 116, and a loop gain adjustment unit 118. The digitally controlled oscillator 120 is configured as an LC oscillation circuit including an inductor 122, a variable capacitance section 124, a negative resistance generation section 126, and an output amplifier 132.

The oscillation frequency of the digitally controlled oscillator 120 can be changed by changing the capacitance value of the variable capacitance section 124 in the digitally controlled oscillator 120. The variable capacitance section 124 has a first element group 128 and a second element group 130. The variable capacitance section 124 is, for example, a semiconductor device disposed On an soi (silicon On insulator) substrate.

The first element set 128 is a coarse-tuned variable capacitor that is used to substantially determine the oscillation frequency of the numerically controlled oscillator 120. On the other hand, the second element group 130 is a variable capacitor for fine tuning of the oscillation frequency of the digitally controlled oscillator 120. The change in the frequency of the unit control signal for the numerically controlled oscillator 120 corresponds to the change in the unit capacitance of the second element group 130. For example, the second element group 130 can change the total capacitance stepwise in 1024 steps, for example. In the present embodiment, the change amount of the total capacitance of the second element group 130 which discretely changes in 1 step is referred to as a unit capacitance. The number of stages in which the total capacitance of the second element group 130 can be discretely changed is referred to as a control bit number. That is, the number of control bits of the second element group 130 is, for example, 1024 bits. Details of the second element group 130 will be described later.

In the control circuit 110, the reference signal generating section 112 generates the reference signal REF based on, for example, the frequency bandwidth signal. For example, the frequency bandwidth signal conforms to Bluetooth (registered trademark).

Fig. 3 is a band diagram showing a frequency bandwidth that can be used in the frequency synthesizer 100 according to the present embodiment. As shown in fig. 3, the frequency bandwidth used between the master 1 and the slaves 2 and 3 according to the present embodiment is a 2.4 GHz band that is presupposed by the Bluetooth standard. Specifically, the frequencies of 2.402 to 2.480[ GHz ] are divided by 79. That is, communication is performed using any one of 2.402 GHz, 2.403 GHz, 2.404 GHz, … …, and 2.480 GHz.

Fig. 4 is a conceptual diagram of a frequency hopping spectrum spreading scheme in communication conforming to the Bluetooth standard, in which the vertical axis represents the passage of time and the horizontal axis represents the relationship with the frequency used at that time. Fig. 4 shows how the frequency bandwidth used by the frequency synthesizer 100 is switched (transitioned) in time. In communication conforming to the Bluetooth standard, since the frequency used is changed 1600 times in 1 second, the time for which data transfer is performed while keeping the frequency constant is 625 μ sec. That is, the value of α shown in fig. 4 becomes 625 μ sec. In addition, this interval of every 625 μ sec is referred to as 1 slot.

Referring again to fig. 2, the comparison signal generation unit 114 performs processing such as frequency division and integration on the output LO of the digitally controlled oscillator 120 to generate a comparison signal. The comparison unit 116 receives the comparison signal and the reference signal REF, compares the phase or the frequency or both the phase and the frequency of these signals, and outputs a comparison result corresponding to the deviation.

The loop gain adjustment unit 118 generates a coarse control signal for controlling the first element group 128 and a fine control signal for controlling the second element group 130 so that the loop gain becomes appropriate, based on the comparison result of the comparison unit 116. The fine control signal includes information of the number of control bits of the second element group 130 with respect to the oscillation frequency. That is, the fine control signal has information of the total capacitance of the second element group 130.

In this way, the oscillation frequency of the digitally controlled oscillator 120 is roughly determined by the coarse adjustment control signal, and the oscillation frequency of the digitally controlled oscillator 120 is made to follow the target value by the fine adjustment control signal. Thus, the frequency synthesizer stably supplies a desired oscillation frequency signal. The details of the fine control signal will be described later.

Here, the detailed configuration of the second element group 130 will be described with reference to fig. 5 and 6.

Fig. 5 is a diagram showing an example of the configuration of the second element group 130. As shown in fig. 5, the second element group 130 has 32 × 32 elements E (1, 1) to E (32, 32). The 32 × 32 elements E (1, 1) to E (32, 32) are arranged in a two-dimensional matrix. Here, n rows and m columns are represented by (n, m). For example, n and m are integers of 1 to 32 inclusive. Thus, for example, element E (12, 15) refers to an element arranged in 12 rows and 15 columns. The second element group 130 includes control terminals 130a arranged in a column, control terminals 130b arranged in an upper side of a row, and control terminals 130c arranged in a lower side of the row. In the present embodiment, the number of elements E is 32 × 32 for simplicity of explanation, but the present invention is not limited to this.

The detailed structure of the second element group 130 will be described with reference to fig. 5 and fig. 6. Fig. 6 is a diagram showing a part of the capacitor elements E (1, 1) to E (32, 32) in fig. 5 in detail. As shown in fig. 6, each of the capacitive elements E (1, 1) to E (32, 32) includes a variable capacitive element C (1, 1) to C (32, 32) and a switching element S (1, 1) to S (32, 32). In each of the variable capacitance elements C (1, 1) to C (32, 32), the capacitance changes into a first capacitance and a second capacitance smaller than the first capacitance in accordance with a plurality of kinds of capacitance control signals supplied to the capacitance control terminal. More specifically, when the first capacitance signal is supplied to the capacitance control terminal, each of the variable capacitance elements C (1, 1) to C (32, 32) becomes a first capacitance, and when the second capacitance signal is supplied to the capacitance control terminal, each of the variable capacitance elements C (1, 1) to C (32, 32) becomes a second capacitance.

Each of the variable capacitance elements C (1, 1) to C (32, 32) is a capacitor formed by gate capacitances of 2 NMOS transistors, for example. That is, for example, 2 NMOS transistors are connected in parallel to each of the variable capacitance elements C (1, 1) to C (32, 32). For example, each of the variable capacitance elements C (1, 1) to C (32, 32) is configured by connecting the drain and the source of 2 NMOS transistors. In this case, a terminal formed by bonding the drain and the source is a capacitance control terminal. The variable capacitive elements C (1, 1) to C (32, 32) are connected in parallel between terminals T1 and T2 of the numerically controlled oscillator 120 (fig. 1).

The switching elements S (1, 1) to S (32, 32) are, for example, NMOS transistors. The switching elements S (1, 1) to S (32, 32) perform ON/OFF (ON/OFF) operations in accordance with a control signal supplied to the gate. For example, the control signal is in a conductive state (ON) when it is at an H level (high voltage), and in a non-conductive state (OFF) when it is at an L level (low voltage). Here, the L-level control signal according to the present embodiment corresponds to the first connection signal, and the H-level control signal corresponds to the second connection signal. The switching elements S (1, 1) to S (32, 32) according to the present embodiment are turned ON when the control signal is at the H level and turned OFF when the control signal is at the L level, but the present invention is not limited thereto. For example, the control signal may be turned ON (ON) when it is at L level, or turned OFF when it is at H level. The configuration of the switching elements S (1, 1) to S (32, 32) is not limited to the NMOS transistor.

The switching elements S (1, n) to S (32, n) are connected in series to a column control line Ltn connected to the upper control terminal Otn and the opposite lower control terminal Obn. Further, the capacitance control terminals of the variable capacitance elements C (1, n) to C (32, n) are connected to the corresponding one ends of the switching elements S (1, n) to S (32, n). The first capacitance signal or the second capacitance signal is supplied to the control terminal Otn and the control terminal Obn.

Further, gates as control terminals of the switching elements S (m, 1) to S (m, 32) are connected in series to a row control line Lgm connected to the control terminal Ogm. For example, when the signal of the control terminal Ogm is at the H level, the switching elements S (m, 1) to S (m, 32) are turned ON, and when the signal is at the L level, the switching elements S (m, 1) to S (m, 32) are turned OFF. In this way, the control terminals of the plurality of switching elements S (m, 1) to S (m, 32) arranged in the corresponding row m are connected in series to the common row control line Lgm, and the first connection signal or the second connection signal is supplied to the row control line Lgm.

In this way, the plurality of switching elements S (1, n) to S (32, n) and the plurality of variable capacitance elements C (1, n) to C (32, n) are formed by a plurality of elements E (1, n) to E (32, n) in a row, and the plurality of elements E (1, n) to E (32, n) have elements E having the variable capacitance elements C and the switching elements S arranged in a row. The second element group 130 is arranged by arranging a plurality of elements E (1, n) to E (32, n) in a row in m rows. Thus, the elements E are arranged in rows and columns E (1, 1) to E (32, 32).

Thus, as will be described later, the total capacitance of the variable capacitance elements C (1, 1) to C (32, 32) can be controlled by the 32 column control lines Ltn and the 32 row control lines Lgm. In this way, in the conventional case, since an independent control line is connected from the loop gain adjustment unit 118 (fig. 2) to each of the variable capacitance elements C (1, 1) to C (32, 32), n × m (32 × 32 — 1024) control lines are necessary, but since only n + m (32+32 — 64) control lines are necessary, it is possible to reduce the size of the capacitance elements E (1, 1) to E (32, 32) and reduce the parasitic capacitance. This makes it easier to increase the number of the capacitive elements E (1, 1) to E (32, 32) in a limited space in the SOI substrate. That is, the number of bits of the second element group 130 can be increased more easily in a limited space in the SOI substrate.

Here, characteristics of NMOS transistors constituting the variable capacitive elements C (1, 1) to C (32, 32) will be described with reference to fig. 7 and 8. Fig. 7 shows an example of an equivalent circuit of the variable capacitance element C in which a voltage VDD is applied to the Gate (Gate) of the NMOS transistor and a variable voltage V is applied to the Source (Source) and the Drain (Drain). Fig. 8 is a diagram showing a relationship between a voltage and a capacitance of the NMOS transistor of fig. 7. The horizontal axis represents the variable voltage V, and the vertical axis represents the gate capacitance C of the NMOS transistor.

As shown in FIG. 8, the NMOS transistor exhibits a high capacitance CH1 at a low voltage level L and a low capacitance CH1 at a high voltage level H. That is, the variable capacitance elements C (1, 1) to C (32, 32) have a high capacitance when a low voltage L is applied thereto and have a low capacitance when a high voltage H is applied thereto.

That is, each of the variable capacitance elements C (1, 1) to C (32, 32) has a high capacitance when the first capacitance signal output from the upper control terminal Otn or the lower control terminal Obn corresponds to the low voltage level L, and has a low capacitance when the second capacitance signal corresponds to the high voltage level H.

The unit capacitance is a difference between the high capacitance and the low capacitance. As described above, in this embodiment, the gate capacitance of the NMOS transistor is used as the variable capacitance element C. Therefore, by appropriately setting the high voltage level H and the low voltage level L, the unit capacitance can be freely set. Thus, for example, by appropriately setting the high voltage level H and the low voltage level L, it is possible to more easily adjust the frequency change for the unit control signal in the digitally controlled oscillator 100.

Here, control of the total capacitance of the variable capacitance elements C (1, 1) to C (32, 32) will be described with reference to fig. 5 and 6 and based on fig. 9. Fig. 9 is a diagram showing an example a130 of a range in which the variable capacitance elements C (1, 1) to C (32, 32) have high capacitance. In the figure, L denotes the first capacitance signal as a low voltage level L, and H denotes the second capacitance signal as a high voltage level H. The Open signal corresponds to a first connection signal for bringing the switching elements S (1, 1) to S (32, 32) into a non-conductive state, and the Short signal corresponds to a second connection signal for bringing the switching elements S (1, 1) to S (32, 32) into a conductive state.

As shown in fig. 9, an Open signal (first connection signal) for making the switching element non-conductive is output to one control terminal Ogn of the control terminals Og1 to Og 32. On the other hand, the Short signal (second connection signal) is output to the control terminals other than the control terminal Ogn among the other control terminals Og1 to Og 32.

As a result, the switching elements S (n, 1) to S (n, 32) to which the Open signal is output are in a non-conductive state. Therefore, it is possible to output either the first capacitance signal (L) or the second capacitance signal (H) to each of the control terminals Ot1 to Ot32 and the control terminals Ob1 to Ob32, and to output either the first capacitance signal (L) or the second capacitance signal (H) to the variable capacitance elements C (1, 1) to C (32, 32).

In other words, if all the switching elements S (n, 1) to S (n, 32) are in the on state, the control terminals Ot1 to Ot32 and the corresponding control terminals Ob1 to Ob32 are at the same potential, and therefore only one of the first capacitance signal (L) and the second capacitance signal (H) can be applied. In contrast, in the present embodiment, since the switching elements S (n, 1) to S (n, 32) to which the Open signal is output are in the non-conductive state, the control terminals Ot1 to Ot32 and the corresponding control terminals Ob1 to Ob32 can be at the same potential or different potentials. Thus, as described above, either the first capacitance signal (L) or the second capacitance signal (H) can be applied to each of the control terminals Ot1 to Ot32 and the control terminals Ob1 to Ob 32.

For example, when only the variable capacitance element C (1, 1) is set to have a high capacitance and the other variable capacitance element C is set to have a low capacitance, the Open signal is output to the control terminal Og1 and the first capacitance signal (L) is output only to the control terminal Ot 1. That is, the second capacitance signal (H) is output to the control terminals other than the control terminal Ot1 among the control terminals Ot1 to Ot32 and the control terminals Ob1 to Ob 32.

Next, when only the variable capacitance elements C (1, 1) and C (2, 1) are made to have a high capacitance and the other variable capacitance element C is made to have a low capacitance, an Open signal is output to the control terminal Og2, and the first capacitance signal (L) is output only to the control terminal Ot 1. In this way, if the second capacitance signal (H) is output to the control terminals other than the control terminal Ot1 among the control terminals Ot1 to Ot32 and the control terminals Ob1 to Ob32, the number of high-capacitance variable capacitance elements C can be increased to 32 one by changing Ogn that outputs the Open signal.

When 32 variable capacitance elements C are set to have high capacitance and the 33 th variable capacitance element C is set to have high capacitance, an Open signal is output to the control terminal Og1, and the first capacitance signal (L) is output only to the control terminals Ot1, Ob1, and Ot 2. By changing Ogn for outputting the Open signal, the number of high-capacitance variable capacitive elements C can be increased from 33 to 64 one by one.

When 64 variable capacitive elements C are made to have high capacitance and the 65 th variable capacitive element C is made to have high capacitance, an Open signal is output to the control terminal Og1, and the first capacitance signal (L) is output only to the control terminals Ot1, Ob1, Ot2, Ob2, and Ot 3. By changing Ogn for outputting the Open signal, the number of high-capacitance variable capacitive elements C can be increased from 65 to 96 one by one. In fig. 9, since an Open signal is being output to the control terminal Og3, 67 variable capacitance elements C are set to high capacitances, and the remaining variable capacitance elements C are set to low capacitances.

By performing such processing, the total capacitance value of the variable capacitance elements C (1, 1) to C (32, 32) can be changed in 32 × 32 stages. That is, the element group 130 has variable capacitance of 1024 bits.

Returning again to fig. 2, the fine control signal will be described in detail. For example, when N capacitors are set to be high, the loop gain adjustment unit 118 of the frequency synthesizer 100 divides 32 × 32 by N and outputs the first capacitance signal (L) to the control terminals Ot1 to Otn and Ob1 to Obn of the column corresponding to the solution N, and also outputs the first capacitance signal (L) to Ot (N +1) when the remainder is not 0. In this case, an Open signal is output to the control terminal Ogm corresponding to the number m of remainders.

For example, when 67 pieces are made to have high capacitance, 67 is divided by 32. Since the solution is 2 and the remainder is 3, the first capacitance signal (L) is output to the control terminals Ot1 to Ot2, Ob1 to Ob2, and Ot3 — Ot (2+1), and the Open signal is output to the control terminal Og 3.

For example, when 64 of the capacitors have a high capacitance, 64 is divided by 32. Since the solution is 2 and the remainder is 0, the first capacitance signal (L) is output to the control terminals Ot1 to Ot2 and Ob1 to Ob2, and the Open signal is output to the control terminal Og 32.

For example, the loop gain adjustment unit 118 stores in advance a table of the relationship between the capacitance necessary for the transmission frequency and the control signals of the control terminals Ot1 to Otn, Ob1 to Obn, and control terminals Og1 to Obn, and applies the control signal corresponding to the necessary capacitance to the second element group 130 as the fine adjustment control signal. In this way, the total capacitance value of the variable capacitance elements C (1, 1) to C (32, 32) can be changed in 1024 steps of 32 × 32.

Fig. 10 is a diagram showing an example of transition of the oscillation frequency of the frequency synthesizer 100. The horizontal axis represents time, and the vertical axis represents oscillation frequency. In fig. 10, L10 shows an example of a transient change in the oscillation frequency of the frequency synthesizer 100 according to the present embodiment, and L20 shows an example of a transient change in the oscillation frequency of the comparative example. The frequency conversion point is set to time 0.

The comparative example is an example of a frequency synthesizer in which a first capacitance element having a minimum capacitance value is controlled in a lower order and a second capacitance element having a capacitance value N times that of the first capacitance element is controlled in a higher order. In the comparative example, when the bit is changed, an operation of switching N first capacitance elements and one second capacitance element, that is, an operation of switching capacitance elements connected in parallel occurs. This causes a shift in timing of switching the N first capacitive elements and the one second capacitive element. Therefore, the oscillation frequency is shifted. In this way, it is difficult to control the timing of the switching operation between the N first capacitance elements and the one second capacitance element, and there is a possibility that the oscillation frequency is shifted.

In contrast, in the frequency synthesizer 100 according to the present embodiment, since the total capacitance value of the variable capacitive elements C (1, 1) to C (32, 32) can be changed by changing the capacitance of each variable capacitive element C, the switching operation of the capacitive elements is not necessary at the time of the site change, and the occurrence of the shift of the oscillation frequency can be suppressed.

The second element group 130 according to the present embodiment is used in the frequency synthesizer 100, but is not limited thereto. The second element group 130 can be used for all electronic instruments requiring variable capacitance.

As described above, according to the present embodiment, the second element group 130 is configured to include the plurality of switching elements S (1, n) to S (32, n) connected in series to the column control line Otn between the column control terminal (Otn) and the column control terminal (Obn), and the plurality of variable capacitance elements C (1, n) to C (32, n) connected to the capacitance control terminal at the corresponding one end of each of the plurality of switching elements S (1, n) to S (32, n). Thus, the first capacitance signal or the second capacitance signal can be supplied to the column control terminal (Otn) and the opposing column control terminal (Obn), and even if the control lines are not independently connected to the variable capacitance elements C (1, n) to C (32, n) from the loop gain adjustment unit 118, the total capacitance of the variable capacitance elements C (1, n) to C (32, n) can be changed to 32 stages by the column control line Otn. By reducing the number of control lines in this way, the number of variable capacitance elements C (1, n) to C (32, n) can be increased while suppressing the area occupied by the control lines and parasitic capacitance even in a limited space.

Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the present invention. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.