阅读说明：本技术 电容阵列型逐次逼近模数转换器的校准方法 (Calibration method of capacitor array type successive approximation analog-digital converter ) 是由 许�鹏 于 2021-11-16 设计创作，主要内容包括：本公开提供了一种电容阵列型逐次逼近模数转换器的校准方法,该校准方法通过获取目标位电容的实际权重值以及该实际权重值与对应目标位电容的理想权重值之间的误差编码；再将待校准的该逐次逼近模数转换器的输出码用该误差编码做相应加或减的修正得到最终校准后的输出码。其突破了非二进制权重必须满足冗余的要求,可以在传统的二进制模数转换器实现权重校准,在模数转换得到的原始码基础上通过简单加减法实现数字校正,有效避免了现有技术的误差问题,提高了校准精度和准确度,同时改善了采用非二进制权重校准带来的电路复杂性和计算复杂度。(The calibration method comprises the steps of obtaining an actual weight value of a target bit capacitor and an error code between the actual weight value and an ideal weight value of the corresponding target bit capacitor; and then the output code of the successive approximation analog-to-digital converter to be calibrated is corrected by the error code in a corresponding addition or subtraction way to obtain the final calibrated output code. The method breaks through the requirement that non-binary weights must meet redundancy, can realize weight calibration on the traditional binary analog-to-digital converter, realizes digital correction by simple addition and subtraction on the basis of the original codes obtained by analog-to-digital conversion, effectively avoids the error problem in the prior art, improves the calibration precision and accuracy, and simultaneously improves the circuit complexity and the calculation complexity caused by adopting non-binary weight calibration.)

1. A calibration method for a capacitor array type successive approximation analog-to-digital converter in which capacitances follow a proportion of binary weights from low to high, wherein the calibration method comprises:

acquiring an actual weight value of a target position capacitor and an error code between the actual weight value and an ideal weight value of the corresponding target position capacitor;

and correspondingly adding or subtracting the output code of the analog-to-digital converter to be calibrated by using the error code to obtain the finally calibrated output code.

2. The calibration method according to claim 1, wherein the capacitor array of the successive approximation analog-to-digital converter comprises a positive capacitor array and a negative capacitor array, and the step of obtaining an actual weight value of the target bit capacitance and an error code between the actual weight value and an ideal weight value of the corresponding target bit capacitance comprises:

initializing a target bit positive capacitor in the positive capacitor array and sampling;

switching the plate voltage state of the target bit capacitor and the next bit capacitor through logic control to obtain a first weight error voltage of the target bit capacitor;

converting the first weight error voltage by using differential modulus conversion to obtain a first weight error voltage code of the target bit capacitor, wherein the first weight error voltage code is represented by the next two bit capacitors of the target bit to the lowest bit capacitor;

initializing a target potential negative capacitor in the negative capacitor array and sampling;

switching the plate voltage states of the target bit capacitor and the next bit capacitor through logic control to obtain a second weight error voltage of the target bit capacitor;

converting the second weighted error voltage by using differential modulus conversion to obtain a second weighted error voltage code of the target bit capacitor, wherein the second weighted error voltage code is represented by the next two bit capacitors of the target bit capacitor to the lowest bit capacitor;

obtaining an error code between an actual weight value and an ideal weight value of the target bit capacitor according to the first weight error voltage code and the second weight error voltage code,

the target potential capacitance includes the target potential positive capacitance and the target potential negative capacitance.

3. The calibration method according to claim 2, wherein a lower plate of any bit positive capacitor is connected to any one of a positive input voltage, a positive reference voltage and a negative reference voltage through a one-out-of-three switch, a connection node of an upper plate and a positive output terminal of the positive capacitor array is connected to a common voltage through a one-out-of-one switch, and the step of initializing a target bit positive capacitor in the positive capacitor array and sampling comprises:

connecting a lower plate of a target positive capacitor in the positive capacitor array with the positive reference voltage, connecting lower plates of other positive capacitors with the negative reference voltage, connecting a lower plate of a target negative capacitor next in the negative capacitor array with the positive reference voltage, connecting lower plates of other negative capacitors with the negative reference voltage, connecting upper plates of all positive capacitors in the positive capacitor array with the common voltage through a single-selection switch, and connecting upper plates of all negative capacitors in the negative capacitor array with the common voltage through a single-selection switch;

sampling, and disconnecting the common voltage, so that the capacitance charges of the positive capacitance array and the negative capacitance array are kept constant.

4. The calibration method according to claim 3, wherein the step of obtaining the first weighted error voltage of the target bit capacitor by switching the plate voltage state of the target bit capacitor through logic control comprises:

logic controls the voltage state of the electrode plate of the positive capacitor of the target position and the next position thereof to switch and connect the lower electrode plate of the positive capacitor of the target position in the positive capacitor array to the negative reference voltage, and the lower electrode plate of the positive capacitor of the next position of the target position in the positive capacitor array to the positive reference voltage, and the lower electrode plate of the negative capacitor of the next position of the target position in the negative capacitor array to switch and connect to the negative reference voltage, and the first weight error voltage is generated between the positive output end of the positive capacitor array and the negative output end of the negative capacitor array,

the first weight error voltage represents a difference value obtained by subtracting a sum of an actual weight value of the positive capacitor next to the target bit and an actual weight value of the negative capacitor next to the target bit from an actual weight value of the positive capacitor next to the target bit.

5. The calibration method according to claim 4, wherein a lower plate of any potential negative capacitor is connected to any one of a negative input voltage, a positive reference voltage and a negative reference voltage through a one-out-of-three switch, a connection node of an upper plate and a negative output terminal of the negative capacitor array is connected to a common voltage through a one-out-of-one switch, and the step of initializing a target potential negative capacitor in the negative capacitor array and sampling comprises:

connecting the lower plate of the next positive capacitor of the target position in the positive capacitor array with the positive reference voltage, connecting the lower plates of other positive capacitors with the negative reference voltage, connecting the lower plate of the negative capacitor of the target position in the negative capacitor array with the positive reference voltage, connecting the lower plates of other negative capacitors with the negative reference voltage, connecting the upper plates of all the positive capacitors in the positive capacitor array with the common voltage through a single-selection switch, and connecting the upper plates of all the negative capacitors in the negative capacitor array with the common voltage through a single-selection switch;

sampling, and disconnecting the common voltage, so that the capacitance charges of the positive capacitance array and the negative capacitance array are kept constant.

6. The calibration method according to claim 5, wherein the step of obtaining the second weighted error voltage of the target bit capacitor by switching the plate voltage state of the target bit capacitor through logic control comprises:

logic control switches the plate voltage state of the positive capacitor next to the target bit, so that the lower plate of the positive capacitor next to the target bit in the positive capacitor array is switched and communicated to the negative reference voltage, the lower plate of the negative capacitor next to the target bit in the negative capacitor array is switched and communicated to the positive reference voltage, the lower plate of the negative capacitor next to the target bit in the target bit is switched and communicated to the negative reference voltage, and the second weighted error voltage is generated between the positive output end of the positive capacitor array and the negative output end of the negative capacitor array,

the second weight error voltage represents a difference value obtained by subtracting a sum of an actual weight value of the positive capacitor next to the target potential and an actual weight value of the negative capacitor next to the target potential from an actual weight value of the negative capacitor next to the target potential.

7. The calibration method of claim 6, wherein the step of obtaining the actual weight value of the target bit capacitance and the error coding between the actual weight value and the ideal weight value of the corresponding target bit capacitance further comprises:

repeating the obtaining step to obtain a plurality of first weight error voltages and first weight error voltage codes, and a plurality of second weight error voltages and second weight error voltage codes;

respectively obtaining an average value of a plurality of first weight error voltage codes and an average value of a plurality of second weight error voltage codes;

and obtaining an error code between the actual weight value and the ideal weight value of the target bit capacitor according to the average value of the first weight error voltage code and the average value of the second weight error voltage code,

or repeating the obtaining step to obtain a plurality of first weight error voltage codes and a plurality of second weight error voltage codes respectively;

calculating to obtain error codes between actual weight values and ideal weight values of a plurality of target bit capacitors;

the final error code is obtained by calculating the average of the plurality of error codes.

8. The calibration method of claim 1, wherein the calibration method further comprises:

the proper capacitance size is selected according to the capacitance production process to meet the low-order matching requirement, so that different high-order weight bits can be selected correspondingly to start calibration.

9. The calibration method of claim 1, wherein the calibration method further comprises:

the bit width of the output code obtained after each calibration can be adjusted according to preset precision requirements and/or parameters of a static memory, wherein the static memory is used for storing the actual weight value or the error code.

10. A calibration method for a capacitor array type successive approximation analog-to-digital converter in which capacitances follow a proportion of binary weights from low to high, wherein the calibration method comprises:

acquiring an actual weight value of a target bit capacitor and a binary code of the actual weight value;

and correspondingly adding or subtracting the output code of the successive approximation analog-to-digital converter to be calibrated by using the binary code to obtain the finally calibrated output code.

Technical Field

The disclosure relates to the technical field of electronic circuits, in particular to a calibration method of a capacitor array type successive approximation analog-to-digital converter.

Background

With the development of the information industry, digital signal processing technology is changing day by day, and analog-to-digital/digital-to-analog (a/D, D/a) converters as bridges for connecting analog and digital worlds are also being widely used. Such as an analog-to-digital converter (ADC) that acts as a bridge between the analog world and the digital world to convert analog signals to digital signals. Along with the increase of the digital signal processing speed, the requirements of high speed and high precision are necessarily put forward on an analog-digital/digital-analog converter; meanwhile, the rapid development of portable consumer electronics, medical instruments and the like also puts forward the requirement of low power consumption on the analog-digital/digital-analog converter. Flash a/D and Δ Σ a/D represent two extremes of high speed and high precision, respectively, and compared to the two, a capacitor array type successive approximation analog-to-digital converter (SAR ADC) with medium speed and medium precision is gradually favored due to its characteristics of extremely low power consumption and low delay, and is increasingly widely applied in the fields of medical instruments, industrial control, microcomputer interfaces, and the like.

SAR ADCs determine the value of each bit by successively comparing the input signal to a signal generated by an internal digital-to-analog converter (DAC). The DAC is typically implemented by a capacitor array, and the size of the DAC capacitor array is typically determined by the resolution, linearity, and matching characteristics of the capacitors of the ADC. Compared with a resistance type or current type digital-to-analog converter, the capacitor array type ADC has no static power consumption, energy consumption is mainly reflected in capacitor charging and discharging, and the capacitor array has a sampling and holding function, so that the area of a chip can be reduced to a certain extent, and cost is reduced. However, the capacitance number and area of the conventional binary capacitor array or the bridge capacitor array increase exponentially with the increase of the resolution. If the unit capacitor C is selected according to the ADC resolution, linearity and matching degree of process production, the area of the capacitor is increased, so that the area of a chip is increased, the cost is increased, the power consumption is increased, and the sampling rate is difficult to improve. Furthermore, when the matching degree of the capacitance can not satisfy the linearity requirement of the ADC, the Direct Current (DC) and Alternating Current (AC) performances of the ADC including Differential Nonlinearity (DNL), Integral Nonlinearity (INL), Total Harmonic Distortion (THD), and Spurious Free Dynamic Range (SFDR) will be affected.

The capacitance mismatch problem of present SAR ADCs is usually solved by analog calibration or digital calibration. Analog calibration is to compensate for errors due to capacitance mismatch during each bit transition by adding a calibration circuit. The digital calibration is to store the capacitance mismatch in the digital domain and perform post-processing to correct the mismatch after obtaining the conversion result. Analog calibration has the advantage of low delay compared to digital calibration, and the disadvantage of increasing circuit complexity and area. Digital calibration introduces redundancy by using non-binary weights so that the higher order capacitance can be calibrated with the lower order capacitance. However, non-binary weighted capacitor arrays increase circuit complexity as well as computational complexity.

Disclosure of Invention

In order to solve the above technical problem, the present disclosure provides a calibration method for a capacitor array type successive approximation analog-to-digital converter, which can break through the redundancy requirement necessary for a non-binary weight analog-to-digital converter, and can implement weight calibration based on a conventional binary analog-to-digital converter, thereby avoiding the circuit complexity and the calculation complexity caused by the non-binary weight.

In one aspect, the present disclosure provides a calibration method for a capacitor array type successive approximation analog-to-digital converter in which capacitances follow a binary weight ratio from a low order to a high order, wherein the calibration method includes:

acquiring an actual weight value of a target position capacitor and an error code between the actual weight value and an ideal weight value of the corresponding target position capacitor;

and correspondingly adding or subtracting the output code of the analog-to-digital converter to be calibrated by using the error code to obtain the finally calibrated output code.

Preferably, the capacitor array of the successive approximation type analog-to-digital converter includes a positive capacitor array and a negative capacitor array, and the step of obtaining the actual weight value of the target bit capacitor and the error code between the actual weight value and the ideal weight value of the corresponding target bit capacitor includes:

initializing a target bit positive capacitor in the positive capacitor array and sampling;

switching the plate voltage state of a target bit capacitor and a next bit capacitor through logic control to obtain a first weight error voltage of the target bit capacitor;

converting the first weighted error voltage by using differential modulus conversion to obtain a first weighted error voltage code of the target bit capacitor, wherein the first weighted error voltage code is represented by the capacitance from the next two bits of the target bit capacitor to the lowest bit capacitor;

initializing a target potential negative capacitor in the negative capacitor array and sampling;

switching the plate voltage state of a target bit capacitor and a next bit capacitor through logic control to obtain a second weight error voltage of the target bit capacitor;

converting the second weighted error voltage by using differential modulus conversion to obtain a second weighted error voltage code of the target bit capacitor, wherein the second weighted error voltage code is represented by the capacitance of the next two bits of the target bit to the lowest bit capacitor;

obtaining an error code between the actual weight value and the ideal weight value of the target bit capacitor according to the first weight error voltage code and the second weight error voltage code,

the target potential capacitor includes a target potential positive capacitor and a target potential negative capacitor.

Preferably, the lower plate of any bit positive capacitor is connected to any one of the positive input voltage, the positive reference voltage and the negative reference voltage through a one-out-of-three switch, the connection node between the upper plate and the positive output end of the positive capacitor array is connected to the common voltage through a one-out-of-one switch, and the step of initializing and sampling the target bit positive capacitor in the positive capacitor array includes:

connecting the lower plate of a target positive capacitor in the positive capacitor array with a positive reference voltage, connecting the lower plates of other positive capacitors with a negative reference voltage, connecting the lower plate of a target next negative capacitor in the negative capacitor array with the positive reference voltage, connecting the lower plates of other negative capacitors with the negative reference voltage, connecting the upper plates of all positive capacitors in the positive capacitor array with a common voltage through a single-selection switch, and connecting the upper plates of all negative capacitors in the negative capacitor array with the common voltage through the single-selection switch;

and sampling, and disconnecting the public voltage to keep the capacitance charges of the positive capacitance array and the negative capacitance array constant.

Preferably, the step of obtaining the first weighted error voltage of the target bit capacitor by logically controlling the plate voltage state of the target bit capacitor includes:

logic controls the voltage state of the electrode plate of the positive capacitor of the target position and the next position to switch and connect the lower electrode plate of the positive capacitor of the target position in the positive capacitor array to the negative reference voltage, and the lower electrode plate of the positive capacitor of the next position to the target position in the positive capacitor array to the positive reference voltage, and switches and connects the lower electrode plate of the negative capacitor of the next position to the negative reference voltage, the first weight error voltage is generated between the positive output end of the positive capacitor array and the negative output end of the negative capacitor array,

the first weight error voltage represents a difference value obtained by subtracting a sum of an actual weight value of a positive capacitor next to the target bit and an actual weight value of a negative capacitor next to the target bit from an actual weight value of the positive capacitor next to the target bit.

Preferably, the lower plate of any potential negative capacitor is connected with any one of a negative input voltage, a positive reference voltage and a negative reference voltage through a one-out-of-three switch, the connection node of the upper plate and the negative output end of the negative capacitor array is connected with a common voltage through a one-out-of-one switch, and the step of initializing a target potential negative capacitor in the negative capacitor array and sampling comprises:

connecting a lower plate of a positive capacitor next to a target position in the positive capacitor array with a positive reference voltage, connecting lower plates of other positive capacitors with a negative reference voltage, connecting a lower plate of a target position negative capacitor in the negative capacitor array with the positive reference voltage, connecting lower plates of other negative capacitors with the negative reference voltage, connecting upper plates of all positive capacitors in the positive capacitor array with a common voltage through a single-selection switch, and connecting upper plates of all negative capacitors in the negative capacitor array with the common voltage through the single-selection switch;

and sampling, and disconnecting the public voltage to keep the capacitance charges of the positive capacitance array and the negative capacitance array constant.

Preferably, the step of obtaining the second weighted error voltage of the target bit capacitor by logically controlling the plate voltage state of the target bit capacitor includes:

logic controls the voltage state of the plate of the positive capacitor of the target position and the next position to switch the lower plate of the positive capacitor of the next position in the positive capacitor array to the negative reference voltage, the lower plate of the negative capacitor of the target position in the negative capacitor array to the negative reference voltage, and the lower plate of the negative capacitor of the next position to the positive reference voltage, the second weight error voltage is generated between the positive output end of the positive capacitor array and the negative output end of the negative capacitor array,

the second weight error voltage represents a difference value obtained by subtracting a sum of an actual weight value of the positive capacitor next to the target potential and an actual weight value of the negative capacitor next to the target potential from an actual weight value of the negative capacitor next to the target potential.

Preferably, the step of obtaining the actual weight value of the target bit capacitor and the error code between the actual weight value and the ideal weight value of the corresponding target bit capacitor further includes:

repeating the obtaining step to obtain a plurality of first weight error voltages and first weight error voltage codes, and a plurality of second weight error voltages and second weight error voltage codes;

respectively obtaining an average value of the plurality of first weight error voltage codes and an average value of the plurality of second weight error voltage codes;

and obtaining an error code between the actual weight value and the ideal weight value of the target bit capacitor according to the average value of the first weight error voltage code and the average value of the second weight error voltage code,

or repeating the obtaining step to obtain a plurality of first weight error voltage codes and a plurality of second weight error voltage codes respectively;

calculating to obtain error codes between actual weight values and ideal weight values of a plurality of target bit capacitors;

the final error code is obtained by calculating the average of the plurality of error codes.

Preferably, the calibration method further comprises:

the proper capacitance size is selected according to the capacitance production process to meet the low-order matching requirement, so that different high-order weight bits can be selected correspondingly to start calibration.

Preferably, the calibration method further comprises:

the bit width of the output code obtained after each calibration can be adjusted according to the preset precision requirement and/or the parameters of the static memory, wherein the static memory is used for storing the actual weight value or the error code.

In another aspect, the present disclosure further provides a calibration method for a capacitor array type successive approximation analog-to-digital converter, where a capacitance in the successive approximation analog-to-digital converter follows a binary weight ratio from a low bit to a high bit, where the calibration method includes:

acquiring an actual weight value of a target bit capacitor and a binary code of the actual weight value;

and performing corresponding addition or subtraction correction on the output code of the successive approximation analog-to-digital converter to be calibrated by using the binary code to obtain the finally calibrated output code.

The beneficial effects of this disclosure are: the calibration method of the capacitor array type successive approximation analog-to-digital converter is suitable for a single-ended or differential input analog-to-digital converter, the capacitance in the successive approximation analog-to-digital converter follows the proportion of binary weight from low order to high order, the capacitor array is realized through a traditional binary capacitor array or a bridge capacitor array, and each bit weight is realized through a single capacitor or a pair of equal capacitors, so that the weight deviation caused by capacitance mismatch or parasitic capacitance is calibrated. The calibration method comprises the steps of obtaining an actual weight value of a target bit capacitor and an error code between the actual weight value and an ideal weight value of the corresponding target bit capacitor; and then the output code of the successive approximation analog-to-digital converter to be calibrated is corrected by the error code in a corresponding addition or subtraction way to obtain the final calibrated output code. The calibration method breaks through the requirement that non-binary weights must meet redundancy, can realize weight calibration on a traditional binary analog-to-digital converter, realizes digital correction by simple addition and subtraction on the basis of an original code obtained by analog-to-digital conversion, effectively avoids the problem that DNL drifts to a certain direction due to the voltage offset of a comparator in binary weight calibration in the prior art, so that a plurality of correction bits of LSB are not enough to represent error values containing the voltage offset, improves calibration precision and accuracy, and simultaneously improves circuit complexity and calculation complexity caused by non-binary weight calibration.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.

FIG. 1 shows a system block diagram of a successive approximation analog-to-digital converter in the prior art;

FIG. 2 is a schematic diagram of a capacitor array of a differential binary-weighted capacitor array type DAC according to the prior art;

FIG. 3 is a diagram illustrating a structure of a capacitor array in a segmented binary-weighted capacitor array type digital-to-analog converter in the prior art;

fig. 4 is a schematic flowchart illustrating a calibration method suitable for a capacitor array successive approximation analog-to-digital converter according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram illustrating a flow of sub-steps of step S110 in the calibration method shown in FIG. 4;

fig. 6 shows a schematic partial structural diagram of a binary SAR ADC with n bit differential inputs in an implementation manner provided by an embodiment of the present disclosure.

Detailed Description

To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are set forth in the accompanying drawings. However, the present disclosure may be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

The present disclosure is described in detail below with reference to the accompanying drawings.

The simplest conventional binary capacitor array consists of C, C, 2C, 4C, …, 2^ (n-1) C, corresponding to the weights of different bits in the binary, n is the resolution of the ADC, C is the unit capacitor, and the total number of capacitors is 2^ n C. The bridge capacitor array can reduce the total capacitance by introducing bridge capacitors between the capacitor arrays, the capacitor array is divided into two C, 2C, … 2^ (n/2-1) C arrays which are connected by the bridge capacitor Cc, the total capacitance is about 2^ (n/2+1) C, and the capacitor array can be further divided into more small capacitor arrays to further reduce the capacitance.

Fig. 1 shows a system block diagram of a successive approximation analog-to-digital converter in the prior art. Referring to fig. 1, a conventional successive approximation analog-to-digital converter (SAR ADC) 100 generally includes a bias and clock circuit 110, a sample-and-hold circuit 120, a comparator 130, a logic controller 140, and a digital-to-analog converter (DAC)150, where Vi is the input signal, Vref is the reference signal, and Dout is the analog-to-digital converter output code. The outputs of the sample-and-hold circuit 120 and the DAC 150 are inputs to the comparator 130; the comparator 130 gives a comparison result according to the magnitude of the double-ended input voltage thereof, and serves as an input of the logic controller 140; the logic controller 140 thus gives the control signals and the final output code of the DAC 150; the bias and clock circuit 110 is responsible for providing clock and voltage and current bias for each module of the chip. The simple working process is summarized as follows: firstly, Vi andcomparing Vi with Vi according to the comparison resultOrAnd comparing by analogy successive approximation for n times to obtain n-bit output.

The SAR ADC can be divided into many classes according to the difference of the embedded digital-to-analog converter, wherein the capacitor array type digital-to-analog converter is widely adopted. As shown in fig. 2: appointing VRP as a positive reference voltage, VRN as a negative reference voltage, VCM as a common-mode voltage, VIP as a positive input voltage and VIN as a negative input voltage; the capacitor array is divided into two ends of P and N, the P end has (N +1) capacitors, the lower polar plate is controlled by the logic controller 140 to be selectively connected with VRP, VRN or VIP through the three-terminal switch, and the upper polar plates of all (N +1) capacitors are connected with VRP, VRN or VIPTogether, its output voltage is VP; n terminal hasThe lower plates of the (n +1) capacitors are selectively connected with VRP, VRN or VIN through a three-terminal switch under the control of the logic controller 140, the upper plates of all the (n +1) capacitors are connected together, and the output voltage is VN. The output voltages VP and VN are respectively connected with the input of the positive end and the input of the negative end of the rear-stage comparator. As mentioned in the foregoing, the digital-to-analog converter based on the binary capacitor array type mainly has the following advantages: the capacitor array has a sampling and holding function; compared with a resistance type or current type digital-to-analog converter, the capacitor array type digital-to-analog converter has no static power consumption, and the energy consumption is mainly reflected in capacitor charging and discharging.

However, the existing capacitor array has the following two disadvantages for SAR ADC: firstly, the capacitor array is usually in the form of binary weights, so that the total capacitance increases as a power function with the conversion precision; secondly, the matching precision of the capacitor is limited. In fig. 2, convention c0 is the unit capacitance,for the mismatch of the ith bit capacitance of the P-side array,for the mismatch of the ith bit capacitance of the N-terminal array,andalso for mismatch coefficients, the true values of the capacitors shown in FIG. 2 can be expressed as. In view of the first problem, the mainstream improvement scheme at present is that a capacitor pair array adopts a segmented capacitor structure, as shown in fig. 3: VP, VN, VRP, VRN, VIP, VIN, c0 have the same meaning as in FIG. 2, and the capacitor array is also divided into P terminal and N terminalThe end, the near end of VP is appointed to be P-MS, the far end of VP is appointed to be P-LS, and the two ends pass through a bridge capacitor C_PSThe connection is carried out in a connecting way,for the mismatch of the ith bit capacitance of the P-MS end array,the mismatch of the ith bit capacitance of the P-LS terminal array,is C_PSMismatch compared to unit capacitance; the VN near end is N-MS, the VN far end is N-LS, and the VN near end and the VN far end pass through a bridge capacitor C_NSThe connection is carried out in a connecting way,mismatch of an ith capacitor of the N-MS end array;mismatch of ith bit capacitance of the N-LS end array;is C_NSCompared to the mismatch of unit capacitance. The actual values of the capacitors shown in FIG. 3 can be expressed asAnd. The structure shown in fig. 3 can reduce the total capacitance by times, but each segment still has the form of binary weight, and the influence of capacitance mismatch still exists; however, the second problem is that many schemes are proposed by predecessors in terms of layout and calibration, such as adding a virtual redundant capacitor to the layout, adopting a common-center structure, and the like, and these methods can overcome inherent errors caused by uneven thickness of the dielectric plate due to process production conditions to a certain extent, but also bring about two problems: firstly, the connection is complex and the parasitic is serious; number of dummy redundant capacitorsThe method is considerable and the area efficiency is greatly reduced.

In addition to the layout-level method, there are various calibration methods to compensate for the error caused by the capacitance matching problem, such as a method for calibrating the capacitor array in the successive approximation capacitance analog-to-Digital converter, which is also the most similar to the present invention, Chun c.lee et al, in the context of "a 12b 70MS/s SAR ADC with Digital start calibration in 14nm CMOS" proposed by the study on VLSI circuits in 2015, indicate that the difference between the two codewords of 011111 and 100000 (caused by the error of MSB), the difference between x01111 and x10000 (caused by the error of MSB-1 bit), and so on, the error of Difference Nonlinearity (DNL) is accumulated to the final Digital correction. The correction process comprises the following steps: before the normal conversion is started, the correction is started from the lowest bit needing to be corrected, the number of bits higher than the correction bit is ignored, the bits needing to be corrected are respectively forced to be 0 and 1, then the rest number of bits are converted and compared in a normal mode, one D + and one D-can be obtained, and the two are subtracted and divided by two to obtain the correction information of the bit; secondly, correcting the most significant bit from the first bit needing to be calibrated until the most significant bit is corrected to include error information of the lower significant bit, and recording the final correction information of the MSB by utilizing a register; after all the corrections are finished, at the end of each normal conversion, the correction information is added by an adder, and a final result is obtained through redundancy conversion, so that the aim of calibration is fulfilled. This method relies on redundancy below the 2-ary weight and there are deficiencies: since DNL drifts in a certain direction due to the presence of the comparator voltage offset, which makes the correction bits of the LSB a few bits insufficient to represent the error value containing the voltage offset, more redundancy needs to be added to cover the effect of the comparator voltage offset.

Based on this, on one hand, in order to avoid the redundancy requirement necessary for the non-binary weight analog-to-digital converter, so as to increase the circuit complexity and the calculation complexity, and on the other hand, in order to avoid the error in the above-mentioned weight calibration method based on the binary capacitor array, the present disclosure provides a calibration method of a capacitor array type successive approximation analog-to-digital converter, which is suitable for a single-ended or differential input analog-to-digital converter, and realizes the calibration of the weight deviation caused by the capacitor mismatch or the parasitic capacitance by the traditional binary capacitor array or the bridge capacitor array and the framework of realizing each bit weight by a single capacitor or a pair of equal capacitors.

The calibration method provided by the disclosure breaks through the requirement that the non-binary weight must meet redundancy, can realize weight calibration on the traditional binary analog-to-digital converter, and realizes digital correction through simple addition and subtraction on the basis of the original code obtained by analog-to-digital conversion, thereby avoiding the circuit complexity and the calculation complexity caused by the non-binary weight.

Fig. 4 is a schematic flowchart of a calibration method suitable for a capacitor array successive approximation analog-to-digital converter according to an embodiment of the present disclosure, fig. 5 is a schematic diagram of a flow of a sub-step of step S110 in the calibration method shown in fig. 4, and fig. 6 is a schematic diagram of a partial structure of a binary SAR ADC with n bit differential inputs according to an implementation manner provided by an embodiment of the present disclosure.

The calibration method of the capacitor array type successive approximation analog-to-digital converter provided by the embodiment of the disclosure is suitable for a single-ended or differential input analog-to-digital converter, and the capacitance in the successive approximation analog-to-digital converter follows the proportion of binary weight from low order to high order. In the present embodiment, the successive approximation type analog-to-digital converter is exemplified by a differential input analog-to-digital converter 200, as shown in fig. 6. The differential input analog-to-digital converter 200 is an n-bit differential input binary SAR ADC, which at least includes: the capacitor array 210 comprises a positive capacitor array 211 and a negative capacitor array 212, wherein the lower plate of any positive capacitor Ci _ P is connected with any one of a positive input voltage VINP, a positive reference voltage VRP and a negative reference voltage VRN through a one-out-of-three switch, the connection node of the upper plate and the positive output end VP of the positive capacitor array 211 is connected with a common voltage VCM through a one-out-of-three switch, the lower plate of any negative capacitor Ci _ N is connected with any one of a negative input voltage VINN, a positive reference voltage VRP and a negative reference voltage VRN through a one-out-of-three switch, the connection node of the upper plate and the negative output end VN of the negative capacitor array 212 is connected with the common voltage VCM through the one-out switch, the positive output end VP of the positive capacitor array 211 is connected with the non-phase input end of the comparator 220, the negative output end of the negative capacitor array 212 is connected with the anti-phase input end of the comparator 220, the comparator 220 provides a comparison result (represented by a logic high-low level) according to a magnitude relation between voltages at two ends of the positive output end VP and the negative output end VN, and feeds back the comparison result to switches of the positive capacitor array 211 and the negative capacitor array 212 through the logic controller 230, wherein the logic controller 230 is configured to control the differential input analog-to-digital converter 200 to switch between a calibration state (for measuring a capacitor, calculating a weight, and storing a weight) and a normal analog-to-digital conversion state; on the other hand, for providing timing control signals for each switch, the connection selection of each switch (three-out-of-one switch, single-out switch) in the capacitor array 210 is determined by the logic controller 230 according to the input of the comparator 220 and the current operation mode. Referring to fig. 4, the calibration method includes:

step 110: and acquiring an actual weight value of the target bit capacitor and an error code between the actual weight value and an ideal weight value of the corresponding target bit capacitor.

Step 120: and correspondingly adding or subtracting the output code of the analog-to-digital converter to be calibrated by using the error code to obtain the finally calibrated output code.

With reference to fig. 4-6, the capacitor array 210 has n-1 pairs of capacitors between the positive output terminal VP and the negative output terminal VN, which correspond to each binary bit weight, and the binary minimum bit (LSB) has no actual capacitor, and can be regarded as a dummy capacitor. The capacitance in the positive capacitor array 211 or the negative capacitor array 212 follows a binary weighted ratio from low to high, namely: the value of the ith bit capacitor is 2 times that of the ith-1 bit capacitor. Ideally, the weight of each bit capacitor corresponds to the value of each binary bit, such as the weight ω of the ith bit capacitor_iIs that。

Due to the capacitance mismatch, there is an error e between the capacitance weight corresponding to each bit of the binary and the ideal value_iWherein, in the step (A),，ω_i，ω_i，idealthe actual and ideal weights of the ith bit capacitance, respectively, are, where i =0,1, 2, …, n-1.

In step S110, the actual weight value ω of the capacitance of the target bit (e.g. ith bit) is obtained_iAnd the actual weight value omega_iIdeal weight value omega corresponding to target position capacitance_i，idealThe error coding can specifically include the following substeps S111-substep S117, referring to fig. 5:

substep S111: and initializing target bit positive capacitors in the positive capacitor array and sampling.

In sub-step S111, the target bit capacitance includes a target bit positive capacitance and a target bit negative capacitance. Connecting the lower plate of a target (i-th) positive capacitor Ci _ p in the positive capacitor array 211 with a positive reference voltage VRP, connecting the lower plates of other positive capacitors with a negative reference voltage VRN, connecting the lower plate of a target (i-1 th) negative capacitor Ci-1_ n in the negative capacitor array 212 with the positive reference voltage VRP, connecting the lower plates of other negative capacitors with the negative reference voltage VRN, connecting the upper plates of all positive capacitors in the positive capacitor array 211 with a common voltage VCM through a single-selection switch, and connecting the upper plates of all negative capacitors in the negative capacitor array 212 with the common voltage VCM through the single-selection switch, namely = VP VN = VCM;

then, the common voltage VCM is turned off, and sampling is performed, so that the capacitance charges of the positive capacitor array 211 and the negative capacitor array 212 are kept constant.

In connection with fig. 6, assuming that k = n-1 to i +1, and i-2 to 1 arbitrary bits, the initialization process is:

vk _ p = VRN, Vk _ n = VRN, Vi _ p = VRP, Vi _ n = VRN, Vi-1_ p = VRN, Vi-1_ n = VRP, VP = VN = VCM, where Vk _ p is a one-out-of-three switch to which the lower plate of the positive capacitor at the K-th bit is connected, Vk _ n is a one-out-of-three switch to which the lower plate of the negative capacitor at the K-th bit is connected, Vi _ p is the voltage of the lower plate of the positive capacitor at the i-th bit, Vi _ n is the voltage of the lower plate of the negative capacitor at the i-th bit, and similarly, Vi-1_ p and Vi-1_ n are the voltage of the lower plate of the positive capacitor at the i-1-th bit and the voltage of the lower plate of the negative capacitor at the i-1-th bit, respectively, and sampling is performed by initializing the capacitors and switches, and then disconnecting the common voltage terminal.

Substep S112: and obtaining a first weight error voltage of the target bit capacitor by switching the plate voltage state of the target bit capacitor and the next bit capacitor through logic control.

In sub-step S112, the logic controls the plate voltage state of the positive capacitor of the target bit (i-th bit) and its next bit (i-1-th bit) to be switched, so that the lower plate of the positive capacitor of the target bit (i-th bit) in the positive capacitor array 211 is switched to be connected to the negative reference voltage VRN, and the lower plate of the positive capacitor of the next bit (i-1 th bit) of the target bit is switched to connect to the positive reference voltage VRP, the lower plate of the negative capacitor of the next bit (i-1 th bit) of the target bit in the negative capacitor array 212 is switched to connect to the negative reference voltage VRN, the aforementioned first weighted error voltage VP-VN is generated between the positive output terminal VP of the positive capacitor array 211 and the negative output terminal VN of the negative capacitor array 212, the first weight error voltage VP-VN represents an actual weight value ω of the target bit positive capacitance Ci _ p (i-th bit positive capacitance, which is named similarly and will not be described in detail)._i,0Subtracting the sum omega of the actual weight value of the positive capacitor Ci-1_ p next to the target position and the actual weight value of the negative capacitor Ci-1_ n next to the target position_i-1The latter difference.

In the present embodiment, specifically, referring to fig. 6, the connection state of the switches is logically controlled so that Vi _ p = VRN, Vi _ n = VRN, Vi-1_ p = VRP, and Vi-1_ n = VRN, so that the first weight error voltage VP-VN is generated between the positive output terminal VP of the positive capacitor array 211 and the negative output terminal VN of the negative capacitor array 212.

In the case of an ideal match, Ci _ p = Ci _ n =2 Ci-1_ p =2 Ci-1_ n,i.e. the voltage value of VP-VN is zero. But this voltage may be positive or negative due to capacitance matching mismatch.

Substep S113: and converting the first weighted error voltage by using differential analog-to-digital conversion to obtain a first weighted error voltage code of the target bit capacitor.

In sub-step S113, the first weighted error voltage code is represented by the capacitance of the next two bits (i-2 nd bit) of the target bit to the lowest bit capacitance. Specifically, an i-1 bit code b of the first weighted error voltage is obtained by converting the i-2 nd bit capacitor to the lowest bit capacitor using differential analog-to-digital conversion_i-2b_i-1…b₀。

（2）

Substep S114: and initializing a target potential negative capacitor in the negative capacitor array and sampling.

In sub-step S114, the lower plate of the positive capacitor Ci-1_ p next to the target position in the positive capacitor array 211 is connected to the positive reference voltage VRP, the lower plates of the other positive capacitors are connected to the negative reference voltage VRN, the lower plate of the negative capacitor Ci _ n next to the target position in the negative capacitor array 121 is connected to the positive reference voltage VRP, the lower plates of the other negative capacitors are connected to the negative reference voltage VRN, the upper plates of the positive capacitors in the positive capacitor array 211 are connected to the common voltage VCM through the one-way switch, the upper plates of the negative capacitors in the negative capacitor array 212 are connected to the common voltage VCM through the one-way switch, that is, VP = VN = VCM, and then the common voltage VCM is disconnected, and sampling is performed, so that the capacitor charges of the positive capacitor array 211 and the negative capacitor array 212 are kept constant.

With reference to fig. 6, the initialization process is:

vk _ p = VRN, Vk _ n = VRN, Vi _ p = VRN, Vi _ n = VRP, Vi-1_ p = VRP, Vi-1_ n = VRN, VP = VN = VCM, where Vk _ p is a one-out-of-three switch to which the lower plate of the positive capacitor at the K-th bit is connected, Vk _ n is a one-out-of-three switch to which the lower plate of the negative capacitor at the K-th bit is connected, Vi _ p is the voltage of the lower plate of the positive capacitor at the i-th bit, Vi _ n is the voltage of the lower plate of the negative capacitor at the i-th bit, and similarly, Vi-1_ p and Vi-1_ n are the voltage of the lower plate of the positive capacitor at the i-1-th bit and the voltage of the lower plate of the negative capacitor at the i-1-th bit, respectively, and sampling is performed by initializing the capacitors and switches, and then disconnecting the common voltage terminal.

Substep S115: and obtaining a second weight error voltage of the target bit capacitor by switching the plate voltage state of the target bit capacitor and the next bit capacitor through logic control.

In the sub-step S115, the plate voltage states of the negative capacitors Ci _ n and Ci-1_ n next to the target bit in the negative capacitor array 212 are switched and communicated to the positive input voltage VRP by logic control, the lower plate of the negative capacitor Ci-1_ n next to the target bit in the negative capacitor array 212 is switched and communicated to the negative reference voltage VRN, the lower plate of the positive capacitor Ci-1_ p next to the target bit in the positive capacitor array 211 is switched and communicated to the negative reference voltage VRN, and the second weight error voltage VP is generated between the positive output terminal VP of the positive capacitor array 211 and the negative output terminal VN of the negative capacitor array 212, wherein the second weight error voltage VP-VN represents the actual weight value ω of the negative capacitor Ci _ n at the target bit_i,1Subtracting the sum omega of the actual weight value of the positive capacitor Ci-1_ p next to the target bit and the actual weight value of the negative capacitor Ci-1_ n next to the target bit_i-1The latter difference.

（3）

In the present embodiment, specifically, referring to fig. 6, the connection state of the switches is logically controlled so that Vi _ p = VRN, Vi _ n = VRN, Vi-1_ p = VRN, and Vi-1_ n = VRP, so that the second weight error voltage VP-VN is generated between the positive output terminal VP of the positive capacitor array 211 and the negative output terminal VN of the negative capacitor array 212.

In the case of an ideal match, Ci _ p = Ci _ n =2 Ci-1_ p =2 Ci-1_ n, i.e. the voltage value of VP-VN is zero. But this voltage could equally be positive or negative due to capacitance matching mismatch.

Substep S116: and converting the second weighted error voltage by using differential analog-to-digital conversion to obtain a second weighted error voltage code of the target bit capacitor.

In sub-step S116, the second weighted error voltage code is encoded by the next two bits (i-2 nd bit) of the target bit) Capacitance to lowest order capacitance. Specifically, using differential analog-to-digital conversion, i-1 bit encoding b of the weighted error voltage is obtained by converting the i-2 nd bit capacitance to the lowest bit capacitance_i-2b_i-1…b₀ 。

（4）

Substep S117: and obtaining an error code between the actual weight value and the ideal weight value of the target bit capacitor according to the first weight error voltage code and the second weight error voltage code.

In sub-step S117, the ith bit weight ω is obtained according to the first weighted error voltage code and the second weighted error voltage code_iAnd the weight error e_i：

（5）

（6）

（7）

The weight error e from the (m +1) th bit to the (n-1) th bit can be obtained by adopting the calibration method provided by the embodiment of the disclosure_iThen after the normal conversion is finished, the binary output code of the analog-digital converter to be calibrated is obtained initially_idealBy simple addition and subtraction, correct code can be obtained_correctNamely, the calibrated output code:

（8）

in another embodiment provided by the present disclosure, in the calibration method proposed in this embodiment, the foregoing steps are substantially the same as those in the previous embodiment, and then after obtaining the ith bit weight ω i through the formula (6) in the sub-step S117, the ith bit weight ω i may also be used to initially obtain the binary output code of the analog-to-digital converter to be calibrated_idealThe simple addition and subtraction is carried out to obtain the correct code_correctNamely, the calibrated output code:

（9）

wherein, b_iIs a corresponding code_idealThe ith bit of the binary code value.

In practical applications, any one of the calibration methods described in the above two embodiments may be selected according to practical application scenarios, so as to obtain the calibrated output code.

Optionally, the calibration method proposed by any one of the two embodiments may further include:

the proper unit capacitance C is selected to ensure that the capacitance weight error of the successive approximation analog-to-digital converter 200 from the lowest bit (LSB) to the next bit (mth bit) of the lowest calibration target bit (m +1 bit) is very small, so as to obtain the output code from the m +1 bit to the (n-1) th bit of the highest bit (MSB) after calibration, wherein the bit order of the lowest calibration target bit (m +1 bit) is lower than the bit order of the convertible highest bit (n-1 bit) of the successive approximation analog-to-digital converter 200, i.e. m is much smaller than n-1.

Therefore, the calibration method provided by the embodiment of the disclosure can realize calibration from m +1 bits to n-1 bits by using the above steps bit by bit, thereby obtaining all weights and weight errors, effectively avoiding the problem that the DNL drifts to a certain direction due to the existence of comparator voltage offset in binary weight calibration in the prior art, so that the correction bits of several bits of the LSB are not enough to represent the error value including the voltage offset, and improving the calibration precision and accuracy.

When the calibration method provided by the embodiment of the disclosure is applied to a single-ended or differential input analog-to-digital converter of a traditional binary capacitor array or a bridge capacitor array, each bit weight is realized by a single capacitor or a pair of equal capacitors, and the weight deviation caused by capacitor mismatch or parasitic capacitance can be calibrated. The calibration method breaks through the requirement that non-binary weights must meet redundancy, can realize weight calibration on the traditional binary analog-to-digital converter, and realizes digital correction by simple addition and subtraction on the basis of the original code obtained by analog-to-digital conversion. Thereby effectively avoiding the circuit complexity and the calculation complexity caused by non-binary weights.

Optionally, in an embodiment, the step of obtaining the actual weight value of the target bit capacitor and the error code between the actual weight value and the ideal weight value of the corresponding target bit capacitor may further include:

repeating the obtaining step to obtain a plurality of first weight error voltages and first weight error voltage codes, and a plurality of second weight error voltages and second weight error voltage codes;

respectively obtaining an average value of the plurality of first weight error voltage codes and an average value of the plurality of second weight error voltage codes;

and obtaining an error code between the actual weight value and the ideal weight value of the target bit capacitor according to the average value of the first weight error voltage code and the average value of the second weight error voltage code.

In another embodiment, the step of obtaining the actual weight value of the target bit capacitor and the error code between the actual weight value and the ideal weight value of the corresponding target bit capacitor may further include:

repeating the obtaining step to respectively obtain a plurality of first weight error voltage codes and a plurality of second weight error voltage codes;

calculating to obtain error codes between actual weight values and ideal weight values of a plurality of target bit capacitors;

the final error code is obtained by calculating the average of the plurality of error codes.

In the two embodiments, the mode of repeatedly obtaining and calculating the average value can effectively eliminate the interference of noise, and further improve the accuracy and precision of calibration.

In some embodiments, an appropriate capacitor size can be selected according to a capacitor production process to meet the low-order matching requirement, and then analog-to-digital conversion of the SAR ADC is used, so that different high-order weight bits can be selected accordingly for calibration, thereby obtaining an accurate bit weight and improving calibration efficiency.

Optionally, the foregoing calibration method may further include:

the bit width of the output code obtained after each calibration can be adjusted according to the preset precision requirement and/or the parameters of the static memory, so that the precision and the accuracy of the weight calibration are further improved. Wherein a static memory (SRAM) is used to store the actual weight values.

It should be noted that in the description of the present disclosure, it is to be understood that the terms "upper", "lower", "inner", and the like, indicate orientation or positional relationship, are only for convenience in describing the present disclosure and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present disclosure.

Further, in this document, the contained terms "include", "contain" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present disclosure, and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention as herein taught are within the scope of the present disclosure.