阅读说明：本技术 用于堆叠纳米带2d晶体管的电荷转移间隔体 (Charge transfer spacers for stacked nanoribbon 2D transistors ) 是由 K·马克西 C·多罗 K·P·奥布莱恩 C·内勒 A·V·佩努马季哈 T·戈萨维 U·E 于 2020-12-21 设计创作，主要内容包括：实施例包括二维(2D)半导体片晶体管以及形成这种器件的方法。在实施例中,一种半导体器件包括2D半导体片的堆叠体,其中,所述2D半导体片中的个体2D半导体片具有第一端和与第一端相对的第二端。在实施例中,第一间隔体在所述2D半导体片的第一端之上,并且第二间隔体在所述2D半导体片的第二端之上。实施例还包括在第一间隔体与第二间隔体之间的栅电极、与所述2D半导体片的第一端相邻的源极接触部和与所述2D半导体片的第二端相邻的漏极接触部。(Embodiments include two-dimensional (2D) semiconductor fin transistors and methods of forming such devices. In an embodiment, a semiconductor device includes a stack of 2D semiconductor dice, wherein individual ones of the 2D semiconductor dice have a first end and a second end opposite the first end. In an embodiment, a first spacer is over a first end of the 2D semiconductor fin and a second spacer is over a second end of the 2D semiconductor fin. Embodiments also include a gate electrode between the first and second spacers, a source contact adjacent to the first end of the 2D semiconductor fin, and a drain contact adjacent to the second end of the 2D semiconductor fin.)

1. A semiconductor device, comprising:

a stack of two-dimensional (2D) semiconductor tiles, wherein individual ones of the 2D semiconductor tiles have a first end and a second end opposite the first end;

a first spacer over the first end of the 2D semiconductor fin;

a second spacer over the second end of the 2D semiconductor wafer;

a gate electrode between the first spacer and the second spacer;

a source contact adjacent the first end of the 2D semiconductor fin; and

a drain contact adjacent the second end of the 2D semiconductor fin.

2. The semiconductor device of claim 1, wherein the 2D semiconductor fin comprises a transition metal dichalcogenide.

3. The semiconductor device according to claim 1 or 2, wherein the gate electrode is between the pair of 2D semiconductor fins.

4. The semiconductor device of claim 3, wherein the gate electrode is separated from the source contact and the drain contact by an insulating plug between the 2D semiconductor fins.

5. The semiconductor device according to claim 3, wherein the second gate electrode is around an outside of the pair of 2D semiconductor fins.

6. The semiconductor device of claim 1 or 2, wherein the first end of the 2D semiconductor fin is substantially coplanar with a surface of the first spacer, and wherein the second end of the 2D semiconductor fin is substantially coplanar with a surface of the second spacer.

7. The semiconductor device of claim 1 or 2, wherein a surface of the first spacer is recessed from the first end of the 2D semiconductor fin, and wherein a surface of the second spacer is recessed from the second end of the 2D semiconductor fin.

8. The semiconductor device of claim 1 or 2, wherein a bottommost 2D semiconductor fin comprises a protrusion extending below the source contact and the drain contact.

9. The semiconductor device of claim 8, wherein an insulating layer is disposed over the protrusion.

10. The semiconductor device of claim 1 or 2, wherein the first and second spacers are charge transfer materials.

11. The semiconductor device of claim 10, wherein the first and second spacers comprise aluminum and oxygen, or molybdenum and oxygen.

12. A method of forming a semiconductor device, comprising:

forming a stack of first and second layers in an alternating pattern over a substrate;

forming recesses into first and second ends of the stack to expose the substrate;

laterally recessing the second layer at the first end and the second end to form a lateral recess;

filling the lateral recess to form a first spacer at the first end and a second spacer at the second end;

removing the first layer;

forming a two-dimensional (2D) semiconductor wafer between the second layer, the first spacer, and the second spacer;

filling a space between the pair of the 2D semiconductor chips with a gate electrode;

forming a source contact adjacent to the first end of the 2D semiconductor fin; and

forming a drain contact adjacent to the second end of the 2D semiconductor fin.

13. The method of claim 12, further comprising:

removing the second layer after filling the space between the pair of the 2D semiconductor fins with the gate electrode; and

a second gate electrode is disposed around an exterior of the 2D semiconductor fin between the first spacer and the second spacer.

14. The method of claim 12 or 13, further comprising:

laterally recessing the gate electrode between the 2D semiconductor fins to form a second lateral recess; and

filling the second lateral recess with an insulating plug.

15. The method of claim 12 or 13, wherein the 2D semiconductor fin comprises a transition metal dichalcogenide.

16. The method of claim 12 or 13, wherein the first and second spacers are charge transfer materials.

17. The method of claim 16, wherein the first and second spacers comprise aluminum and oxygen, or molybdenum and oxygen.

18. The method of claim 12 or 13, wherein the first layer comprises aluminum and nitrogen, and wherein the second layer comprises gallium and nitrogen, or wherein the first layer comprises an oxide, and wherein the second layer comprises a nitride.

19. An electronic system, comprising:

a plate;

an electronic package coupled to the board; and

a die electrically coupled to the electronic package, wherein the die comprises:

a stack of two-dimensional (2D) semiconductor tiles, wherein individual ones of the 2D semiconductor tiles have a first end and a second end opposite the first end;

a first spacer over the first end of the 2D semiconductor fin;

a second spacer over the second end of the 2D semiconductor wafer;

a gate electrode between the first spacer and the second spacer;

a source contact adjacent the first end of the 2D semiconductor fin; and

a drain contact adjacent the second end of the 2D semiconductor fin.

20. The electronic system of claim 19, wherein the 2D semiconductor dice comprise a transition metal dichalcogenide.

Technical Field

Embodiments of the present disclosure relate to semiconductor devices, and more particularly, to nanoribbon two-dimensional (2D) transistors with charge transfer spacers.

Background

Scaling of features in integrated circuits has been a driving force behind the evolving semiconductor industry over the last decades. Scaling to smaller and smaller features enables an increase in the density of functional units over the limited chip area of a semiconductor chip. For example, shrinking transistor size allows for an increased number of memory or logic devices to be incorporated on a chip, thereby facilitating the manufacture of products with increased capacity. However, driving with larger and larger capacities is not without problems. The necessity to optimize the performance of each device becomes increasingly important.

In the fabrication of integrated circuit devices, the study of two-dimensional (2D) semiconductor devices, such as Transition Metal Dichalcogenides (TMDs), is becoming more prevalent as a way to provide further size reduction. In particular, TMD devices allow for improved short channel effects and allow for additional scaling of transistor devices. Scaling 2D semiconductor transistors, however, is not without consequence. As the size of these basic building blocks of microelectronic circuits decreases and the sheer number of basic building blocks fabricated in a given area increases, the constraints on the semiconductor processes used to fabricate these building blocks become greater.

Drawings

Fig. 1A is a cross-sectional view of a two-dimensional (2D) semiconductor device having charge transfer spacers according to an embodiment.

Fig. 1B is a cross-sectional view of a 2D semiconductor device with recessed charge transfer spacers according to an embodiment.

Fig. 1C is a cross-sectional view of a single gated (gated) 2D semiconductor device with charge transfer spacers according to an embodiment.

Fig. 2 is an energy band diagram illustrating charge transfer provided by the charge transfer spacers according to an embodiment.

Fig. 3A-3K are cross-sectional views depicting a process for forming a 2D semiconductor device with charge transfer spacers, according to an embodiment.

Fig. 4A and 4B are cross-sectional views depicting a process for forming a 2D semiconductor device with recessed charge transfer spacers according to an embodiment.

FIG. 5 illustrates a computing device in accordance with one implementation of embodiments of the present disclosure.

Fig. 6 is an interposer implementing one or more embodiments of the present disclosure.

Detailed Description

According to various embodiments, nanoribbon two-dimensional (2D) transistors with charge transfer spacers are described herein. In the following description, various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. It will be apparent, however, to one skilled in the art that the present invention may be practiced without specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

As mentioned above, scaling of two-dimensional (2D) semiconductor devices is not without problems. In particular, 2D semiconductor devices suffer from contact resistances that are at most an order of magnitude higher than those typically required for high performance devices. This is because the current inverse cannot be usedThe contact regions are selectively doped by the reactor, process, and integrated flow. For gate lengths L below approximately 10nm due to reduced short channel effects_gSingle layer 2D materials have the potential to be superior to silicon and III-V transistors. However, they require a considerable inherent channel quality with highly doped source/drain (S/D) regions to obtain proper on and off current. They may also need to be integrated in stacked nanoribbons to provide the required on-current per unit chip area.

The high on-current and the low off-current have been shown independently in the 2D transistor but not simultaneously. High on-current has been demonstrated by doping the entire semiconductor via substitutional dopants in chemical vapor transport or by charge transfer doping from oxides or molecules. Doping the entire semiconductor prevents the material from achieving low off-current due to the movement of the fermi level towards more free carriers not only in the contact region but also in the channel. This prevents the gate from turning off the channel. Low off-current has been shown for intrinsic Chemical Vapor Deposition (CVD) and stripped 2D materials, but both of them are contact resistances significantly greater than 100 Ω μm. The intrinsic material can be gated sufficiently to show an off current below 1pA/μm, but for the same drain bias, the on current is approximately 10 μ a/μm. Furthermore, there is no solution for stacking nanoribbon 2D material architectures.

Accordingly, embodiments disclosed herein include an integration scheme that allows for stacked transistor channels and spacer dielectrics for doping contact and access regions of a device. This charge transfer spacer architecture is fully compatible with 2D materials. Generally, the scheme includes forming a 2D nanosheet transistor, the 2D nanosheet transistor including an intrinsic channel and a contact region doped to move the fermi level closer to the conduction (or valence) band. Doping of the contact region is provided by forming charge transfer spacers around the contact region. This provides local doping of the contact region while allowing the channel region to remain intrinsic.

Referring now to fig. 1A, a cross-sectional view of a 2D nanosheet transistor 100 in accordance with an embodiment is shown. In an embodiment, the 2D nanosheet transistor 100 is formed over a substrate 101. The substrate 101 may be a semiconductor substrate. In an embodiment, the underlying semiconductor substrate 101 represents a common workpiece object for manufacturing integrated circuits. The semiconductor substrate 101 typically comprises a wafer or other component made of silicon or another semiconductor material. Suitable semiconductor substrates 101 include, but are not limited to, single crystal silicon, polycrystalline silicon, and silicon-on-insulator (SOI), as well as similar substrates formed of other semiconductor materials, such as substrates comprising germanium, carbon, or III-V materials.

In an embodiment, a stack of 2D semiconductor fins 110 is disposed over the substrate 101. As shown in cross-section, a pair of 2D semiconductor fins 110 (i.e., a bottom fin 110 and a top fin 110) are sandwiched between portions of the spacers 112. In some embodiments, the bottom portion and the top portion may be connected to each other out of the plane shown in fig. 1A to form a closed tubular structure. In some embodiments, the tubular structure may include an opening (e.g., along the length of the tube or a portion of the length of the tube) to provide an access point to contact the interior gate electrode 130 between pairs of 2D semiconductor fins 110_I. In the illustrated embodiment, four pairs of 2D semiconductor wafers 110 are shown in the stack. However, it should be understood that any number of 2D semiconductor dice 110 may be provided in the transistor 100. In an embodiment, the barrier layer 111 may be disposed over the 2D semiconductor fin 110.

In an embodiment, the 2D semiconductor fin 110 may include any suitable 2D semiconductor material. The 2D semiconductor material is a natural semiconductor, the thickness of which is on an atomic scale. For example, the 2D semiconductor material may have a thickness provided by a single atomic layer of material (i.e., a single layer of 2D semiconductor material). In other embodiments, the 2D semiconductor fin 110 may include several layers of 2D semiconductor material. In particular embodiments, the 2D semiconductor fin 110 may include van der waals 2D material (2D material for short). One class of 2D materials is Transition Metal Dichalcogenides (TMDs). TMD is a class of two-dimensional materials, which generally have the formula MX₂Wherein M represents a transition metal and X represents a chalcogen, such as sulfur, selenium or tellurium. For example, the TMD semiconductor tiles 110 may include, but are not limited to MoS₂、WS₂、MoSe₂And WSe₂. It should be understood that the 2D material is not limited to TMD. For example, the 2D material may also include indium selenide (InSe).

In an embodiment, the 2D semiconductor dice 110 may be double gated. That is, the inner and outer surfaces of the 2D semiconductor wafer 110 may be gated. Internal gate electrode 130_IProvided between the pair of 2D semiconductor fins 110, and an external gate electrode 130_EAn internal gate electrode 130 provided on each of the 2D semiconductor fins 110_IOn the opposite surface. In the illustrated embodiment, each gate electrode 130 is shown as a single layer for simplicity. However, it should be understood that the high-k dielectric may be between the conductive material of the gate electrode and the 2D semiconductor fin.

In an embodiment, the S/D contacts 105 are provided on opposite ends of the 2D semiconductor fin 110. The S/D contact 105 may be a highly doped semiconductor material or a conductive material. In an embodiment, the S/D contact 105 passes through the insulating plug 122 and the internal gate electrode 130 at the end of the 2D semiconductor fin 110_IAnd (4) isolating. For example, the insulating plug 122 may be an oxide or a nitride. In an embodiment, the insulating layer 123 may be disposed on the bottommost inner gate electrode 130_IOver the exposed portions of the 2D semiconductor fin 110, the exposed portions extending outwardly beyond the edges of the 2D semiconductor fin 110.

In an embodiment, a pair of spacers 112 may be provided over opposite ends of the 2D semiconductor fin 110. For example, the pair of 2D semiconductor fins 110 may be sandwiched between portions of the spacers 112. The spacers 112 may be formed of a material that allows charge transfer doping within the contact regions (i.e., the end regions contacted by the S/D contacts 105) of the 2D semiconductor dice 110. For example, the spacers 112 may include a material such as, but not limited to, aluminum oxide or molybdenum oxide. Furthermore, since the spacers 112 are positioned to the ends of the 2D semiconductor fin 110, the channel region is substantially undoped (i.e., intrinsic). This provides a low off current for the transistor device 100.

An example of charge transfer doping is provided in the energy band diagram 250 of fig. 2. As shown, the spacers include interstitial defect sites that are capable of donating charge carriers to the TMD semiconductor material. This allowsFermi level E_fMoving closer to the conduction band E_C. Thus, the contact resistance of the TMD is reduced.

Referring now to fig. 1B, a cross-sectional view of a transistor device 100 is shown, according to additional embodiments. In an embodiment, the transistor device 100 in fig. 1B is substantially similar to the transistor device 100 in fig. 1A, except that the spacers 112 are laterally recessed. As shown, a recess 113 is provided at an outer edge of the spacer body 112. The recess 113 may then be filled by the S/D contact 105. Such an embodiment provides an increased surface area interface between the 2D semiconductor fin 110 and the S/D contact 105.

Referring now to fig. 1C, a cross-sectional view of a transistor device 100 is shown, according to yet another embodiment. The transistor device 100 in fig. 1C may be substantially similar to the transistor device 100 in fig. 1A, except that the external gate electrode 130 is omitted_E. Instead, an insulating layer 142 is provided around the 2D semiconductor fin 110. Such an embodiment may be referred to as a single-gated transistor device 100 because the gate is only present along the interior surface of the 2D semiconductor dice 110.

Referring now to fig. 3A-3K, a series of cross-sectional views depicting a process for forming a semiconductor device 300 is shown, in accordance with an embodiment. The semiconductor device 300 may be substantially similar to the semiconductor device 100 in fig. 1A.

Referring now to fig. 3A, a cross-sectional view of a semiconductor device 300 at a fabrication stage is shown, according to an embodiment. In an embodiment, the stack 340 is disposed over the substrate 301. Stack 340 may include alternating first layers 341 and second layers 342. The first layer 341 and the second layer 342 may be materials having etch selectivity with respect to each other. In a particular embodiment, first layer 341 may include aluminum nitride and second layer 342 may include gallium nitride. In an alternative embodiment, the first layer 341 may include an oxide and the second layer 342 may include a nitride. In an embodiment, the protective barrier layer 311 may be disposed over a top surface of the stack 340.

Referring now to fig. 3B, a cross-sectional view of the semiconductor device 300 after forming a recess 343 at an end of the stack 340 is shown, according to an embodiment. In an embodiment, stack 340 may be etched using a dry etch process to form recess 343. The recess 343 may expose a surface of the substrate 301. The etching process may be a dry etching process that etches both the first layer 341 and the second layer 342.

Referring now to fig. 3C, a cross-sectional view of semiconductor device 300 after forming lateral recess 344 in second layer 342 is shown, according to an embodiment. In an embodiment, lateral recesses 344 may be formed with a wet etch chemistry that selectively etches second layer 342 while substantially not altering first layer 341. In an embodiment, the etch is a timed etch to provide a recess of a desired size.

Referring now to fig. 3D, a cross-sectional view of the semiconductor device 300 is shown after filling the lateral recess 344 with spacers 312, in accordance with an embodiment. In an embodiment, the spacers 312 are a material that provides charge transfer to a subsequently formed 2D semiconductor fin. For example, the spacers 312 may include aluminum oxide or molybdenum oxide. In an embodiment, the spacers 312 may be deposited with an Atomic Layer Deposition (ALD) process.

Referring now to fig. 3E, a cross-sectional view of the semiconductor device 300 after the first layer 341 is removed is shown, in accordance with an embodiment. In an embodiment, the removal of first layer 341 provides openings 345 between second layers 342. First layer 341 may be removed with a wet etch chemistry that is selective to first layer 341 relative to second layer 342 and spacers 312.

Referring now to fig. 3F, a cross-sectional view of the semiconductor device 300 after forming the 2D semiconductor fin 310 in the opening 345 is shown, according to an embodiment. In the illustrated embodiment, four pairs of 2D semiconductor dice 310 are provided₁-310₄. However, more or less 2D semiconductor dice 310 may be provided by increasing or decreasing the number of first layers 341 and second layers 342. As shown in the cross-sectional view, each pair of 2D semiconductor dice 310 includes a top dice and a bottom dice. It should be understood that the top and bottom sheets may be coupled together out of the plane of fig. 3F to provide a tubular structure. In some embodiments, the tubular structure may include an opening (e.g., along the length of the tube or a portion of the length of the tube) to provide an access point to contactInternal gate electrodes within the 2D semiconductor dice 310 that will be deposited in subsequent processing operations.

In an embodiment, the 2D semiconductor fin 310 includes a single layer of 2D semiconductor material. In other embodiments, the 2D semiconductor dice 310 include several layers of 2D semiconductor material. In an embodiment, the 2D semiconductor comprises a TMD, such as but not limited to MoS₂、WS₂、MoSe₂Or WSe₂. The 2D semiconductor may also include InSe. In an embodiment, the 2D material is disposed on the exposed surface by a Metal Organic Chemical Vapor Deposition (MOCVD) process, utilizing ALD and a chalcogenide process, or any other suitable process. Since the deposition process is conformal, the bottom most 2D semiconductor wafer 310₁May extend beyond an edge of the spacer body 312. In addition, portions of the 2D material may be deposited along the sidewalls between the pair of sheets 310 due to the conformal deposition process. For example, the top sheet 310₁May be coupled out of the plane of fig. 3F to the bottom sheet 310₁. In such an embodiment, the semiconductor wafer 310 may be part of a tubular structure.

Referring now to FIG. 3G, an internal gate electrode 330 is shown, according to an embodiment_IA cross-sectional view of the semiconductor device 300 after being disposed over the inner surfaces of the 2D semiconductor fins 310 (i.e., between pairs of 2D semiconductor fins 310). In the illustrated embodiment, the inner gate electrode 330_IMay include a high-k dielectric material (not shown) in direct contact with the 2D semiconductor dice 310 and a conductive electrode over the high-k dielectric material. That is, the high-k dielectric material may be used to couple the inner gate electrode 330_IIs separated from the inner surface of the 2D semiconductor wafer 310. The high-k dielectric material and the conductive material may be deposited using an ALD process or the like. In a conformal deposition process, the inner gate electrode 330_IMay extend over the portion 316 of the bottommost 2D semiconductor fin 310 beyond the outer edge of the spacer 312. In embodiments, portions 336 and 316 may be etched away, or portions 336 and 316 may remain in the final device as the remainder of the fabrication.

Referring now to fig. 3H, a cross-sectional view of semiconductor device 300 after removing second layer 342 is shown, according to an embodiment. Removing the remaining portion of the second layer 342 allows dual gate control of the 2D semiconductor dice 310, as will be described below. However, in embodiments where dual gate control is not required, second layer 342 may remain in place to form a structure similar to semiconductor device 100 in fig. 1C. In an embodiment, the second layer 342 may be removed with a wet etch process.

Referring now to fig. 3I, forming an external gate electrode 330 around a 2D semiconductor fin 310 according to an embodiment is shown_EFollowed by a cross-sectional view of the semiconductor device 300. External gate electrode 330_EFilling the space vacated by the second layer 342. In an embodiment, the outer gate electrode 330_EMay be formed with the internal gate electrode 330_ISubstantially the same material. For example, the outer gate electrode 330_EMay include a high-k dielectric in direct contact with the 2D semiconductor dice 310 and a conductive material over the high-k dielectric.

Referring now to FIG. 3J, an illustration of an inner gate electrode 330 is shown, in accordance with an embodiment_IA cross-sectional view of the semiconductor device 300 after laterally recessing and providing the insulating plugs 322 in the recess. The insulating plug 322 connects the subsequently deposited S/D contact with the inner gate electrode 330_IAnd (4) electrically isolating. In embodiments having remaining portions 336 and 316, insulation barrier 323 may be deposited over remaining portions 336 to provide electrical isolation from the S/D contacts.

Referring now to fig. 3K, a cross-sectional view of the semiconductor device 300 after forming the S/D contacts 305 adjacent to the 2D semiconductor fin 310 is shown, according to an embodiment. In an embodiment, the S/D contact 305 is a highly doped semiconductor material or a conductive material. In an embodiment, the inner and outer gate electrodes 330 may be contacted by contact metal provided out of the plane of fig. 3K between the S/D contacts 305_IAnd 330_E。

Referring now to fig. 4A and 4B, cross-sectional views of alternative contacting schemes according to embodiments are provided. In an embodiment, the resulting semiconductor device 400 in fig. 4B may be substantially similar to the semiconductor device 100 in fig. 1B.

Referring now to FIG. 4A, a root is shownA cross-sectional view of the semiconductor device 400 at a stage of fabrication according to an embodiment. The processing up to fig. 4A may be substantially similar to the processing described above with respect to fig. 3A-3J, and will not be repeated here. The semiconductor device 400 includes a substrate having a stack of 2D semiconductor dice 410 over the substrate 401. The barrier layer 411 covers the stack of 2D semiconductor dice 410. Internal gate electrode 430_IWithin the 2D semiconductor wafer 410, and an external gate electrode 430_ESurrounding the exterior of the 2D semiconductor wafer 410. The plug 422 covers an end of the 2D semiconductor wafer 410.

In an embodiment, spacers 412 around the ends of 2D semiconductor dice 410 have been laterally recessed to form recesses 447. The spacers 412 may be recessed with a wet etch process. Recessing the spacers 412 provides an increased interface area between the 2D semiconductor fin 410 and subsequently deposited S/D contacts.

Referring now to fig. 4B, a cross-sectional view of the semiconductor device 400 after forming the S/D contacts 405 is shown, according to an embodiment. As shown, the recess 447 is filled with S/D contact 405 such that the S/D contact wraps around the end of the 2D semiconductor fin 410.

FIG. 5 illustrates a computing device 500 in accordance with one implementation of embodiments of the present disclosure. The computing device 500 houses a board 502. The board 502 may include a number of components including, but not limited to, a processor 504 and at least one communication chip 506. The processor 504 is physically and electrically coupled to the board 502. In some implementations, at least one communication chip 506 is also physically and electrically coupled to the board 502. In other implementations, the communication chip 506 is part of the processor 504.

Depending on its application, computing device 500 may include other components that may or may not be physically and electrically coupled to board 502. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a Global Positioning System (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., hard disk drive, Compact Disk (CD), Digital Versatile Disk (DVD), etc.).

The communication chip 506 enables wireless communication for transferring data to and from the computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 506 may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and higher. The computing device 500 may include a plurality of communication chips 506. For example, a first communication chip 506 may be dedicated to shorter range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip 506 may be dedicated to longer range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and the like.

The processor 504 of the computing device 500 includes an integrated circuit die packaged within the processor 504. In an embodiment, an integrated circuit die of a processor may include a transistor device having a 2D semiconductor fin with spacers for charge transfer to reduce contact resistance, such as those described herein. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 506 also includes an integrated circuit die packaged within the communication chip 506. In an embodiment, an integrated circuit die of a communication chip may include a transistor device having a 2D semiconductor fin with spacers for charge transfer to reduce contact resistance, such as those described herein.

In other implementations, another component housed within the computing device 500 may include a transistor device having a 2D semiconductor fin with spacers for charge transfer to reduce contact resistance, such as those described herein.

In various implementations, the computing device 500 may be a laptop computer, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a Personal Digital Assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In other implementations, the computing device 500 may be any other electronic device that processes data.

Fig. 6 illustrates an interposer 600 including one or more embodiments of the present disclosure. Interposer 600 is an intervening substrate used to bridge first substrate 602 to second substrate 604. The first substrate 602 may be, for example, an integrated circuit die. The second substrate 604 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. In an embodiment, one of the first substrate 602 and the second substrate 604 may include a transistor device having a 2D semiconductor fin with spacers for charge transfer to reduce contact resistance according to embodiments described herein. Generally, the purpose of interposer 600 is to spread connections to a wider pitch or to reroute connections to different connections. For example, the interposer 600 may couple an integrated circuit die to a Ball Grid Array (BGA)606, which may then be coupled to a second substrate 604. In some embodiments, first substrate 602 and second substrate 604 are attached to opposite sides of interposer 600. In other embodiments, first and second substrates 602/604 are attached to the same side of interposer 600. And in other embodiments, three or more substrates are interconnected by interposer 600.

Interposer 600 may be formed from epoxy, fiberglass reinforced epoxy, ceramic material, or polymeric material such as polyimide. In other embodiments, interposer 600 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 608 and vias 610, including but not limited to Through Silicon Vias (TSVs) 612. Interposer 600 may also include embedded devices 614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as Radio Frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on interposer 600. According to embodiments of the present disclosure, the apparatus or process disclosed herein may be used to fabricate interposer 600.

Accordingly, embodiments of the present disclosure may include transistor devices having 2D semiconductor fins with spacers for charge transfer to reduce contact resistance, and the resulting structures.

The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Example 1: a semiconductor device, comprising: a stack of two-dimensional (2D) semiconductor tiles, wherein individual ones of the 2D semiconductor tiles have a first end and a second end opposite the first end; a first spacer over a first end of the 2D semiconductor fin; a second spacer over a second end of the 2D semiconductor wafer; a gate electrode between the first spacer and the second spacer; a source contact adjacent to a first end of the 2D semiconductor fin; and a drain contact adjacent to a second end of the 2D semiconductor fin.

Example 2: the semiconductor device of example 1, wherein the 2D semiconductor fin comprises a transition metal dichalcogenide.

Example 3: the semiconductor device of example 1 or example 2, wherein the gate electrode is between the pair of the 2D semiconductor fins.

Example 4: the semiconductor device of example 3, wherein the gate electrode is separated from the source contact and the drain contact by an insulating plug between the 2D semiconductor dice.

Example 5: the semiconductor device of example 3, wherein the second gate electrode is around an exterior of the pair of 2D semiconductor fins.

Example 6: the semiconductor device of examples 1-5, wherein the first end of the 2D semiconductor fin is substantially coplanar with a surface of the first spacer, and wherein the second end of the 2D semiconductor fin is substantially coplanar with a surface of the second spacer.

Example 7: the semiconductor device of examples 1-6, wherein a surface of the first spacer is recessed from the first end of the 2D semiconductor fin, and wherein a surface of the second spacer is recessed from the second end of the 2D semiconductor fin.

Example 8: the semiconductor device of examples 1-7, wherein the bottommost 2D semiconductor fin includes a protrusion extending below the source contact and the drain contact.

Example 9: the semiconductor device of example 8, wherein an insulating layer is disposed over the protrusion.

Example 10: the semiconductor device of examples 1-9, wherein the first and second spacers are charge transfer materials.

Example 11: the semiconductor device of example 10, wherein the first and second spacers comprise aluminum and oxygen, or molybdenum and oxygen.

Example 12: a method of forming a semiconductor device, comprising: forming a stack of first and second layers in an alternating pattern over a substrate; forming recesses into the first and second ends of the stack to expose the substrate; laterally recessing the second layer at the first end and the second end to form a lateral recess; filling the lateral recess to form a first spacer at the first end and a second spacer at the second end; removing the first layer; forming a two-dimensional (2D) semiconductor wafer between the second layer, the first spacer and the second spacer; filling a space between the pair of 2D semiconductor fins with a gate electrode; forming a source contact adjacent to a first end of the 2D semiconductor fin; and forming a drain contact adjacent to a second end of the 2D semiconductor fin.

Example 13: the method of example 12, further comprising: removing the second layer after filling the space between the pair of 2D semiconductor fins with the gate electrode; and disposing a second gate electrode around an exterior of the 2D semiconductor fin between the first spacer and the second spacer.

Example 14: the method of example 12 or example 13, further comprising: laterally recessing the gate electrode between the 2D semiconductor fins to form a second lateral recess; and filling the second lateral recess with an insulating plug.

Example 15: the method of examples 12-14, wherein the 2D semiconductor fin comprises a transition metal dichalcogenide.

Example 16: the method of examples 12-15, wherein the first and second spacers are charge transfer materials.

Example 17: the method of example 16, wherein the first and second spacers comprise aluminum and oxygen, or molybdenum and oxygen.

Example 18: the method of examples 12-17, wherein the first layer comprises aluminum and nitrogen, and wherein the second layer comprises gallium and nitrogen, or wherein the first layer comprises an oxide, and wherein the second layer comprises a nitride.

Example 19: an electronic system, comprising: a plate; an electronic package connected to the board; and a die electrically coupled to the electronic package, wherein the die comprises: a stack of two-dimensional (2D) semiconductor tiles, wherein individual ones of the 2D semiconductor tiles have a first end and a second end opposite the first end; a first spacer over a first end of the 2D semiconductor fin; a second spacer over a second end of the 2D semiconductor wafer; a gate electrode between the first spacer and the second spacer; a source contact adjacent to a first end of the 2D semiconductor fin; and a drain contact adjacent to a second end of the 2D semiconductor fin.

Example 20: the electronic system of example 19, wherein the 2D semiconductor fin comprises a transition metal dichalcogenide.