阅读说明：本技术 基于栅源漏一体化沉积的氮化镓器件及其制作方法 (Gallium nitride device based on gate-source-drain integrated deposition and manufacturing method thereof ) 是由 马晓华 司泽艳 芦浩 侯斌 杨凌 鲁微 武玫 郝跃 于 2021-08-25 设计创作，主要内容包括：本发明公开了一种基于栅源漏一体化沉积的氮化镓器件,氮化镓器件包括：衬底、AlN成核层、GaN缓冲层、AlGaN势垒层、以及位于AlGaN势垒层远离衬底一侧的SiN钝化层、源电极、漏电极和栅电极；AlGaN势垒层的第一表面包括两个图形区,每个图形区包括多个阵列排布的第一开孔,源、漏电极相对设置于第一表面的两侧,且沿垂直于衬底所在平面的方向,漏电极的正投影与源电极的正投影分别覆盖两个图形区；SiN钝化层位于源电极和漏电极之间,SiN钝化层包括第二开孔,至少部分栅电极位于第二开孔内。本发明采用一体化沉积的设计方式制作氮化镓器件,能够避免源漏金属高温退火工艺,抑制金属外扩,并实现亚微米级源漏欧姆接触。(The invention discloses a gallium nitride device based on gate-source-drain integrated deposition, which comprises: the GaN-based light-emitting diode comprises a substrate, an AlN nucleating layer, a GaN buffer layer, an AlGaN barrier layer, and an SiN passivation layer, a source electrode, a drain electrode and a gate electrode which are positioned on one side of the AlGaN barrier layer away from the substrate; the first surface of the AlGaN barrier layer comprises two pattern areas, each pattern area comprises a plurality of first openings which are arranged in an array mode, a source electrode and a drain electrode are oppositely arranged on two sides of the first surface, and the orthographic projection of the drain electrode and the orthographic projection of the source electrode respectively cover the two pattern areas along the direction perpendicular to the plane where the substrate is located; the SiN passivation layer is located between the source electrode and the drain electrode, the SiN passivation layer comprises a second opening, and at least part of the gate electrode is located in the second opening. The invention adopts the design mode of integrated deposition to manufacture the gallium nitride device, can avoid the high-temperature annealing process of source and drain metal, inhibit the metal from expanding outwards and realize the submicron-level source and drain ohmic contact.)

1. A gallium nitride device based on gate-source-drain integrated deposition is characterized by comprising: a substrate;

an AlN nucleation layer on one side of the substrate;

a GaN buffer layer positioned on one side of the AlN nucleating layer far away from the substrate;

the AlGaN barrier layer is positioned on one side of the GaN buffer layer, which is far away from the substrate;

the SiN passivation layer, the source electrode, the drain electrode and the gate electrode are positioned on one side, far away from the substrate, of the AlGaN barrier layer; wherein the content of the first and second substances,

the AlGaN barrier layer comprises a first surface far away from one side of the GaN buffer layer, the first surface comprises two graphic regions, each graphic region comprises a plurality of first openings which are arranged in an array, the source electrode and the drain electrode are oppositely arranged on two sides of the first surface, and along the direction perpendicular to the plane of the substrate, the orthographic projection of the drain electrode and the orthographic projection of the source electrode respectively cover the two graphic regions;

the SiN passivation layer is located between the source electrode and the drain electrode, the SiN passivation layer comprises a second opening, the second opening penetrates through the SiN passivation layer in the direction perpendicular to the plane where the substrate is located, the gate electrode is located on one side, far away from the substrate, of the SiN passivation layer, and at least part of the gate electrode is located in the second opening.

2. The gallium nitride device based on gate-source-drain integration deposition of claim 1, wherein the length of the pattern region is 5-20 μm along the direction from the source electrode to the drain electrode.

3. The gallium nitride device based on gate-source-drain integrated deposition of claim 2, wherein the orthographic projection of the first opening along the direction perpendicular to the plane of the substrate is circular or polygonal.

4. The gallium nitride device based on gate-source-drain integrated deposition of claim 1, wherein the depth of the first opening is 5-20 μm in a direction perpendicular to the plane of the substrate.

5. A manufacturing method of a gallium nitride device based on gate-source-drain integrated deposition is characterized by comprising the following steps:

providing an epitaxial substrate, wherein the epitaxial substrate comprises a substrate, and an AlN nucleating layer, a GaN buffer layer and an AlGaN barrier layer which are sequentially grown on the substrate in advance;

cleaning the epitaxial substrate, and etching the epitaxial substrate to the buffer layer;

depositing a SiN film on the AlGaN barrier layer by utilizing a Plasma Enhanced Chemical Vapor Deposition (PECVD) process to form a SiN passivation layer;

coating photoresist on the SiN passivation layer, photoetching to form an opening region, a source electrode region and a drain electrode region, and etching away the SiN passivation layer below the opening region, the SiN passivation layer below the source electrode region and the SiN passivation layer below the drain electrode region;

coating photoresist on the SiN passivation layer, performing preset pattern region photoetching in a source electrode region and a drain electrode region respectively, and etching by using ICP equipment to form a plurality of first openings arranged in an array;

coating photoresist on the SiN passivation layer, forming a gate electrode region, a source electrode region and a drain electrode region by photoetching, and depositing a gate source drain metal layer on the gate electrode region, the source electrode region and the drain electrode region;

and carrying out low-temperature rapid thermal annealing treatment in a rapid thermal annealing furnace to form ohmic contact, and then manufacturing the gallium nitride device.

6. The method for manufacturing a gate-source-drain integrally deposited gallium nitride device according to claim 5, wherein the gate-source-drain metal layer is deposited by a Sputter magnetron sputtering or electron beam evaporation process.

7. The method for manufacturing the gallium nitride device based on the gate-source-drain integrated deposition of claim 6, wherein the gate source-drain metal layer comprises a contact layer/a catalytic layer/a barrier layer/a cap layer.

8. The method of claim 7, wherein the step of forming the GaN device comprises forming a GaN layer on the substrate, and forming a GaN layer on the substrateIn that the contact layer comprises Ti/Ta/Ti_xAl_y/Ta_zAl_yThe catalytic layer comprises Al, the barrier layer comprises Ta/Ti/Ni/Mo, and the cap layer comprises Au/TiN/TiW/TiC/TaN/Pt; wherein x represents an atomic ratio of Ti, y represents an atomic ratio of Al, and z represents an atomic ratio of Ta.

9. The method for manufacturing a gallium nitride device based on gate-source-drain integrated deposition according to claim 5, wherein the annealing temperature is 300-600 ℃ when performing low-temperature rapid thermal annealing in a rapid thermal annealing furnace

10. The gate-source-drain integrally deposited gallium nitride device according to claim 5, wherein said step of cleaning said epitaxial substrate comprises:

placing the epitaxial substrate into acetone, ultrasonically cleaning for 2min, and placing into positive photoresist stripping liquid heated in water bath at 60 ℃ for boiling for 10 min;

placing the epitaxial substrate into acetone for ultrasonic cleaning for 3min, and placing the epitaxial substrate into ethanol for ultrasonic cleaning for 3 min;

washing off residual acetone and ethanol on the surface of the epitaxial substrate by using deionized water, and washing for 30s by using HF;

and cleaning the epitaxial substrate by using deionized water, and drying the epitaxial substrate by using ultrapure nitrogen.

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a gallium nitride device based on gate-source-drain integrated deposition and a manufacturing method thereof.

Background

The GaN-based device has excellent performances of high electron saturation drift velocity, high breakdown field strength, large heat conductivity and the like, so compared with Si and GaAs, the GaN-based device can better meet the requirements of the development of the modern society on high frequency and high power. The AlGaN/GaN HEMT device has the advantages in the aspect of high microwave power due to the fact that the heterojunction is provided with the two-dimensional electron gas channel with high electron concentration.

At present, the related art generally adopts a gold-containing process to manufacture a GaN-based device. The AlGaN/GaNHEMT device is formed by laminating Ti/Al/Ni/Au ohmic metal in an annealing furnace and quickly thermally annealing to form ohmic contact, and then depositing Ni/Au metal to form a gate electrode. However, higher annealing temperatures cause the molten Al to react with the Au to form AlAu₄The ohmic contact surface is rough and the ohmic edge expands outwards, so that the rough ohmic contact edge can cause the appearance of a peak electric field, and the breakdown characteristic of the device is reduced; especially for microwave devices, non-uniform current distribution and high signal attenuation are also caused. On the other hand, when the device works at a large current, the bulge on the surface of the ohmic contact metal can be cracked, and the reliability of the device is affected.

In addition, the preparation cost of the Au-containing ohmic electrode and the gate electrode is high, and Au-containing high-temperature ohmic annealing cannot be applied to the preparation of a self-aligned gate device and cannot be heterogeneously integrated with a Si-based CMOS control element.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a gallium nitride device based on gate-source-drain integrated deposition and a manufacturing method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:

in a first aspect, the present invention provides a gallium nitride device based on gate-source-drain integrated deposition, comprising: a substrate;

an AlN nucleation layer on one side of the substrate;

a GaN buffer layer positioned on one side of the AlN nucleating layer far away from the substrate;

the AlGaN barrier layer is positioned on one side of the GaN buffer layer, which is far away from the substrate;

the SiN passivation layer, the source electrode, the drain electrode and the gate electrode are positioned on one side, far away from the substrate, of the AlGaN barrier layer; wherein the content of the first and second substances,

the AlGaN barrier layer comprises a first surface far away from one side of the GaN buffer layer, the first surface comprises two graphic regions, each graphic region comprises a plurality of first openings which are arranged in an array, the source electrode and the drain electrode are oppositely arranged on two sides of the first surface, and along the direction perpendicular to the plane of the substrate, the orthographic projection of the drain electrode and the orthographic projection of the source electrode respectively cover the two graphic regions;

the SiN passivation layer is located between the source electrode and the drain electrode, the SiN passivation layer comprises a second opening, the second opening penetrates through the SiN passivation layer in the direction perpendicular to the plane where the substrate is located, the gate electrode is located on one side, far away from the substrate, of the SiN passivation layer, and at least part of the gate electrode is located in the second opening.

In one embodiment of the present invention, the length of the pattern region is 5 to 20 μm in a direction from the source electrode to the drain electrode.

In one embodiment of the invention, the orthographic projection of the first opening is circular or polygonal along the direction perpendicular to the plane of the substrate.

In one embodiment of the invention, the depth of the first opening is 5-20 μm in a direction perpendicular to the plane of the substrate.

In a second aspect, the present invention provides a method for manufacturing a gallium nitride device based on gate-source-drain integrated deposition, including:

providing an epitaxial substrate, wherein the epitaxial substrate comprises a substrate, and an AlN nucleating layer, a GaN buffer layer and an AlGaN barrier layer which are sequentially grown on the substrate in advance;

cleaning the epitaxial substrate, and etching the epitaxial substrate to the buffer layer;

depositing a SiN film on the AlGaN barrier layer by utilizing a Plasma Enhanced Chemical Vapor Deposition (PECVD) process to form a SiN passivation layer;

coating photoresist on the SiN passivation layer, photoetching to form an opening region, a source electrode region and a drain electrode region, and etching away the SiN passivation layer below the opening region, the SiN passivation layer below the source electrode region and the SiN passivation layer below the drain electrode region;

coating photoresist on the SiN passivation layer, photoetching in preset pattern areas in a source electrode area and a drain electrode area respectively, and etching by using ICP equipment to form a plurality of first openings which are arranged in an array manner;

coating photoresist on the SiN passivation layer, forming a gate electrode region, a source electrode region and a drain electrode region by photoetching, and depositing a gate source drain metal layer on the gate electrode region, the source electrode region and the drain electrode region;

and carrying out low-temperature rapid thermal annealing treatment in a rapid thermal annealing furnace to form ohmic contact, and then manufacturing the gallium nitride device.

In one embodiment of the invention, the gate source drain metal layer is deposited by using a Sputter magnetron sputtering or electron beam evaporation process.

In one embodiment of the invention, the gate source drain metal layer comprises a contact layer/catalytic layer/barrier layer/cap layer.

In one embodiment of the invention, the contact layer comprises Ti/Ta/Ti_xAl_y/Ta_zAl_yThe catalytic layer comprises Al, the barrier layer comprises Ta/Ti/Ni/Mo, and the cap layer comprises Au/TiN/TiW/TiC/TaN/Pt; wherein x represents an atomic ratio of Ti, y represents an atomic ratio of Al, and z represents an atomic ratio of Ta.

In one embodiment of the present invention, the annealing temperature when the low-temperature rapid thermal annealing is performed in the rapid thermal annealing furnace is 300 to 600 ℃.

In one embodiment of the present invention, the step of cleaning the epitaxial substrate comprises:

placing the epitaxial substrate into acetone, ultrasonically cleaning for 2min, and placing into positive photoresist stripping liquid heated in water bath at 60 ℃ for boiling for 10 min;

placing the epitaxial substrate into acetone for ultrasonic cleaning for 3min, and placing the epitaxial substrate into ethanol for ultrasonic cleaning for 3 min;

washing off residual acetone and ethanol on the surface of the epitaxial substrate by using deionized water, and washing for 30s by using HF;

and cleaning the epitaxial substrate by using deionized water, and drying the epitaxial substrate by using ultrapure nitrogen.

Compared with the prior art, the invention has the beneficial effects that:

the invention provides a gallium nitride device based on integrated deposition of a gate source and a drain and a manufacturing method thereof, wherein a gate source and drain metal layer is directly deposited in a gate electrode area, a source electrode area and a drain electrode area obtained by photoetching when a source electrode, a gate electrode and a drain electrode are manufactured, and the integrated deposition design mode can avoid overlay errors of the gate electrode, the source electrode and the drain electrode, so that submicron-level source-drain ohmic contact is realized; in addition, the manufacturing method carries out low-temperature rapid thermal annealing treatment in a rapid thermal annealing furnace to form ohmic contact, thereby being beneficial to reducing the transverse diffusion of the GaN device after annealing at the positions of the source electrode and the drain electrode, and further realizing the preparation of the ultrahigh frequency device.

In addition, the manufacturing method of the GaN device provided by the invention adopts a gold-free process, is compatible with a Si-based CMOS production line, can greatly improve the productivity, and can be used for carrying out heterogeneous integration on the manufactured GaN device and a Si-based CMOS control element.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

FIG. 1 is a schematic structural diagram of a GaN device based on gate-source-drain integrated deposition according to an embodiment of the invention;

FIG. 2 is a top view of a graphics area provided by an embodiment of the present invention;

FIG. 3 is another top view of a graphics area provided by an embodiment of the present invention;

FIG. 4 is another top view of a graphics area provided by an embodiment of the present invention;

fig. 5 is a schematic flow chart of a method for manufacturing a gallium nitride device based on gate-source-drain integrated deposition according to an embodiment of the present invention;

FIG. 6 is a schematic process diagram of a method for fabricating a GaN device based on gate-source-drain integrated deposition according to an embodiment of the invention;

FIG. 7 is a schematic process diagram of another method for manufacturing a GaN device based on gate-source-drain integrated deposition according to the embodiment of the invention;

FIG. 8 is a schematic process diagram of another method for fabricating a GaN device based on gate-source-drain integrated deposition according to the embodiment of the invention;

fig. 9 is a schematic process diagram of another method for manufacturing a gallium nitride device based on gate-source-drain integrated deposition according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Fig. 1 is a schematic structural view of a gan device based on gate-source-drain integrated deposition according to an embodiment of the present invention, and fig. 2 is a top view of a pattern region according to an embodiment of the present invention. Referring to fig. 1-2, an embodiment of the present invention provides a gallium nitride device based on gate-source-drain integrated deposition, including: a substrate 1;

an AlN nucleation layer 2 on one side of the substrate 1;

a GaN buffer layer 3 positioned on one side of the AlN nucleating layer 2 far away from the substrate 1;

an AlGaN barrier layer 4 positioned on the GaN buffer layer 3 on the side away from the substrate 1;

a SiN passivation layer 5, a source electrode 6, a drain electrode 7 and a gate electrode 8 which are positioned on one side of the AlGaN barrier layer 4 away from the substrate 1; wherein the content of the first and second substances,

the AlGaN barrier layer 4 comprises a first surface S1 far away from one side of the GaN buffer layer 3, the first surface S1 comprises two graphic areas A, each graphic area A comprises a plurality of first openings B1 arranged in an array, the source electrode 6 and the drain electrode 7 are oppositely arranged on two sides of the first surface S1, and along the direction perpendicular to the plane of the substrate 1, the orthographic projection of the drain electrode 7 and the orthographic projection of the source electrode 6 respectively cover the two graphic areas A;

the SiN passivation layer 5 is located between the source electrode 6 and the drain electrode 7, the SiN passivation layer 5 comprises a second opening B2, the second opening B2 penetrates through the SiN passivation layer 5 in a direction perpendicular to the plane of the substrate 1, the gate electrode 8 is located on the side of the SiN passivation layer 5 away from the substrate 1, and at least part of the gate electrode 8 is located in the second opening B2.

Specifically, the gallium nitride device includes a substrate 1, and an AlN nucleation layer 2, a GaN buffer layer 3, and an AlGaN barrier layer 4 grown in this order on one side of the substrate 1, wherein the AlGaN barrier layer 4 includes a first surface S1 on the side away from the GaN buffer layer 3. Optionally, the gallium nitride device further includes a SiN passivation layer 5, a source electrode 6 and a drain electrode 7, the source electrode 6 and the drain electrode 7 are oppositely disposed on two sides of the first surface S1, the SiN passivation layer 5 is located on one side of the AlGaN barrier layer 4 away from the GaN buffer layer 3, that is, the SiN passivation layer 5 is in contact with the first surface S1, and an orthographic projection of the SiN passivation layer 5 is located between the source electrode 6 and the drain electrode 7 along a direction perpendicular to the plane of the substrate 1.

In this embodiment, the first surface S1 of the AlGaN barrier layer 4 further includes two pattern regions a, which are respectively located below the source electrode 6 and the drain electrode 7 in the viewing angle shown in fig. 1; as shown in fig. 2, each pattern region a includes a plurality of first openings B1 arranged in an array, and the first openings B1 are recessed toward a side close to the GaN buffer layer 3 in a direction perpendicular to the plane of the substrate 1. In the above gallium nitride device, the source electrode 6 and the first surface S1, and the drain electrode 7 and the first surface S1 are all in ohmic contact, it should be understood that, because the ohmic electrode has edge crowding effect, the current is mainly concentrated on the edges of the source electrode 6 and the drain electrode 7, in this embodiment, the pattern area a is disposed on one side (i.e., the edge of the source electrode 6) below the source electrode 6 close to the drain electrode 7, and one side (i.e., the edge of the drain electrode 7) below the drain electrode 7 close to the source electrode 6, and a first opening B1 array is etched through the AlGaN barrier layer 4 in the ohmic edge area of the source electrode 6 and the drain electrode 7, so that not only the contact area between the source electrode 6, the drain electrode 7 and the AlGaN barrier layer 4 is effectively increased, but also the tunneling probability of electrons of the AlGaN barrier layer 4 etched at the first opening B1 is improved, thereby reducing the ohmic contact resistance and the ohmic annealing temperature; in addition, the introduction of the first opening B1 can reduce the damage to the 2EDG to a large extent, i.e. a gold-free ohmic contact with high current and low resistance can be formed.

It should be noted that fig. 2 illustrates only the pattern region a under the source electrode 6 as an example, and the structure of the pattern region a under the drain electrode 7 is completely the same as that of the pattern region a.

Further, the SiN passivation layer 5 includes a second opening B2, and the second opening B2 penetrates the SiN passivation layer 5 in a direction perpendicular to the plane of the substrate 1, the gate electrode 8 is located on a side of the SiN passivation layer 5 away from the substrate 1, and at least a portion of the gate electrode 8 is located in the second opening B2.

Fig. 3-4 are alternative top views of a graphics area provided by embodiments of the present invention. Alternatively, the depth of the first openings B1 in the direction perpendicular to the plane of the substrate 1 is 5-20 μm, and the orthographic projection thereof may be circular, square or diamond. It should be understood that, in the direction perpendicular to the plane of the substrate 1, since the AlGaN barrier layer has a large thickness, if the depth of the first opening B1 is too small, the probability of electron tunneling between the ohmic metal and the 2DEG channel is extremely low, and thus the contact resistance is increased; on the contrary, if the etching depth of the first opening B1 is too large, the gold half contact barrier is reduced, but the 2DEG channel density in the adjacent region is also reduced, electrons can only tunnel through the contact sidewall of the metal and the semiconductor, the tunneling area of electrons is reduced, and the contact resistance is increased.

It should be noted that, in the present embodiment, the shape and the number of the first openings B1 in each pattern area a can be set according to actual requirements, and the present application is not limited thereto.

With reference to fig. 2-4, the length a of the pattern area a is 5-20 μm along the direction from the source electrode 6 to the drain electrode 7.

Specifically, because the current has edge concentration effect, the edge areas of the source electrode and the drain electrode are the main path of current transmission, so the length a of the pattern area A is not easy to be overlarge, and the overlarge pattern area A can cause the etched area of the AlGaN barrier layer to be enlarged, so that the density of two-dimensional electron gas generated by polarization is reduced, and on the other hand, the overlong length can cause the cross-sectional area of current transmission to be reduced, so that the contact resistance is increased; therefore, the length a of the pattern area A is set to be 5-20 mu m, so that the contact resistance of the device is reduced while the two-dimensional electronic air tightness is not reduced.

Fig. 5 is a schematic flow chart of a method for manufacturing a gallium nitride device based on gate-source-drain integrated deposition according to an embodiment of the present invention, and fig. 6 to 9 are schematic process diagrams of a method for manufacturing a gallium nitride device based on gate-source-drain integrated deposition according to an embodiment of the present invention. Referring to fig. 1, 5-9, an embodiment of the present invention further provides a method for manufacturing a gallium nitride device based on gate-source-drain integrated deposition, including:

s1, providing an epitaxial substrate, wherein the epitaxial substrate comprises a substrate 1, and an AlN nucleating layer 2, a GaN buffer layer 3 and an AlGaN barrier layer 4 which are sequentially grown on the substrate 1 in advance;

s2, cleaning the epitaxial substrate, and etching the epitaxial substrate to the buffer layer 3;

s3, depositing a SiN film on the AlGaN barrier layer 4 by utilizing a Plasma Enhanced Chemical Vapor Deposition (PECVD) process to form a SiN passivation layer 5;

s4, coating photoresist on the SiN passivation layer 5, forming an opening region, a source electrode region and a drain electrode region through photoetching, and etching away the SiN passivation layer 5 below the opening region, the SiN passivation layer 5 below the source electrode 6 region and the SiN passivation layer 5 below the drain electrode 7 region;

s5, coating photoresist on the SiN passivation layer 5, respectively carrying out photoetching on preset pattern areas in the source electrode area and the drain electrode area, and then etching by utilizing an ICP (inductively coupled plasma) device to form a plurality of first openings B1 in array arrangement;

s6, coating photoresist on the SiN passivation layer, forming a gate electrode area, a source electrode area and a drain electrode area through photoetching, and depositing a gate source drain metal layer on the gate electrode area, the source electrode area and the drain electrode area;

and S7, carrying out low-temperature rapid thermal annealing treatment in a rapid thermal annealing furnace to form ohmic contact, and then manufacturing the gallium nitride device.

Optionally, the step of cleaning the epitaxial substrate comprises:

placing the epitaxial substrate in acetone, ultrasonically cleaning for 2min, and decocting in positive photoresist stripping solution heated in water bath at 60 deg.C for 10 min;

placing the epitaxial substrate in acetone, ultrasonically cleaning for 3min, and placing in ethanol, and ultrasonically cleaning for 3 min;

washing off residual acetone and ethanol on the surface of the epitaxial substrate by using deionized water, and washing for 30s by using HF (hydrogen fluoride);

and cleaning the epitaxial substrate by using deionized water, and drying the epitaxial substrate by using ultrapure nitrogen.

Alternatively, in the step S2, the step of etching the epitaxial substrate to the buffer layer 3 after the step of cleaning the epitaxial substrate includes:

and S201, photoetching an electric isolation region on the AlGaN barrier layer 4.

Firstly, placing an epitaxial substrate on which an AlGaN barrier layer 4 grows on a hot plate at 200 ℃ and baking for 5 min; then, photoresist is thrown on the epitaxial substrate by using a photoresist spinner, wherein the rotating speed of the photoresist spinner is 3500 rpm; after photoresist throwing is finished, the epitaxial substrate is placed on a hot plate at the temperature of 90 ℃ and baked for 1min, and the epitaxial substrate is placed into a photoetching machine to expose the photoresist in the preset electric isolation area; and finally, putting the exposed epitaxial substrate into a developing solution to remove the photoresist in the preset electric isolation area, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist.

And S202, etching an electric isolation area on the AlGaN barrier layer 4.

And etching the AlGaN barrier layer 4 by adopting an ICP (inductively coupled plasma) process to form a step area on the epitaxial substrate subjected to photoetching, so as to realize the mesa isolation of the active area. Wherein the gas adopted for etching is Cl₂/BCl₃The pressure is 5mTorr, the power of the upper electrode is 100w,the lower electrode power is 10w, and the etching time is 40 s;

and S203, removing the etched mask.

And sequentially putting the epitaxial substrate subjected to active area isolation into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electrical isolation area, cleaning with deionized water and drying with nitrogen.

Optionally, in step S3, the step of depositing the SiN film on the AlGaN barrier layer 4 by using a plasma enhanced chemical vapor deposition PECVD process to form the SiN passivation layer 5 includes:

s301, cleaning the surface of the epitaxial substrate.

Firstly, putting an epitaxial substrate into an acetone solution, and ultrasonically cleaning the epitaxial substrate for 3mim, wherein the ultrasonic intensity can be 3.0; then, putting the epitaxial substrate into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min; then, the epitaxial substrate is sequentially placed into an acetone solution and an ethanol solution for ultrasonic cleaning for 3min, and the ultrasonic intensity is 3.0; finally, the epitaxial substrate was rinsed with ultrapure water and blown dry with nitrogen.

S302, growing a SiN passivation layer 5 with the thickness of 60nm on the AlGaN barrier layer 4 by utilizing a plasma enhanced chemical vapor deposition PECVD process, wherein the growing process conditions are as follows: NH3 and SiH4 are used as a Si source and an N source, and the optimized flow ratio is SiH 4: NH3 ═ 2: 1, the deposition temperature is 250 ℃, the pressure of the reaction chamber is 600mTorr, the RF power is 22W, and the reaction time is 7.5 min.

Further, in step S4, the steps of coating a photoresist on the SiN passivation layer, forming the opening region, the source electrode region and the drain electrode region by photolithography, and etching away the SiN passivation layer under the opening region, the SiN passivation layer under the source electrode region and the SiN passivation layer under the drain electrode region include:

s401, a hole region, a source electrode region and a drain electrode region are lithographically opened on the passivation layer 5.

Firstly, placing an epitaxial substrate which is etched on a hot plate at 200 ℃ for baking for 5 min; then, throwing a stripping glue on the epitaxial substrate, wherein the thickness of the throwing glue is 0.35 mu m, and drying the epitaxial substrate on a hot plate at the temperature of 200 ℃ for 5 min; then throwing photoresist on the epitaxial substrate, wherein the thickness of the photoresist is 0.77 mu m, and drying the epitaxial substrate on a hot plate at 90 ℃ for 1 min; and (3) placing the epitaxial substrate into a photoetching machine to expose the photoresist in the pattern area A, placing the exposed epitaxial substrate into a developing solution to remove the photoresist and the stripping resist in the hole area, the source electrode area and the drain electrode area, and then washing the epitaxial substrate with ultrapure water and drying the epitaxial substrate with nitrogen.

S402, removing the SiN passivation layer 5 below the opening area, the source electrode area and the drain electrode area through ICP dry etching.

Specifically, the reaction gas is CF by using an ICP device₄And O₂And the pressure of the reaction chamber is 10mTorr, and the radio frequency powers of the upper electrode and the lower electrode are 100W and 10W, respectively, removing at least a portion of the SiN passivation layer 5 under the source electrode region and the drain electrode region, and removing the passivation layer 5 to the barrier layer 4 under the gate region to form a second opening B2.

Further, in step S5, the step of coating a photoresist on the SiN passivation layer, performing photolithography on a predetermined pattern region in the source electrode region and the drain electrode region, and etching by using an ICP apparatus to form a plurality of first openings B1 arranged in an array includes:

and S501, photoetching a preset pattern area A on the passivation layer 5.

Firstly, placing an epitaxial substrate on a hot plate at 200 ℃ for baking for 5 min; then, throwing a stripping glue on the epitaxial substrate, wherein the thickness of the throwing glue is 0.35 mu m, and drying the epitaxial substrate on a hot plate at the temperature of 200 ℃ for 5 min; then throwing photoresist on the epitaxial substrate, wherein the thickness of the photoresist is 0.77 mu m, and drying the epitaxial substrate on a hot plate at 90 ℃ for 1 min; then, the epitaxial substrate is placed into a photoetching machine to expose the photoresist in the pattern area A; and finally, placing the exposed epitaxial substrate into a developing solution to remove the photoresist and the stripping resist in the pattern area A, and washing with ultrapure water and drying with nitrogen.

S502, etching a first opening B1 in the AlGaN barrier layer 4

For the epitaxial substrate after the photoetching, the AlGaN barrier layer 4 is etched by adopting an ICP (inductively coupled plasma) process in a dry method to realize the array opening of the pattern area AEtching holes with Cl as gas₂/BCl₃，BCl₃Flow rate 20sccm, Cl₂The flow rate is 8sccm, the pressure is 5mTorr, the upper electrode power is 50w, the lower electrode power is 15w, and the etching time is 60 s.

In the above step S6, the steps of coating a photoresist on the SiN passivation layer 5, forming a gate electrode region, a source electrode region, and a drain electrode region by photolithography, and depositing a gate source drain metal layer on the gate electrode region, the source electrode region, and the drain electrode region include:

s601, a gate electrode region, a source electrode region and a drain electrode region are etched on the passivation layer 5.

Firstly, placing an epitaxial substrate on a hot plate at 200 ℃ for baking for 5 min; then, throwing a stripping glue on the epitaxial substrate, wherein the thickness of the throwing glue is 0.35 mu m, and drying the epitaxial substrate on a hot plate at the temperature of 200 ℃ for 5 min; then throwing photoresist on the epitaxial substrate, wherein the thickness of the photoresist is 0.77 mu m, and drying the epitaxial substrate on a hot plate at 90 ℃ for 1 min; then, the epitaxial substrate is placed into a photoetching machine to expose the photoresist in the gate electrode area, the source electrode area and the drain electrode area; and finally, putting the exposed epitaxial substrate into a developing solution, removing the photoresist and the stripping glue in the gate electrode area, the source electrode area and the drain electrode area, and carrying out ultra-pure water washing and nitrogen blow-drying on the epitaxial substrate.

And S602, depositing a gate source drain metal layer by adopting a Sputter magnetron sputtering or electron beam evaporation process.

Firstly, removing an undeveloped photoresist thin layer of an epitaxial substrate subjected to photoetching in a gate region, a source region and a drain region by using a plasma photoresist remover, wherein the processing time is 5min, and the stripping yield can be effectively improved; then, the epitaxial substrate is placed in a sputtering table until the vacuum degree of a reaction chamber of the sputtering table reaches 2 multiplied by 10^-6And after Torr, sequentially sputtering the AlGaN barrier layers in the gate, source and drain electrode areas: a contact layer with a thickness of 20nm, a catalytic layer with a thickness of 20nm, a barrier layer with a thickness of 30nm, and a cap layer with a thickness of 60 nm.

Optionally, the contact layer comprises Ti/Ta/Ti_xAl_y/Ta_zAl_yThe catalytic layer comprises Al, the barrier layer comprises Ta/Ti/Ni/Mo, and the cap layer comprises Au/TiN/TiW/W/TiC/TaN/Pt; wherein x represents an atomic ratio of Ti, y represents an atomic ratio of Al, and z represents an atomic ratio of Ta.

And S603, stripping the metal.

Firstly, soaking an epitaxial substrate which is sputtered in acetone for more than 40 minutes and carrying out ultrasonic treatment; then, putting the epitaxial substrate into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min; then, the epitaxial substrate is sequentially placed into an acetone solution and an ethanol solution for ultrasonic cleaning for 3 min; subsequently, the epitaxial substrate was rinsed with ultrapure water and blown dry with nitrogen.

It should be understood that the conventional manufacturing process is to fabricate the source electrode 6 and the drain electrode 7, anneal them at an annealing temperature above 800 ℃ to form ohmic contacts, and then perform subsequent gate manufacturing, where too high an annealing temperature may cause gate failure. Therefore, in the present embodiment, in step S7, the annealing temperature in the low-temperature rapid thermal annealing is set to 300 to 600 ℃. Illustratively, the epitaxial substrate is placed in a rapid annealing furnace, nitrogen gas is introduced into the annealing furnace for 10min, and annealing is performed for 60s while the annealing furnace temperature is set to 500 ℃ in a nitrogen atmosphere, so that the ohmic metal of the source electrode 6, the drain electrode 7 and the first opening B1 sinks to the GaN buffer layer 3, thereby forming ohmic contact between the ohmic metal and the heterojunction channel.

The beneficial effects of the invention are that:

the invention provides a gallium nitride device based on integrated deposition of a gate source and a drain and a manufacturing method thereof, wherein a gate source and drain metal layer is directly deposited in a gate electrode area, a source electrode area and a drain electrode area obtained by photoetching when a source electrode, a gate electrode and a drain electrode are manufactured, and the integrated deposition design mode can avoid overlay errors of the gate electrode, the source electrode and the drain electrode, so that submicron-level source-drain ohmic contact is realized; in addition, the manufacturing method carries out low-temperature rapid thermal annealing treatment in a rapid thermal annealing furnace to form ohmic contact, thereby being beneficial to reducing the transverse diffusion of the GaN device after annealing at the positions of the source electrode and the drain electrode, and further realizing the preparation of the ultrahigh frequency device.

In addition, the manufacturing method of the GaN device provided by the invention adopts a gold-free process, is compatible with a Si-based CMOS production line, can greatly improve the productivity, and can be used for carrying out heterogeneous integration on the manufactured GaN device and a Si-based CMOS control element.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.

While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.