阅读说明：本技术 一种GaN低寄生钝化器件及其制备方法 (GaN low parasitic passivation device and preparation method thereof ) 是由 马晓华 芦浩 杨凌 侯斌 邓龙格 陈炽 武玫 张濛 郝跃 于 2021-08-25 设计创作，主要内容包括：本发明公开了一种GaN低寄生钝化器件及其制备方法,该器件包括：衬底层；GaN外延层,形成于衬底层上；源电极,形成于GaN外延层上；漏电极,形成于GaN外延层上；第一钝化层,形成于GaN外延层上；第二钝化层,形成于第一钝化层上,以和第一钝化层构成复合钝化层；第三钝化层,形成于源电极、漏电极与复合钝化层之间；T型栅电极,形成于GaN外延层上,贯穿于复合钝化层,且T型栅电极的横向部分位于第二钝化层上。本发明的方案,以T型栅电极为硬质掩膜,通过横向分区钝化,即可提高栅下钝化效果,亦可降低非栅区寄生电容,显著提高器件频率特性,降低高频下的电流崩塌；同时,通过栅金属作为硬质掩膜的分区钝化方式,工艺简单。(The invention discloses a GaN low parasitic passivation device and a preparation method thereof, wherein the device comprises: a substrate layer; a GaN epitaxial layer formed on the substrate layer; a source electrode formed on the GaN epitaxial layer; a drain electrode formed on the GaN epitaxial layer; a first passivation layer formed on the GaN epitaxial layer; a second passivation layer formed on the first passivation layer to form a composite passivation layer with the first passivation layer; the third passivation layer is formed among the source electrode, the drain electrode and the composite passivation layer; and the T-shaped gate electrode is formed on the GaN epitaxial layer and penetrates through the composite passivation layer, and the transverse part of the T-shaped gate electrode is positioned on the second passivation layer. According to the scheme, the T-shaped gate electrode is used as the hard mask, and the passivation effect under the gate can be improved through transverse partition passivation, the parasitic capacitance of a non-gate region can be reduced, the frequency characteristic of a device is obviously improved, and the current collapse under high frequency is reduced; meanwhile, the process is simple by a partition passivation mode with the gate metal as a hard mask.)

1. A GaN low parasitic passivation device, comprising:

a substrate layer;

the GaN epitaxial layer is formed on the substrate layer;

a source electrode formed on the GaN epitaxial layer;

the drain electrode is formed on the GaN epitaxial layer;

a first passivation layer formed on the GaN epitaxial layer;

a second passivation layer formed on the first passivation layer to form a composite passivation layer with the first passivation layer;

a third passivation layer formed between the source electrode, the drain electrode and the composite passivation layer, and on the source electrode and the drain electrode;

and the T-shaped gate electrode is formed on the GaN epitaxial layer and penetrates through the composite passivation layer, and the transverse part of the T-shaped gate electrode is positioned on the second passivation layer.

2. The GaN low parasitic passivation device of claim 1, wherein the first passivation layer is a high dielectric constant material; the second passivation layer and the third passivation layer are made of the same material and are both low-dielectric-constant materials.

3. The GaN low parasitic passivation device of claim 1, wherein the high dielectric constant material comprises SiN.

4. The GaN low parasitic passivation device of claim 1, wherein the low dielectric constant material comprises BN and BCB.

5. The GaN low parasitic passivation device of claim 1, wherein the GaN epitaxial layer comprises, from bottom to top, a nucleation layer, a buffer layer, a back barrier layer, a channel layer, and a barrier layer; the material of the back barrier layer comprises AlGaN or AlN; the material of the channel layer comprises InGaN; the barrier layer comprises AlGaN, and the Al component is 20-30%.

6. A preparation method of a GaN low-parasitic passivation device is characterized by comprising the following steps:

step 1, obtaining a GaN wafer;

the GaN wafer comprises a substrate layer and a GaN epitaxial layer on the substrate layer;

step 2, etching the GaN epitaxial layer to a specified position to realize active region isolation;

step 3, photoetching source electrode and drain electrode patterns at two ends of the upper surface of the GaN epitaxial layer, and evaporating ohmic contact metal in the source electrode and drain electrode pattern areas to form a source electrode and a drain electrode;

step 4, forming a first passivation layer on the GaN epitaxial layer;

step 5, forming a second passivation layer on the first passivation layer to form a composite passivation layer with the first passivation layer;

step 6, etching a gate groove penetrating through the composite passivation layer in the middle area of the source electrode and the drain electrode, and etching away the composite passivation layer on the source electrode and the drain electrode;

step 7, photoetching a grid electrode area on the second passivation layer, and depositing grid metal on the grid electrode area to form a T-shaped grid electrode;

step 8, etching off the composite passivation layer between the source gates and between the gate drains by using the T-shaped gates as hard masks;

step 9, forming third passivation layers between the source electrode and the T-shaped gate electrode, between the drain electrode and the T-shaped gate electrode, and on the source electrode and the drain electrode;

and 10, etching openings of the third passivation layer above the source electrode, the gate electrode and the drain electrode region, and depositing interconnection metal to finish the preparation of the device.

7. The method according to claim 6, wherein the step 1 comprises:

step 1.1, epitaxially growing a nucleation layer, a buffer layer, a back barrier layer, a channel layer and a barrier layer on a substrate layer from bottom to top in sequence to form a GaN wafer; the material of the back barrier layer comprises AlGaN or AlN; the material of the channel layer comprises InGaN; the barrier layer is made of AlGaN, and the Al component is 20-30%;

and 1.2, cleaning the surface of the GaN wafer to remove organic and inorganic stains and surface oxides in the growth process of the GaN wafer material.

8. The method for preparing a composite material according to claim 7, wherein the step 4 comprises:

step 4.1, cleaning the surface of the sample of which the source-drain ohmic contact is completed in the step 3;

and 4.2, growing a SiN passivation layer with the thickness of 20nm, namely a first passivation layer, on the barrier layer by using a plasma enhanced chemical vapor deposition process.

9. The method of claim 6, wherein the step 5 comprises:

step 5.1, growing a BN film on the copper foil;

step 5.2, a PMMA anisole solution is spin-coated on the BN film to form a PMMA/BN/copper structure;

step 5.3, removing copper in the PMMA/BN/copper structure by adopting a chemical method to obtain a transparent film with the PMMA/BN structure;

step 5.4, cleaning the transparent film with the PMMA/BN structure, and transferring the transparent film to the surface of the first passivation layer for surface mounting;

step 5.5, heating the device comprising the transparent film with the PMMA/BN structure;

and 5.6, cleaning the heated device containing the transparent film with the PMMA/BN structure, and removing the PMMA glue to obtain a BN film, namely a second passivation layer.

10. The method according to claim 6, wherein the third passivation layer and the second passivation layer are made of the same material and formed in the same manner.

Technical Field

The invention belongs to the technical field of microelectronics, and particularly relates to a GaN low-parasitic passivation device and a preparation method thereof.

Background

With the improvement of the technological level, the first and second generation semiconductor materials in the prior art can not meet the requirements of higher frequency and higher power electronic devices, and the electronic devices based on nitride semiconductor materials can meet the requirements, so that the device performance is greatly improved, and the third generation semiconductor materials represented by GaN are widely applied to the manufacture of microwave millimeter wave devices. GaN is a novel wide bandgap compound semiconductor material, and has many excellent characteristics that silicon-based semiconductor materials do not have, such as wide bandgap, high breakdown electric field, and higher thermal conductivity, and is corrosion-resistant and radiation-resistant. With the development of modern mobile communication and satellite and radar systems, devices face the challenge of exerting better performance in high-frequency working environments. Particularly, in the high-frequency application fields of 5G millimeter waves, even 6G terahertz waves, terahertz waves and the like of the prior art, the frequency characteristics of the prior device need to be optimized.

In order to repair surface defects and limit current collapse, a surface passivation technology is generally adopted in the device process at home and abroad at present to inhibit the current collapse effect, enhance the blocking capability of the device on foreign ion contamination and effectively reduce the current collapse caused by surface states. In addition, the surface passivation can also isolate the virtual grid effect caused by air ionization, thereby reducing the current collapse caused by the virtual grid effect. Specific methods for suppressing current collapse include:

in 2008, Masataka Higashiwaki et Al adopt measures such as AlGaN barrier layer with high Al component, SiN passivation layer grown by Cat-CVD and the like to grow AlGaN/GaN HEMT device with gate length of 60nm on a 4H-SiC substrate, wherein the 2DEG surface density is 2 multiplied by 1013cm-2, the 2DEG mobility of the device is 1900cm 2/(V.s), the saturation current is 1.6A/mm, and fT and fmax respectively reach 190GHz and 241 GHz. Reference [1] Higashiwaki M, Mimura T, Matsui T. GaN-based FETs using Cat-CVD SiN deposition for micrometer-wave applications [ J ]. Thin Solid Films,2008,516(5): 548-.

However, the method using the SiN passivation layer may result in a large parasitic capacitance of the device, which may result in a decrease in frequency characteristics, and is not suitable for high frequency applications. The current solution is to use a low dielectric constant low-k passivation layer. N.ramana et al, north carolina state university in 2013, significantly improved the frequency characteristics of the device using a low-k passivation layer structure of Atomic Layer Deposition (ALD) SiO 2. Reference [2] N.ramann, B.Lee, C.Kirkpatrick, R.Suri, and V.Misra, Properties of atomic layer-disposed dielectrics for AlGaN/GaN device application [ J ], semiconductor.Sci.Technol, 2013,28:074004.

In summary, the conventional global passivation technology is used internationally to optimize and improve the performance of the semiconductor surface. The passivation method can make the parasitic capacitance of the device large, resulting in the degradation of frequency characteristics, which is not favorable for the application in the high frequency field. The low dielectric constant passivation can reduce the parasitic capacitance of the device and improve the frequency characteristic of the device, but the surface state passivation effect of the device is general, so that the radio frequency current of the device collapses greatly and the device is not beneficial to large-signal work; and the low-k dielectric is easy to cause reverse leakage of the device, worsen the off-state characteristic and increase extra power consumption.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a GaN low parasitic passivation device and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:

in a first aspect, an embodiment of the present invention provides a GaN low parasitic passivation device, including:

a substrate layer;

the GaN epitaxial layer is formed on the substrate layer;

a source electrode formed on the GaN epitaxial layer;

the drain electrode is formed on the GaN epitaxial layer;

a first passivation layer formed on the GaN epitaxial layer;

a second passivation layer formed on the first passivation layer to form a composite passivation layer with the first passivation layer;

a third passivation layer formed between the source electrode, the drain electrode and the composite passivation layer, and on the source electrode and the drain electrode;

and the T-shaped gate electrode is formed on the GaN epitaxial layer and penetrates through the composite passivation layer, and the transverse part of the T-shaped gate electrode is positioned on the second passivation layer.

In one embodiment of the present invention, the first passivation layer is a high dielectric constant material; the second passivation layer and the third passivation layer are made of the same material and are both low-dielectric-constant materials.

In one embodiment of the invention, the high dielectric constant material comprises SiN.

In one embodiment of the present invention, the low dielectric constant material includes BN and BCB.

In one embodiment of the invention, the GaN epitaxial layer comprises a nucleation layer, a buffer layer, a back barrier layer, a channel layer and a barrier layer from bottom to top; the material of the back barrier layer comprises AlGaN or AlN; the material of the channel layer comprises InGaN; the barrier layer comprises AlGaN, and the Al component is 20-30%.

In a second aspect, an embodiment of the present invention further provides a method for manufacturing a GaN low parasitic passivation device, including:

step 1, obtaining a GaN wafer;

the GaN wafer comprises a substrate layer and a GaN epitaxial layer on the substrate layer;

step 2, etching the GaN epitaxial layer to a specified position to realize active region isolation;

step 3, photoetching source electrode and drain electrode patterns at two ends of the upper surface of the GaN epitaxial layer, and evaporating ohmic contact metal in the source electrode and drain electrode pattern areas to form a source electrode and a drain electrode;

step 4, forming a first passivation layer on the GaN epitaxial layer;

step 5, forming a second passivation layer on the first passivation layer to form a composite passivation layer with the first passivation layer;

step 6, etching a gate groove penetrating through the composite passivation layer in the middle area of the source electrode and the drain electrode, and etching away the composite passivation layer on the source electrode and the drain electrode;

step 7, photoetching a grid electrode area on the second passivation layer, and depositing grid metal on the grid electrode area to form a T-shaped grid electrode;

step 8, etching off the composite passivation layer between the source gates and between the gate drains by using the T-shaped gates as hard masks;

step 9, forming third passivation layers between the source electrode and the T-shaped gate electrode, between the drain electrode and the T-shaped gate electrode, and on the source electrode and the drain electrode;

and 10, etching openings of the third passivation layer above the source electrode, the gate electrode and the drain electrode region, and depositing interconnection metal to finish the preparation of the device.

In one embodiment of the present invention, the step 1 comprises:

step 1.1, epitaxially growing a nucleation layer, a buffer layer, a back barrier layer, a channel layer and a barrier layer on a substrate layer from bottom to top in sequence to form a GaN wafer; the material of the back barrier layer comprises AlGaN or AlN; the material of the channel layer comprises InGaN; the barrier layer is made of AlGaN, and the Al component is 20-30%;

and 1.2, cleaning the surface of the GaN wafer to remove organic and inorganic stains and surface oxides in the growth process of the GaN wafer material.

In one embodiment of the present invention, the step 4 comprises:

step 4.1, cleaning the surface of the sample of which the source-drain ohmic contact is completed in the step 3;

and 4.2, growing a SiN passivation layer with the thickness of 20nm, namely a first passivation layer, on the barrier layer by using a plasma enhanced chemical vapor deposition process.

In one embodiment of the present invention, the step 5 comprises:

step 5.1, growing a BN film on the copper foil;

step 5.2, a PMMA anisole solution is spin-coated on the BN film to form a PMMA/BN/copper structure;

step 5.3, removing copper in the PMMA/BN/copper structure by adopting a chemical method to obtain a transparent film with the PMMA/BN structure;

step 5.4, cleaning the transparent film with the PMMA/BN structure, and transferring the transparent film to the surface of the first passivation layer for surface mounting;

step 5.5, heating the device comprising the transparent film with the PMMA/BN structure;

and 5.6, cleaning the heated device containing the transparent film with the PMMA/BN structure, and removing the PMMA glue to obtain a BN film, namely a second passivation layer.

In one embodiment of the present invention, the third passivation layer and the second passivation layer are made of the same material and formed in the same method.

The invention has the beneficial effects that: the invention provides a GaN low parasitic passivation device and a preparation method thereof.A T-shaped gate electrode is used as a hard mask, a first passivation layer and a second passivation layer are formed below the T-shaped gate electrode, and third passivation layers are formed below the T-shaped gate electrode and between the first passivation layer and the second passivation layer as well as a source electrode and a drain electrode; the regional passivation aims at simultaneously solving the problems of reducing parasitic capacitance and current collapse, can obviously improve the frequency characteristic of a device and reduce the current collapse under high frequency. Meanwhile, the technical scheme of regional passivation between the source and the drain is realized by using the gate metal as a hard mask, the preparation process is simple, and the introduction of an additional photoetching step is avoided; and dry etching is adopted as anisotropy, so that the passivation layer under the gate is prevented from being over-etched. In addition, as a further effect, the first passivation layer is made of a high-dielectric-constant material, so that the reverse leakage of the grid electrode can be reduced; the second passivation layer and the third passivation layer are made of low-dielectric-constant materials, so that the generated parasitic parameters are small, and the frequency characteristics of the device can be improved.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

FIG. 1 is a schematic structural diagram of a GaN low parasitic passivation device provided by an embodiment of the invention;

FIG. 2 is a schematic flow chart of a method for manufacturing a GaN low parasitic passivation device according to an embodiment of the invention;

fig. 3a to fig. 3j are schematic process diagrams of a method for manufacturing a GaN low parasitic passivation device according to an embodiment of the present invention.

In the figure, 100, a substrate layer; 200. a GaN epitaxial layer; 201. a nucleation layer; 202. a buffer layer; 203. a back barrier layer; 204. a channel layer; 205. a barrier layer; 301. a source electrode; 302. a drain electrode; 303. a T-shaped gate electrode; 304. an interconnect metal; 401. a first passivation layer; 402. a second passivation layer; 403. and a third passivation layer.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

In a first aspect, embodiments of the present invention provide a GaN low parasitic passivation device. Referring to fig. 1, fig. 1 is a schematic structural diagram of a GaN low parasitic passivation device according to an embodiment of the present invention, where the GaN low parasitic passivation device according to the embodiment of the present invention includes: a substrate layer 100, a GaN epitaxial layer 200, a passivation layer, and source, drain, and gate electrodes; wherein the content of the first and second substances,

a GaN epitaxial layer 200 is formed on the substrate layer 100; a source electrode 301 is formed on the GaN epitaxial layer 200; a drain electrode 302 is formed on the GaN epitaxial layer 200; a first passivation layer 401 is formed on the GaN epitaxial layer 200; a second passivation layer 402 is formed on the first passivation layer 401 to form a composite passivation layer with the first passivation layer 401; a third passivation layer 403 is formed between the source electrode 301, the drain electrode 302 and the composite passivation layer, and on the source electrode 301 and the drain electrode 302; the T-shaped gate electrode 303 is formed on the GaN epitaxial layer 200, penetrates through the composite passivation layer, and a lateral portion of the T-shaped gate electrode 303 is located on the second passivation layer 402.

In the embodiment of the invention, the first passivation layer 401 and the second passivation layer 402 are formed below the T-shaped gate electrode 303, and the third passivation layer 403 is formed below the T-shaped gate electrode 303 and between the first passivation layer 401 and the second passivation layer 402 and the source electrode 301 and the drain electrode 302, so that the passivation effect under the gate can be improved and the parasitic capacitance of a non-gate region can be reduced through horizontal regional passivation. The regional passivation aims at simultaneously solving the problems of reducing parasitic capacitance and current collapse, can obviously improve the frequency characteristic of a device and reduce the current collapse under high frequency.

In a more preferred embodiment of the present invention, the first passivation layer 401 is a high-k material, which may be SiN or other suitable high-k material; the first passivation layer 401 is made of a high dielectric constant material, and gate reverse leakage can be reduced compared with conventional low-k global passivation. The second passivation layer 402 and the third passivation layer 403 are made of the same material, and are both low-dielectric constant materials, which may be BN or BCB, or other suitable low-dielectric constant materials. The second passivation layer 402 and the third passivation layer 403 both adopt low dielectric constant materials, so that the generated parasitic parameters are small, and the frequency characteristics of the device can be improved; in addition, since the second passivation layer 402 and the third passivation layer 403 are made of the same material, an interface problem that may occur when contacting may be avoided.

As a more preferred embodiment of the present invention, the first passivation layer 401 is grown to a thickness of 20nm to 40nm, the second passivation layer 402 is grown to a thickness of 60nm to 100nm, and the third passivation layer 403 is grown to a thickness of 80nm to 140 nm.

It should be noted that, in the GaN low-parasitic passivation device according to the embodiment of the present invention, the epitaxial layer may be an epitaxial layer of an existing GaN wafer, or may be an epitaxial layer provided in the embodiment of the present invention, and the GaN epitaxial layer 200 includes, from bottom to top, a nucleation layer 201, a buffer layer 202, a back barrier layer 203, a channel layer 204, and a barrier layer 205; the material of the back barrier layer 203 comprises AlGaN or AlN, the material of the back barrier layer 203 is AlGaN or AlN, the channel confinement property can be improved, the source-drain punch-through is inhibited, and the thickness is preferably 1-5 nm; the material of the channel layer 204 comprises InGaN, the material of the channel layer 204 is InGaN, the channel electron transmission speed can be improved, the channel quantum confinement property is improved, and the thickness is preferably 5-15 nm; the material of the barrier layer 205 includes AlGaN, and the Al composition is 20 to 30% and the thickness is preferably 12 to 25 nm.

In a second aspect, embodiments of the present invention provide a method for manufacturing a GaN low parasitic passivation device. Referring to fig. 2, fig. 2 is a flowchart of a method for manufacturing a GaN low parasitic passivation device according to an embodiment of the present invention. The preparation method provided by the embodiment of the invention comprises the following steps:

step 1, obtaining a GaN wafer;

the GaN wafer comprises a substrate layer 100 and a GaN epitaxial layer 200 on the substrate layer 100;

step 2, etching the GaN epitaxial layer 200 to a specified position to realize active region isolation;

step 3, photoetching source electrode 301 and drain electrode 302 graphs at two ends of the upper surface of the GaN epitaxial layer 200, and evaporating ohmic contact metal in the source electrode 301 and drain electrode 302 graph areas to form a source electrode 301 and a drain electrode 302;

step 4, forming a first passivation layer 401 on the GaN epitaxial layer 200;

step 5, forming a second passivation layer 402 on the first passivation layer 401 to form a composite passivation layer with the first passivation layer 401;

step 6, etching a gate groove penetrating through the composite passivation layer in the middle area of the source electrode 301 and the drain electrode 302, and etching away a composite passivation layer second passivation layer 402 on the source electrode 301 and the drain electrode 302, wherein the source electrode 301 and the drain electrode 302 are the second passivation layer 402;

step 7, etching a gate region on the second passivation layer 402, and depositing a gate metal on the gate region to form a T-shaped gate electrode 303;

step 8, etching off the composite passivation layer between the source gates and between the gate drains by using the T-shaped gates as hard masks;

step 9, forming a third passivation layer 403 on the source electrode 301 and the T-shaped gate electrode 303, between the drain electrode 302 and the T-shaped gate electrode 303, and on the source electrode 301 and the drain electrode 302;

step 10, opening and etching the third passivation layer 403 above the source electrode 301, the gate electrode and the drain electrode 302 region, and depositing an interconnection metal 304 to complete the device preparation.

Illustratively, the step 1 includes:

step 1.1, epitaxially growing a nucleation layer 201, a buffer layer 202, a back barrier layer 203, a channel layer 204 and a barrier layer 205 on a substrate layer 100 from bottom to top in sequence to form a GaN wafer; the material of the back barrier layer 203 comprises AlGaN or AlN; the material of the channel layer 204 includes InGaN; the barrier layer 205 comprises AlGaN, and the Al component is 20-30%;

and 1.2, cleaning the surface of the GaN wafer to remove organic and inorganic stains and surface oxides in the growth process of the GaN wafer material.

Illustratively, the step 4 includes:

step 4.1, cleaning the surface of the sample of which the source-drain ohmic contact is completed in the step 3;

step 4.2, a SiN passivation layer with a thickness of 20nm, i.e. a first passivation layer 401, is grown on the barrier layer 205 by using a plasma enhanced chemical vapor deposition process.

Illustratively, the step 5 includes:

step 5.1, growing a BN film on the copper foil;

step 5.2, a PMMA anisole solution is spin-coated on the BN film to form a PMMA/BN/copper structure;

step 5.3, removing copper in the PMMA/BN/copper structure by adopting a chemical method to obtain a transparent film with the PMMA/BN structure;

step 5.4, cleaning the transparent film with the PMMA/BN structure, and transferring the transparent film to the surface of the first passivation layer 401 for surface mounting;

step 5.5, heating the device comprising the transparent film with the PMMA/BN structure;

and 5.6, cleaning the heated device comprising the transparent film with the PMMA/BN structure, and removing the PMMA glue to obtain a BN film, namely a second passivation layer 402.

Likewise, the third passivation layer 403 may also be formed by the same method as the second passivation layer 402, where BN is deposited by means of a transfer, which method is of higher quality compared to growth directly on the semiconductor.

According to the preparation method of the GaN low-parasitic passivation device, the technical scheme of regional passivation between the source and the drain is realized in a mode that the gate metal is used as the hard mask, the preparation process is simple, and the introduction of an additional photoetching step is avoided; and dry etching is adopted as anisotropy, so that the passivation layer under the gate is prevented from being over-etched. Compared with the technical scheme of realizing the regional passivation between the source and the drain by adopting the mode of taking the gate metal as the hard mask, if the SiO is adopted₂Hard mask lithography to achieve zonal passivation adds additional process steps, and SiO₂The hard mask needs to be removed by wet etching, and due to the isotropy of the wet etching, over-etching of an effective passivation layer is easily caused, and the device characteristics are deteriorated.

In addition, according to the preparation method of the GaN low-parasitic passivation device, the T-shaped gate electrode 303 is used as a hard mask, the first passivation layer 401 and the second passivation layer 402 are formed below the T-shaped gate electrode 303, the third passivation layer 403 is formed below the T-shaped gate electrode 303 and between the first passivation layer 401 and the second passivation layer 402 and the source electrode 301 and the drain electrode 302, and through transverse partition passivation, the under-gate passivation effect can be improved, and the parasitic capacitance of a non-gate region can also be reduced. The regional passivation aims at simultaneously solving the problems of reducing parasitic capacitance and current collapse, can obviously improve the frequency characteristic of a device and reduce the current collapse under high frequency.

Based on the same inventive concept as the first aspect, the first passivation layer 401 is a high-k material, which may be SiN or other suitable high-k material; the first passivation layer 401 is made of a high dielectric constant material, and gate reverse leakage can be reduced compared with conventional low-k global passivation. The second passivation layer 402 and the third passivation layer 403 are made of the same material, and are both low-dielectric constant materials, which may be BN or BCB, or other suitable low-dielectric constant materials. The second passivation layer 402 and the third passivation layer 403 both adopt low dielectric constant materials, so that the generated parasitic parameters are small, and the frequency characteristics of the device can be improved; in addition, since the second passivation layer 402 and the third passivation layer 403 are made of the same material, an interface problem that may occur when contacting may be avoided.

Preferably, the first passivation layer 401 is grown to a thickness of 20nm to 40nm, the second passivation layer 402 is grown to a thickness of 60nm to 100nm, and the third passivation layer 403 is grown to a thickness of 80nm to 140 nm.

The following describes a method for fabricating a GaN low parasitic passivation device according to the present invention with a specific example. In this embodiment, the GaN wafer is not present, but is obtained by growing an epitaxial layer on a substrate material.

Step 1, epitaxially growing a heterojunction material on a substrate layer 100 to obtain a GaN wafer; the GaN wafer surface is cleaned to remove organic and inorganic contaminants and surface oxides introduced during material storage as shown in fig. 3 a.

As an example, the step may specifically include:

step 1.1, epitaxially growing a nucleation layer 201, a buffer layer 202, a back barrier layer 203, a channel layer 204 and a barrier layer 205 on a substrate layer 100 from bottom to top in sequence to form a GaN wafer; the material of the back barrier layer 203 comprises AlGaN or AlN; the material of the channel layer 204 includes InGaN; the material of the barrier layer 205 includes AlGaN, and the Al composition is 20 to 30%.

The back barrier layer 203 is made of AlGaN or AlN, so that the confinement property of a channel can be improved, source-drain punch-through is inhibited, and the thickness is preferably 1-5 nm. The material of the channel layer 204 is InGaN, which can improve the channel electron transmission speed and improve the channel quantum confinement, and the thickness is preferably 5-15 nm. The thickness of the barrier layer 205 is preferably 12-25 nm.

And 1.2, cleaning the surface of the GaN wafer to remove organic and inorganic stains and surface oxides in the growth process of the GaN wafer material.

The cleaning step may specifically include:

firstly, the wafer is placed in acetone for 2 minutes of ultrasonic treatment, then the wafer is boiled in positive photoresist stripping liquid heated in water bath at the temperature of 60 ℃ for 10 minutes, then the sample is sequentially placed in acetone and ethanol for 3 minutes of ultrasonic treatment, and after the residual acetone and ethanol are washed away by deionized water, HF (HF: H) is used₂O is 1: 5) and cleaning the wafer for 30s, finally cleaning the wafer with deionized water, and drying the wafer with ultra-pure nitrogen.

And 2, etching the mesa to the channel layer 204 by adopting an ICP (inductively coupled plasma) device to realize active region isolation, as shown in FIG. 3 b.

As an example, the step may specifically include:

step 2.1, photo-etching electrically isolated regions on the barrier layer 205:

firstly, placing a sample wafer on which a barrier layer 205 grows on a hot plate of 200 and baking for 5 min;

then, throwing photoresist to the sample wafer at the rotation speed of 3500rpm, and drying the sample wafer on a hot plate at the temperature of 90 ℃ for 1min after the photoresist throwing is finished;

then, the sample wafer is put into a photoetching machine to expose the photoresist in the electric isolation area;

finally, the sample wafer after exposure is placed into a developing solution to remove the photoresist in the electric isolation area, and the sample wafer is washed by ultrapure water and dried by nitrogen;

step 2.2, etching an electrically isolated region on the barrier layer 205:

for the sample wafer after the photoetching, the barrier layer 205 and the channel layer 204 are etched by an ICP (inductively coupled plasma) process in a dry method, so that the mesa isolation of an active region is realized, and gas Cl adopted in the etching is used₂/BCl₃The pressure is 5mTorr, the power of an upper electrode is 100W, the power of a lower electrode is 10W, and the etching time is 40 s;

step 2.3, removing the etched mask:

and sequentially putting the sample wafer subjected to active area isolation into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electric isolation area, cleaning with deionized water and drying with nitrogen.

And 3, coating photoresist on the barrier layer 205, photoetching patterns of the source electrode 301 and the drain electrode 302, and evaporating ohmic contact metal in the pattern areas of the source electrode 301 and the drain electrode 302 by adopting an electron beam evaporation process, as shown in fig. 3 c.

For example, the step may specifically include:

step 3.1, source electrode 301 area and drain electrode 302 area are etched on barrier layer 205:

firstly, placing a sample wafer subjected to mesa etching on a hot plate of 200 and baking for 5 min;

then, throwing the stripping glue on the sample wafer, wherein the thickness of the throwing glue is 0.35 mu m, and drying the sample wafer on a hot plate at the temperature of 200 ℃ for 5 min;

then, throwing photoresist on the sample wafer, wherein the thickness of the photoresist is 0.77 mu m, and drying the sample wafer on a hot plate at 90 ℃ for 1 min;

then, the sample wafer is put into a photoetching machine to expose the photoresist in the source electrode 301 area and the drain electrode 302 area;

finally, the exposed sample wafer is put into a developing solution to remove the photoresist and the stripping glue in the source electrode 301 area and the drain electrode 302 area, and the photoresist and the stripping glue are washed by ultra-pure water and dried by nitrogen.

Step 3.2, priming the membrane:

and removing the undeveloped photoresist thin layer in the pattern area of the sample wafer subjected to the photoetching in the source electrode 301 area and the drain electrode 302 area by using a plasma photoresist remover, wherein the processing time is 5min, and the stripping yield is greatly improved by the step.

Step 3.3, evaporating the drain electrode 302 metal:

putting the sample subjected to plasma photoresist removal into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10^-6After Torr, the plasma is again emitted to the source electrode 301 regionAnd evaporating ohmic metal on the barrier layer 205 in the region of the domain and the drain electrode 302 and on the photoresist outside the region of the source electrode 301 and the drain electrode 302, wherein the ohmic metal is a metal stack structure sequentially consisting of four layers of metals of Ti, Al, Ni and Au from bottom to top.

Step 3.4, stripping metal and annealing:

firstly, soaking a sample wafer subjected to source-drain metal evaporation in acetone for more than 40 minutes and then carrying out ultrasonic treatment;

then, putting the sample wafer into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min;

then, putting the sample wafer into an acetone solution and an ethanol solution in sequence, and ultrasonically cleaning for 3 min;

the coupons were then rinsed with ultra pure water and blown dry with nitrogen.

And finally, putting the sample wafer into a rapid annealing furnace, introducing nitrogen into the annealing furnace for 10min, setting the temperature of the annealing furnace at 830 ℃ in the nitrogen atmosphere, and performing high-temperature annealing for 30s to ensure that the ohmic metal on the source electrode 301 and the drain electrode 302 region sinks to the GaN channel layer 204, so that ohmic contact between the ohmic metal and the heterojunction channel is formed, and the source electrode 301 and the drain electrode 302 are formed.

Step 4, depositing a SiN film on the barrier layer 205 and the source/drain electrode 302 by using Plasma Enhanced Chemical Vapor Deposition (PECVD) to form a SiN passivation layer, i.e., a first passivation layer 401, as shown in fig. 3 d.

For example, the step may specifically include:

step 4.1, surface cleaning is carried out on the sample which is subjected to source-drain ohmic contact:

firstly, putting a sample into an acetone solution for ultrasonic cleaning for 3mim, wherein the ultrasonic intensity is 3.0;

then, putting the sample into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min;

then, the sample is sequentially placed into an acetone solution and an ethanol solution for ultrasonic cleaning for 3min, and the ultrasonic intensity is 3.0;

finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.

Step 4.2, growing a SiN passivation layer with the thickness of 20nm on the barrier layer 205 and the source and drain electrodes 302 by using a plasma enhanced chemical vapor deposition PECVD process:

the growth process conditions are as follows: by NH₃And SiH₄The optimized flow ratio is SiH as Si source and N source₄：NH₃2: 1, deposition temperature is 250 deg.C, reaction chamber pressure is 600mTorr, and RF power is 22W. The reaction time was 2 min.

It should be noted that the first passivation layer is deposited by a full-scale deposition method, and a certain thickness of the sidewall of the source electrode and the drain electrode is also deposited during the deposition, but is not shown in the figure for convenience of drawing. The same applies to the subsequent second and third passivation layers.

And step 5, growing a BN film on the copper foil, and transferring the BN film to the surface of the SiN by using a material transfer technology to generate a composite passivation layer, as shown in FIG. 3 e.

For example, the step may specifically include:

step 5.1, growing a BN film on the copper foil:

synthesizing BN film by LPCVD method.

First, the precursor borane ammonia (NH)₃-BH₃) Placing the copper foil in a glass tube, and placing the copper foil in a quartz tube in a tube furnace;

then opening a mechanical pump and a valve, and heating the tube furnace from room temperature to 1000 ℃ (the heating rate is 50 ℃/min);

then heating the water bath to a certain temperature and opening the valve;

finally, after the valve is opened, the valve is opened by H₂Loaded into a quartz tube, H₂The flow rate was 0.05L/min, and a BN film was deposited on the copper substrate. The growth thickness was 100 nm.

Step 5.2, spin coating PMMA (679.03):

placing the copper foil with the BN film growing on the surface on a spin coating machine, rotating at the rotating speed of 1000r/min for 40s, and spin-coating a PMMA anisole solution on the surface of the copper foil to form a PMMA/BN/copper structure;

step 5.3, removing the copper foil:

drying the copper foil coated with PMMA at 170 ℃ for 3min,put into FeCl₃In solution (FeCl)₃1mol/L, 10% HCl) is kept stand for 2 hours to remove copper, and a transparent film with a PMMA/BN structure is obtained;

step 5.4, rinsing and surface mounting:

repeatedly rinsing the PMMA/BN transparent film without the copper foil by using deionized water, transferring the PMMA/BN transparent film to the surface of SiN for surface mounting to form a composite passivation layer;

step 5.5, heating by a hot plate:

the device comprising the transparent film of PMMA/BN structure is placed on a hot plate and heated: heating at 80 deg.C for 2min, heating to 120 deg.C for 2min, and heating to 160 deg.C for 4 min;

step 5.6, cleaning the SiN/BN film:

and (3) putting the device containing the PMMA/BN structure transparent film into an acetone solution, cleaning for 10min at 45 ℃, finally cleaning with isopropanol, and removing PMMA glue to obtain the BN film transferred to the SiN surface, namely the second passivation layer 402.

Step 6, a gate trench and an ohmic metal opening region are etched on the second passivation layer 402 and etched using ICP, as shown in fig. 3 f.

By way of example, this step may include:

step 6.1, etching a gate groove and an ohmic metal opening area on the composite passivation layer:

firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min;

then, coating and spin coating the photoresist at a spin coating speed of 3500r/mim, and baking the sample on a hot plate at 90 deg.C for 1 min;

then, putting the sample into a photoetching machine to expose the photoresist in the thinning area;

finally, the sample after completing the exposure is put into a developing solution to remove the photoresist in the thinning area, and is subjected to ultra-pure water rinsing and nitrogen blow drying.

Step 6.2, thinning the composite passivation layer by utilizing an Inductively Coupled Plasma (ICP) etching process:

the etching conditions are as follows: the reaction gas being CF₄And O₂，CF₄Flow rate25sccm，O₂The flow is 5sccm, the pressure of the reaction chamber is 5mTorr, the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, and the etching depth is 120 nm.

And 7, photoetching a grid electrode area, and depositing grid metal by electron beam evaporation to finish the preparation of the T-shaped grid, as shown in fig. 3 g.

By way of example, this step may include:

step 7.1, a gate electrode area is etched on the composite passivation layer:

firstly, placing a sample wafer subjected to groove etching on a hot plate of 200 and baking for 5 min;

then, throwing the stripping glue on the sample wafer, wherein the thickness of the throwing glue is 0.35 mu m, and drying the sample wafer on a hot plate at the temperature of 200 ℃ for 5 min;

then, throwing photoresist on the sample wafer, wherein the thickness of the photoresist is 0.77 mu m, and drying the sample wafer on a 90 hot plate for 1 min;

then, the sample wafer is put into a photoetching machine to expose the photoresist in the gate electrode area;

finally, putting the exposed sample wafer into a developing solution to remove the photoresist and the stripping glue in the gate electrode area, and carrying out ultra-pure water washing and nitrogen blow-drying on the sample wafer;

step 7.2, priming the membrane:

removing the undeveloped photoresist thin layer in the pattern area of the sample wafer subjected to the gate electrode photoetching for 5min by using a plasma photoresist remover;

step 7.3, evaporating the gate electrode metal:

putting the sample with the grooved grid opened into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10^-6After the Torr is carried out, evaporating gate metal on the photoresist outside the groove gate region and the gate electrode region, wherein the gate metal is a metal stack structure which is formed by two layers of metal of Ni 45nm and Au 400nm from bottom to top in sequence;

step 7.4, stripping metal:

soaking the sample wafer subjected to gate electrode evaporation in acetone for more than 40 minutes and then carrying out ultrasonic treatment; then putting the sample wafer into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min; then, putting the sample wafer into an acetone solution and an ethanol solution in sequence, and ultrasonically cleaning for 3 min; and finally, washing the sample wafer by using ultrapure water and drying the sample wafer by using nitrogen to finish the manufacture of the grid electrode.

And 8, etching the passivation layer between the source gates and between the gate drains by using the T-shaped gates as a hard mask, as shown in FIG. 3 h.

The composite passivation layer between source gates and between gate drains is etched to the barrier layer 205 using an inductively coupled plasma ICP etch process.

Illustratively, the etching conditions are: the reaction gas being CF₄And O₂，CF₄The flow rate is 25sccm, the O2 flow rate is 5sccm, the pressure of the reaction chamber is 5mTorr, the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, and the etching depth is 120 nm.

Step 9, forming third passivation layers 403 on the source electrode 301, the T-shaped gate electrode 303, the drain electrode 302, the T-shaped gate electrode 303, and the source electrode 301 and the drain electrode 302, so as to complete filling of the passivation layers between the source gates and between the gate drains, and reduce parasitic parameters of the device, as shown in fig. 3 i.

The third passivation layer 403 is preferably made of BN, the growth process conditions are the same as those in step 5, and the growth thickness of the BN passivation layer with the growth thickness is 120 nm.

Step 10, opening and etching the third passivation layer 403 above the gate, source and drain electrode 302 regions, and completing the deposition of the interconnection metal 304 by electron beam evaporation, thereby completing the device fabrication, as shown in fig. 3 j.

By way of example, this step may include:

step 10.1, lithographically interconnect regions on the sample:

firstly, placing a sample wafer on a hot plate at 200 ℃ for baking for 5 min;

then, throwing the stripping glue on the sample wafer, wherein the thickness of the throwing glue is 0.35 mu m, and drying the sample wafer on a hot plate at the temperature of 200 ℃ for 5 min;

then, throwing photoresist on the sample wafer, wherein the thickness of the photoresist is 0.77 mu m, and drying the sample wafer on a hot plate at 90 ℃ for 1 min;

then, the sample wafer is put into a photoetching machine to expose the photoresist in the interconnected electrode area;

finally, putting the exposed sample wafer into a developing solution to remove the photoresist and the stripping glue in the interconnected electrode area, and carrying out ultra-pure water washing and nitrogen blow-drying on the sample wafer;

step 10.2, opening and etching the third passivation layer 403BN by utilizing an Inductively Coupled Plasma (ICP) etching process:

the etching conditions are as follows: the reaction gas being CF₄And O₂，CF₄Flow rate of 25sccm, O₂The flow is 5sccm, the pressure of the reaction chamber is 5mTorr, the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, and the etching depth is 120 nm.

Step 10.3, priming the membrane:

removing a photoresist thin layer which is not developed and cleaned in a pattern area of a sample wafer subjected to the interconnection electrode photoetching for 5min by using a plasma photoresist remover;

and step 10.4, depositing a metal Ti 20nm/Au 200nm layer on the sample by adopting an electron beam evaporation process, and removing the photoresist to finish the manufacture of the device.

Step 10.5, stripping metal:

soaking the sample wafer subjected to the evaporation of the interconnected electrodes in acetone for more than 40 minutes and then carrying out ultrasonic treatment; then putting the sample wafer into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min; then, putting the sample wafer into an acetone solution and an ethanol solution in sequence, and ultrasonically cleaning for 3 min; and finally, washing the sample wafer with ultrapure water and drying the sample wafer with nitrogen to finish the manufacture of the device.

According to the GaN low-parasitic passivation device and the preparation method thereof provided by the embodiment of the invention, the T-shaped gate electrode is used as a hard mask, the first passivation layer and the second passivation layer are formed below the T-shaped gate electrode, the third passivation layer is formed below the T-shaped gate electrode and between the first passivation layer and the second passivation layer as well as the source electrode and the drain electrode, and through transverse regional passivation, the passivation effect under the gate can be improved, and the parasitic capacitance of a non-gate region can also be reduced; the regional passivation aims at simultaneously solving the problems of reducing parasitic capacitance and current collapse, can obviously improve the frequency characteristic of a device and reduce the current collapse under high frequency. Meanwhile, the technical scheme of regional passivation between the source and the drain is realized by using the gate metal as a hard mask, the preparation process is simple, and the introduction of an additional photoetching step is avoided; and dry etching is adopted as anisotropy, so that the passivation layer under the gate is prevented from being over-etched transversely. In addition, as a further effect, the first passivation layer is made of a high-dielectric-constant material, so that the reverse leakage of the grid electrode can be reduced; the second passivation layer and the third passivation layer are made of low-dielectric-constant materials, so that the generated parasitic parameters are small, and the frequency characteristics of the device can be improved.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.