阅读说明：本技术 一种数字功率发射芯片的阻抗调制系统及方法 (Impedance modulation system and method of digital power transmitting chip ) 是由 陈茵 游飞 马明明 吴雯祺 陈雪蕾 何倩 秦荣兴 王瑜 于 2021-08-31 设计创作，主要内容包括：本发明提供一种数字功率发射芯片的阻抗调制系统及方法,属于无线通信技术领域。该系统分别通过调整多级驱动的功率分配网络和可重构输出匹配网络,实现芯片中数字功放阵列的输入、输出阻抗,与前级输出阻抗、负载阻抗之间的良好匹配,同时通过功率控制信号控制数字功率放大器的状态,使得发射芯片热管理更为有效,大大提升芯片的热可靠性。(The invention provides an impedance modulation system and method of a digital power transmitting chip, and belongs to the technical field of wireless communication. The system realizes the good matching between the input impedance and the output impedance of the digital power amplifier array in the chip and the output impedance and the load impedance of the preceding stage by adjusting the power distribution network and the reconfigurable output matching network of the multilevel drive respectively, and controls the state of the digital power amplifier through the power control signal, so that the heat management of the transmitting chip is more effective, and the thermal reliability of the chip is greatly improved.)

1. An impedance modulation system of a digital power transmitting chip is characterized by comprising a driving power distribution network, a digital power amplifier array, a reconfigurable output matching network and a digital control module;

the driving power distribution network is formed by cascading n stages of driving power distribution subunits, each stage of driving power distribution subunit comprises a power distribution module and a plurality of driving power amplifiers connected with the power distribution module, the input of the nth stage of power distribution module is connected with the output of the (n-1) th stage of driving power amplifier, and the output of the nth stage of driving power amplifier is connected with the input of the high-uniform-weight digital power amplifier array in the digital power amplifier array;

the digital power amplifier array comprises a high-uniform-weight digital power amplifier array and a low-non-uniform-weight digital power amplifier array; the high-uniform-weight digital power amplifier array consists of m digital power amplifier sub-arrays, and each digital power amplifier sub-array comprises the same number of digital power amplifiers; the low non-uniform weight digital power amplifier array comprises a plurality of digital power amplifiers and coupling units;

the reconfigurable output matching network is used for matching the output impedance of the digital power amplifier array with the load impedance of the digital transmitting chip and performing power synthesis on the output of the digital power amplifier array, and comprises an output pre-matching unit, a power synthesis unit and a variable parameter element matching unit which are connected in sequence; the output pre-matching unit is used for pre-matching the output impedance of the digital power amplifier array, the power synthesis unit is used for performing power synthesis on the output of each digital power amplifier array, and the variable parameter element matching unit is used for modulating the load impedance of the digital transmitting chip;

the digital control module is used for quantizing and coding the baseband signal to obtain a power coding signal so as to realize the control of the driving power distribution network, the digital power amplifier array and the reconfigurable output matching network, namely the digital control module quantizes and codes the baseband signal to obtain the power coding signal and transcodes the power coding signal into power control signals A-A ', a static voltage control signal B, B' and a variable parameter control signal C; the power control signals A-A 'are used for controlling the working state of a driving power amplifier in a driving power distribution network, the static voltage control signal B, B' respectively provides effective bias for a high-uniform-weight digital power amplifier and a low-non-uniform-weight digital power amplifier in a digital power amplifier array, and the variable parameter control signal C controls a variable parameter element matching unit in a reconfigurable output matching network;

the phase modulation signals are respectively input into a power distribution module of a first-stage driving power distribution subunit in a driving power distribution network and a low non-uniform weight digital power amplifier array of the digital power amplifier array; the power distribution module in the driving power distribution network is used for performing equal power distribution on an input phase modulation signal, then driving the power amplifier to amplify the power of the signal, and finally outputting the signal to the high-uniform-weight digital power amplifier array, and meanwhile, the driving power distribution network is used for modulating the input impedance of the high-uniform-weight digital power amplifier array; the high uniform weight digital power amplifier array is used for carrying out amplitude modulation on the phase modulation signal under the control of the power control signal to obtain an amplitude-phase modulation signal containing high-order amplitude information of the power control signal, then outputting the amplitude-phase modulation signal to a pre-matching unit of the reconfigurable output matching network, and inputting the amplitude-phase modulation signal to the power synthesis unit after impedance matching; the low non-uniform weight digital power amplifier array is used for carrying out amplitude modulation on the phase modulation signal under the control of the power control signal to obtain an amplitude-phase modulation signal containing low-order amplitude information of the power control signal, and inputting the amplitude-phase modulation signal to the power synthesis unit; the power synthesis unit inputs the synthesized power signal to the variable parameter element matching unit and then sends the power signal to a load or an antenna of a transmitting chip.

2. The impedance modulation system according to claim 1, wherein the number of paths of the driving power amplifiers connected to the power distribution block in the other stage driving power distribution subunit except the first stage driving power distribution subunit is the same or different.

3. The impedance modulation system according to claim 1, wherein the total number of the final driving power amplifiers is equal to the number of all the digital power amplifiers with high uniform weight in the digital power amplifier array, the number of the final driving power distribution subunit is equal to the number of the digital power amplifier subarrays in the digital power amplifier with high uniform weight, and the number of the driving power amplifiers included in each of the final driving power distribution subunits is equal to the number of the digital power amplifiers in a single digital power amplifier subarray.

4. The impedance modulation system of claim 1, wherein the power distribution module, in addition to performing several paths of equal power distribution on the input signal, can also realize that the input impedance of the power distribution module is limited to be kept stable under the condition that the on-off state of a rear-connected driving power amplifier is changed; the driving power amplifier is used for providing proper input power for the power distribution module or the digital power amplifier array of the next stage, and the working state of the driving power amplifier is controlled by the digital control module.

5. The impedance modulation system according to claim 1, wherein the layout of the m digital power amplifier sub-arrays in the high uniform weight digital power amplifier array is symmetrical on the layout, so as to avoid the phenomena of chip performance deterioration and reliability reduction caused by local overheating of the chip.

6. A method for modulating the impedance of a digital power transmitting chip is characterized by comprising the following steps:

the digital control module carries out quantization coding on the baseband signal to obtain a power coding signal, and then the signal is transcoded into a power control signal A-A ', a static voltage control signal B, B' and a variable parameter control signal C; the power control signals A-A 'are used for controlling the working state of a driving power amplifier in a driving power distribution network, the static voltage control signal B, B' respectively provides effective bias for a high-uniform-weight digital power amplifier and a low-non-uniform-weight digital power amplifier in a digital power amplifier array, and the variable parameter control signal C controls a variable parameter element matching unit in a reconfigurable output matching network;

the power control signals A-A' control the driving power distribution network to realize the matching of the input impedance, and the specific process is as follows: the on and off of each stage of driving power distribution subunit are respectively controlled by power control signals A-A ', and each driving power amplifier corresponds to one bit of the power control signals A-A'; the on-off of each digital power amplifier in the high-uniform-weight digital power amplifier array is consistent with the on-off condition of a driving power amplifier in a final-stage driving power distribution subunit connected with the digital power amplifier array;

the number of bits of the static voltage control signal B is equal to the number of the digital power amplifiers with high uniform weight, and one bit corresponds to one digital power amplifier; if the digital power amplifier is in an open state, the static voltage control signal B provides effective bias for the digital power amplifier, and simultaneously controls the corresponding drive amplifier of the front stage of the digital power amplifier to be open; if the digital power amplifier is in a turn-off state, the static voltage control signal B is set to an invalid level which cannot provide bias for the digital power amplifier, and meanwhile, the corresponding drive amplifier of the front stage of the digital power amplifier is controlled to be turned off; the control rule of the static voltage control signal B is the same as that of the static voltage control signal B, and each bit of the static voltage control signal B' provides effective bias for a digital power amplifier with low non-uniform weight;

the variable parameter control signal C adjusts the variable parameter element matching unit, changes the load impedance transformation value of the unit to the transmitting chip, further changes the input impedance of the variable parameter element matching unit, and realizes the fine adjustment of the output matching impedance modulation; the output pre-matching unit and the variable parameter element matching unit jointly realize the function of matching the output impedance of the digital power amplifier array.

7. The method for impedance modulation of a digital power transmitting chip as claimed in claim 6, wherein the digital control module transcodes the H-bit power encoded signal into the static voltage control signal B, B' in a moving temperature encoding manner; the high h bit of the power coding signal is transcoded into a static voltage control signal B, and the static voltage control signal B is used for controlling the digital power amplifiers with high uniform weight in an open state to be uniformly distributed in each digital power amplifier subarray; the rest low H-H bits of the power coding signal do not need transcoding, namely are equal to a static voltage control signal B', and are directly used for controlling the digital power amplifier with low non-uniform weight; the mobile temperature coding is changed to 1 every n-1 bits, wherein n is the number of high-uniform-weight digital power amplifiers contained in a single digital power amplifier subarray.

8. The method of digital power transmitting chip impedance modulation according to claim 6, wherein the power control signals a-a "need to control N stages of driving power amplifiers; and taking the OR of the control code words of all the driving power amplifiers in the k-1 stage in the following k stage.

9. The method according to claim 6, wherein the power control signals A-A "control the digital power amplifiers in the on-state to be uniformly distributed in each digital power amplifier sub-array, so that the loads carried by each final-stage driving power distribution sub-unit are kept equal, and the digital power amplifiers in the on-state are uniformly distributed around the chip layout.

10. The method of digital power transmitting chip impedance modulation of claim 6 wherein the variable parameter control signal C controls the impedance transformation value of the network to the chip load by controlling the variable parameters of the elements in the variable parameter element matching unit.

Technical Field

The invention belongs to the technical field of wireless communication, and particularly relates to an impedance modulation system of a direct power output digital transmitting chip and a modulation method thereof.

Background

In order to meet the requirements of wireless communication, space internet, cognitive radio and the like, broadband, multi-band and multiple modes coexist simultaneously, the realization of reconfigurable and high efficiency of an integrated chip becomes the necessary requirement of a microwave transmitter, and the digitization of a microwave power amplifier is an effective technical way for realizing the requirements. The digital POWER amplifier combines POWER coding signal processing to realize full digital microwave POWER amplification (POWER DAC) on the basis of a microwave switch POWER amplifier.

In a Digital Power transmitting chip, a Digital Power amplifier (DPA or Digital Power amplifier for short) array is used to replace a Digital-to-analog converter, a mixer unit and a Power amplifier in a traditional transmitter, so as to realize up-conversion and Power amplification of a baseband signal directly to a radio frequency signal. With the continuous introduction of high-order modulation and multiplexing modulation technology in communication systems, the requirements for the dynamic range and the output accuracy of a transmitter are higher and higher. Digital power amplifiers as an emerging digital transmitter solution, digital power amplifier arrays comprising a large number of power amplifier cells are developed to meet the demand. However, under the excitation of a signal with a large dynamic range, the equivalent input impedance and the equivalent output impedance of the digital power amplifier array change greatly, so that the impedance mismatch phenomenon is easily generated, and the efficiency of the digital transmitter is further influenced.

The conventional digital transmitting chip has little concern about the problems mentioned above, and the digital power amplifier array is directly connected with the front stage and the rear stage, or the matching network is generally fixed and is not adjustable during design. For example, in the study of A.Balteau et al, "A2-Bit, 24dBm, Millimer-Wave SOI CMOS Power-DAC Cell for Watt-Level high-Efficiency, full Digital m-ary QAM Transmitters," in IEEE Journal of Solid-State circuits, vol.48, No.5, pp.1126-1137, May 2013, doi:10.1109/JSSC.2013.2252752 ", etc., the differential Power amplifier is directly connected to the differential patch antenna.

Therefore, the impedance modulation is carried out on the input impedance and the output impedance of the digital power amplifier array, the problem of impedance mismatch in the digital transmitter under the excitation of signals with a large dynamic range is solved, and the method is very important for further improving the performance of the digital transmitter.

Disclosure of Invention

In view of the problems in the background art, an object of the present invention is to provide an impedance modulation system of a digital power transmitting chip and a modulation method thereof. The system realizes the good matching between the input impedance and the output impedance of the digital power amplifier array in the chip and the output impedance and the load impedance of the preceding stage by adjusting the power distribution network and the reconfigurable output matching network of the multilevel drive respectively, and controls the state of the digital power amplifier through the power control signal, so that the heat management of the transmitting chip is more effective, and the thermal reliability of the chip is greatly improved.

In order to achieve the purpose, the technical scheme of the invention is as follows:

an impedance modulation system of a digital power transmitting chip comprises a driving power distribution network, a digital power amplifier array, a reconfigurable output matching network and a digital control module;

the driving power distribution network is formed by cascading n stages of driving power distribution subunits, each stage of driving power distribution subunit comprises a power distribution module and a plurality of driving power amplifiers connected with the power distribution module, the input of the nth stage of power distribution module is connected with the output of the (n-1) th stage of driving power amplifier, and the output of the nth stage of driving power amplifier is connected with the input of a high-uniform-weight (namely, Most Significant Bit, MSB) digital power amplifier array in the digital power amplifier array;

the digital power amplifier array comprises a high-uniform-weight digital power amplifier array and a low-non-uniform-weight (namely, a Least-Significant-match Bi t, LSB) digital power amplifier array; the high-uniform-weight digital power amplifier array consists of m digital power amplifier sub-arrays, and each digital power amplifier sub-array comprises the same number of digital power amplifiers; the low non-uniform weight digital power amplifier array comprises a plurality of digital power amplifiers and coupling units;

the reconfigurable output matching network is used for matching the output impedance of the digital power amplifier array with the load impedance of the digital transmitting chip and performing power synthesis on the output of the digital power amplifier array, and comprises an output pre-matching unit, a power synthesis unit and a variable parameter element matching unit which are connected in sequence; the output pre-matching unit is used for pre-matching the output impedance of the digital power amplifier array, the power synthesis unit is used for performing power synthesis on the output of each digital power amplifier array, and the variable parameter element matching unit is used for modulating the load impedance of the digital transmitting chip;

the digital control module is used for quantizing and coding the baseband signal to obtain a power coding signal so as to realize the control of the driving power distribution network, the digital power amplifier array and the reconfigurable output matching network, namely the digital control module quantizes and codes the baseband signal to obtain the power coding signal and transcodes the power coding signal into power control signals A-A ', a static voltage control signal B, B' and a variable parameter control signal C; the power control signals A-A 'are used for controlling the working state of a driving power amplifier in a driving power distribution network, the static voltage control signal B, B' respectively provides effective bias for a high-uniform-weight digital power amplifier and a low-non-uniform-weight digital power amplifier in a digital power amplifier array, and the variable parameter control signal C controls a variable parameter element matching unit in a reconfigurable output matching network;

the phase modulation signals are respectively input into a power distribution module of a first-stage driving power distribution subunit in a driving power distribution network and a low non-uniform weight digital power amplifier array of the digital power amplifier array; the power distribution module in the driving power distribution network is used for performing equal power distribution on an input phase modulation signal, then driving the power amplifier to amplify the power of the signal, and finally outputting the signal to the high-uniform-weight digital power amplifier array, and meanwhile, the driving power distribution network is used for modulating the input impedance of the high-uniform-weight digital power amplifier array; the high uniform weight digital power amplifier array is used for carrying out amplitude modulation on the phase modulation signal under the control of the power control signal to obtain an amplitude-phase modulation signal containing high-order amplitude information of the power control signal, then outputting the amplitude-phase modulation signal to a pre-matching unit of the reconfigurable output matching network, and inputting the amplitude-phase modulation signal to the power synthesis unit after impedance matching; the low non-uniform weight digital power amplifier array is used for carrying out amplitude modulation on the phase modulation signal under the control of the power control signal to obtain an amplitude-phase modulation signal containing low-order amplitude information of the power control signal, and inputting the amplitude-phase modulation signal to the power synthesis unit; the power synthesis unit inputs the synthesized power signal to the variable parameter element matching unit and then sends the power signal to a load or an antenna of a transmitting chip.

Further, in the other stages of driving power distribution subunits except the first stage of driving power distribution subunit, the number of the driving power amplifiers connected with the power distribution module may be the same or different.

Furthermore, the total number of the final-stage driving power amplifiers is equal to the number of all high-uniform-weight digital power amplifiers in the digital power amplifier array, the number of the final-stage driving power distribution subunit is equal to the number of high-uniform-weight digital power amplifier subarrays, and the number of the driving power amplifiers contained in each final-stage driving power distribution subunit is equal to the number of the digital power amplifiers in a single high-uniform-weight digital power amplifier subarray.

Furthermore, the power distribution module can distribute a plurality of paths of equal power to the input signal, and can also keep the input impedance of the power distribution module stable under the condition that the on-off state of a rear-connected driving power amplifier is changed; the driving power amplifier is used for providing proper input power for the power distribution module or the digital power amplifier array of the next stage, and the working state of the driving power amplifier is controlled by the digital control module.

Furthermore, the layout of the m digital power amplifier sub-arrays in the high-uniform-weight digital power amplifier array on the layout has symmetry, so that the phenomena of performance deterioration and reliability reduction of a chip caused by local overheating of the chip are avoided.

A method of digital power transmitting chip impedance modulation, the method comprising:

the digital control module carries out quantization coding on the baseband signal to obtain a power coding signal, and then the signal is transcoded into a power control signal A-A ', a static voltage control signal B, B' and a variable parameter control signal C; the power control signals A-A 'are used for controlling the working state of a driving power amplifier in a driving power distribution network, the static voltage control signal B, B' respectively provides effective bias for a high-uniform-weight digital power amplifier and a low-non-uniform-weight digital power amplifier in a digital power amplifier array, and the variable parameter control signal C controls a variable parameter element matching unit in a reconfigurable output matching network;

the power control signals A-A' control the driving power distribution network to realize the matching of the input impedance, and the specific process is as follows: the on and off of the driving power amplifiers in each stage of driving power distribution subunit are respectively controlled by power control signals A-A ', and each driving power amplifier corresponds to one bit of the power control signals A-A'; the on-off condition of each digital power amplifier in the high-uniform-weight digital power amplifier array is kept consistent with the on-off condition of a driving power amplifier in a final-stage driving power distribution subunit connected with the digital power amplifier array;

the number of bits of the static voltage control signal B is equal to the number of the digital power amplifiers with high uniform weight, and one bit corresponds to one digital power amplifier; if the digital power amplifier is in an open state, the static voltage control signal B provides effective bias for the digital power amplifier, and simultaneously controls a driving power amplifier corresponding to a preceding stage of the digital power amplifier to be open; if the digital power amplifier is in a turn-off state, the static voltage control signal B is set to an invalid level which cannot provide bias for the digital power amplifier, and meanwhile, the corresponding driving power amplifier of the front stage of the digital power amplifier is controlled to be turned off; the two steps can ensure that each high uniform weight digital power amplifier is accurately in an on/off state;

the control law of the static voltage control signal B is the same as that of the static voltage control signal B, and each bit of the static voltage control signal B' provides effective bias for a digital power amplifier with low non-uniform weight.

The variable parameter control signal C adjusts the variable parameter element matching unit, changes the load impedance transformation value of the unit to the transmitting chip, further changes the input impedance of the variable parameter element matching unit, and realizes the fine adjustment of the output matching impedance modulation; the output pre-matching unit and the variable parameter element matching unit jointly realize the function of modulating the output impedance of the digital power amplifier array, so that the load impedance of the digital transmitting chip and the output impedance of the digital power amplifier array are well matched.

Further, the digital control module transcodes the H-bit power coded signal into a static voltage control signal B, B' in a moving temperature coding mode; the high h bit of the power coding signal is transcoded into a static voltage control signal B, and the static voltage control signal B is used for controlling the digital power amplifiers with high uniform weight in an open state to be uniformly distributed in each digital power amplifier subarray; the remaining low H-H bits of the power encoded signal do not need transcoding, i.e. are equal to the static voltage control signal B', and are directly used for controlling the digital power amplifier with low non-uniform weight.

Further, the moving temperature encoding is similar to temperature encoding. The temperature coding is to decode progressive binary original codes with the step length of 1 into temperature codes changing from low bit to high bit by 1, but the result of moving the temperature coding and decoding is to change 1 every n-1 bits (n is the number of high uniform weight digital power amplifiers contained in a single digital power amplifier subarray); that is, counting from the lowest bit (0 th bit) to the high bit at an interval of n-1 bits, the nth bit is used as the next bit to change to 1, and so on; if the number of the highest bit of a certain bit is less than n, the highest bit is counted, and then the lowest bit is skipped to continue counting.

Further, the power control signals A-A' need to control the N-level driving power amplifier; the control code word of each driving power amplifier in the kth-1 stage driving power distribution subunit may be the or of all the control code words of all the driving power amplifiers in the kth stage connected to the control code word; that is, when one driving power amplifier in the kth driving power distribution subunit is in an on state, the corresponding driving power amplifier of the kth-1 stage is on certainly; and the control code word for driving the power amplifier in the final-stage driving power distribution subunit is the same as the static voltage control signal B.

Furthermore, the power control signals A-A' control the digital power amplifiers in the open state to be relatively uniformly distributed in each digital power amplifier subarray, so that the loads carried by each final-stage driving power distribution subunit are kept equal, the digital power amplifiers in the open state are uniformly distributed around the chip layout, the heat dissipation area of the chip is increased, and the phenomena of performance deterioration and reliability reduction caused by local overheating of the chip are avoided.

Further, the variable parameter control signal C controls the impedance transformation value of the network to the chip load by controlling the variable parameters of the elements in the variable parameter element matching unit.

In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:

the input impedance of the digital power amplifier array is modulated by the power distribution network driven by multiple stages, so that the impedance change value is limited in a smaller range when the output power is changed; and simultaneously, the reconfigurable output matching network is used for modulating the load impedance of the digital transmitter, so that the load impedance of the digital transmitter is better matched with the output impedance of the digital power amplifier array. Therefore, the scheme of the invention solves the problem that the design difficulty of the input/output impedance matching network of the digital power transmitting chip is increased sharply under the excitation of signals with large dynamic range, enables the thermal management of the chip to be more effective and improves the efficiency of the digital transmitter.

Drawings

Fig. 1 is a block diagram of an impedance modulation system of a digital power transmitting chip according to the present invention.

Fig. 2 is a schematic diagram of a cascade of multi-stage driving power distribution networks according to the present invention.

Fig. 3 is a block diagram of a primary driving power distribution subunit in the present invention.

Fig. 4 is a block diagram of the high uniform weight digital power amplifier array structure of the present invention.

Fig. 5 is a block diagram of a low non-uniform weight digital power amplifier array structure according to the present invention.

Fig. 6 is a block diagram of the impedance modulation method of the digital power transmitting chip of the present invention.

Fig. 7 is a schematic diagram of a balun structure adopted by the power distribution module in the embodiment of the present invention.

Fig. 8 is a block diagram of a single-ended-to-differential conversion module of a previous stage of a primary driving power sub-unit according to an embodiment of the present invention.

Fig. 9 is a block diagram of an output pre-matching unit according to an embodiment of the present invention.

Fig. 10 is a block diagram of a switched capacitor matching network in an embodiment of the invention.

Fig. 11 is a block diagram of the switched capacitor array 2 according to the embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings.

Example 1

The embodiment of the invention provides an impedance modulation system applied to a digital power transmitting chip with 4bit MSB and 4bit LSB, the block diagram of which is shown in figure 1, and the impedance modulation system comprises a driving power distribution network 101, a digital power amplifier array 102, a reconfigurable output matching network 103 and a digital control module 104;

the driving power distribution network 101 is formed by n stages of driving power distribution subunit (driving power distribution subunit for short) connected in series, and a cascade schematic diagram is shown in fig. 2, where each stage of driving power distribution subunit includes a power distribution module and a plurality of driving power amplifiers (driving amplifier for short) connected to the power distribution module, and an input of the nth stage of power distribution module is connected to an output of the nth-1 stage of driving amplifier. In this embodiment, the number of stages N is 2, a block diagram of the primary driving power splitting subunit 201 is shown in fig. 3, the power distribution module 301 adopts a balun structure, the balun divides a phase modulation signal input from a port 1' into 4 paths of signals (t is 4) with equal power, and the signals are respectively sent to 4 paths of driving amplifiers, each path of driving amplifier is output from a port 1 "-" 4", and is respectively connected to one secondary driving power splitting subunit; the structures of the 4 second-stage (also the final stage in this example) driving power sub-units 202 are the same as those of the primary driving power sub-unit, wherein the outputs of the second-stage driving (16 paths of outputs in total of the 4 second-stage sub-units) are connected with the inputs of the high-uniform-weight digital power amplifier sub-arrays 401 to 404 shown in fig. 4. The driving amplifier is used for providing proper input power for a driving power molecular unit or a digital power amplifier array of the next stage.

It is noted that the power distribution module 301 in each stage of sub-unit is not limited to be implemented in a balun structure. The balun structure is shown in fig. 7, and adopts a differential input and differential output mode, so that a single-ended differential-to-differential module shown in fig. 8 is added at a preceding stage of the primary driving power splitting unit, and is used for converting an input single-ended phase modulation signal into a differential signal; in addition, the drive and discharge connected behind the balun also adopt a differential structure. The balun not only performs 4-path equal power distribution on the input signal, but also can limit the input impedance of the balun to be kept stable under the condition that the on-off state of the subsequent driving and discharging is changed.

The digital power amplifier array 102 adopts a differential structure, and comprises a high uniform weight digital power amplifier array 108 and a low non-uniform weight digital power amplifier array 109. The high-uniform-weight digital power amplifier array is composed of m sub-arrays, as shown in fig. 4(m is 4)401 to 404, wherein each sub-array includes 4 high-uniform-weight differential digital power amplifiers (n is 4), so that the total number of the digital power amplifiers is 16; the low non-uniform weight digital power amplifier array comprises 4 differential digital power amplifiers with non-uniform weights and a coupling unit, and the structure of the low non-uniform weight digital power amplifier array is shown in fig. 5.

In fig. 2, each path of the output (total 16 paths) of the driving amplifier 302 in the final driving power sub-unit is connected with a differential digital power amplifier with uniform weight in the high uniform weight digital power amplifier sub-arrays 401-404, while the input of the differential digital power amplifier sub-array with low non-uniform weight is directly provided by a phase modulation signal, and the output of the digital power amplifier sub-array with high uniform weight is connected with the reconfigurable output matching network 103 in fig. 1.

The input impedance of the digital power amplifier array 102 is modulated by the power distribution network 101 driven by multiple stages. As shown in fig. 3, the driving power sub-unit is equivalent to a multi-port network, an input port is an input of the power distribution module, and an output port is an output of the t-way driving amplifier. The input impedance of the medium and high uniform weight digital power amplifier of the digital power amplifier array is an equivalent load driven and amplified in the final-stage driving power molecular unit 20N; similarly, in the multi-stage driving and amplifying link, the input impedance of the power dividing subunit driven by the rear stage is the equivalent load of the power dividing subunit driven by the front stage. Each timeThe stage-driven power sub-unit performs impedance transformation on its equivalent load, so that the input impedance of the digital power amplifier sub-array is modulated stage by stage through the driving power distribution network, and finally appears as the input impedance of the driving power distribution network 101, such as Z indicated in fig. 1_DPAin*. The low non-uniform weight digital power amplifier has relatively small power, so that the input impedance modulation of the digital power amplifier array is relatively little influenced.

When the power of a baseband signal changes, controlling the high-uniform-weight digital power amplifier in an on state to be relatively uniformly distributed in each subarray, so that equivalent loads loaded by the driving power sub-units of each final stage are equivalent, the input impedance of each final stage sub-unit is equivalent, and the like; finally, equivalent loads loaded by each driver in the primary driving power molecular unit are equivalent, and the change of the input impedance value of the driving power distribution network can be limited within a small range after passing through the power distribution module, so that good matching with the output impedance of the front stage of the network can be kept.

The reconfigurable output matching network 103 is used for realizing matching between the output impedance of the digital power amplifier array and the load impedance of the digital transmitting chip and performing power synthesis on the output of the digital power amplifier array; as shown in fig. 1, the configuration includes an output pre-matching unit 105, a power combining unit 106, and a variable parameter element matching unit 107, which are connected in this order. In this embodiment, the output pre-matching unit 105 is configured to pre-match the output impedance of the digital power amplifier array, and the structure of the output pre-matching unit is as shown in fig. 9, in the high-uniform-weight digital power amplifier sub-array, the output of each path of differential digital power amplifier is connected to one Marchand balun, and the structure realizes the function of impedance modulation; the output of each path of Marchand balun is output to the power synthesis unit 106 through a coupling unit;

the power combining unit 106 performs power combining on the outputs of the respective digital power amplifier sub-arrays and outputs the resultant to the variable parameter element matching unit 107. The power synthesis unit may also adopt a balun structure shown in fig. 7, and may convert the input and output ports into four paths of differential synthesis one path of differential power synthesis structure by interchanging them, and the output of each high uniform weight digital power amplifier subarray is synthesized by adopting one synthesis structure, and finally the four paths of synthesized signals of the four subarrays are synthesized into one path of power signal by one synthesis structure. The output of the low non-uniform weight digital power amplifier array may be directly connected to the final composite power signal.

The variable parameter element matching unit 107 modulates the load impedance of the digital transmitting chip, and is formed by combining a switched capacitor array with a transmission line, and the structure of the variable parameter element matching unit is shown in fig. 10. Power combined signal v₃₀₁The signal is input into a switched capacitor array 1002 through a transmission line 1001, and is output to a transmitting chip load after passing through a transmission line 1003. The switched capacitor array 1002 is formed by connecting r branches in parallel, and each branch is formed by connecting a constant value capacitor and a switched capacitor in series. Wherein r switched capacitors are controlled by r bits of variable parameter control signal C, and one switched capacitor corresponds to one bit in signal C. It is noted that the specific structure of the transmission lines 1001 and 1003 shown in fig. 10 may not be the same. The switched capacitor array 1002 may employ a switched capacitor array 2 shown at 1101 in fig. 11 in addition to the switched capacitor array 1 shown in fig. 10. The circuit is formed by connecting a balun transformer and r switching capacitors in parallel, and each switching capacitor is also controlled by a corresponding bit in an r-bit variable parameter control signal C.

Other structures known to those skilled in the art may be adopted, and are not limited to the two circuits illustrated in the present embodiment.

To illustrate the principle of impedance transformation in the reconfigurable output matching network 103, the following is described in detail: the load impedance is transformed by the matching unit of the variable parameter element to become a signal v as shown in FIG. 1₃₀₁Impedance Z_load*. For the power combining unit 106, the signal v₃₀₁Takes the current value as the signal v₃₀₁'～v_30m' sum of currents, and signal v under the same voltage₃₀₁'～v_30m' where the impedance value can reach the signal v₃₀₁X times the value of the impedance (x equals the signal v)₃₀₁Current magnitude and signal v of₃₀₁'～v_30mAt the ratio of the magnitudes of the currents), i.e.Z_load*X times of (c). To make the signal v₃₀₁'～v_30m' impedance at position xZ_load*Ideal load impedance R of high uniform weight digital power amplifier_optKeeping the consistency, and transforming the consistency through an output pre-matching unit. R_optThe method can be obtained by carrying out load traction on the digital power amplifier and the like. The low non-uniform weight digital power amplifier has relatively small output current, and is v-pair₃₀₁The impedance value has relatively little influence.

The digital control module 104 is configured to perform quantization coding on the baseband signal to obtain an H-bit power encoded signal, so as to control the driving power distribution network, the digital power amplifier array, and the reconfigurable matching network, specifically: the digital control module transcodes the power coding signal into a static voltage control signal B, and only the high h bit of the power coding signal is needed by adopting a mobile temperature coding mode. The function of the static voltage control signal B after transcoding is to control the digital power amplifiers with high uniform weight in the open state to be uniformly distributed in each digital power amplifier sub-array. The remaining low H-H bits of the power encoded signal do not need transcoding, i.e. are equal to the static voltage control signal B', and are directly used for controlling the digital power amplifier with low non-uniform weight.

The invention further provides an impedance modulation method based on the impedance modulation system, and a block diagram of the method is shown in fig. 6, and the method specifically includes:

the digital control module 104 quantizes and encodes the baseband signal to obtain an 8-bit power encoded signal, and then transcodes the signal into a power control signal A, A ', a static voltage control signal B, B' and a variable parameter control signal C; the power control signal A, A 'controls the on and off of the driver in the driver power distribution network, the static voltage control signal B, B' provides effective bias for the high uniform weight differential digital power amplifier and the low non-uniform weight differential digital power amplifier in the digital power amplifier array, and the variable parameter control signal C controls the switch capacitor in the variable parameter element matching unit.

The power control signals a-a' control the drive power distribution network 101 to achieve input impedance matching. Further, in the driving power sub-units 201 to 202(N is 2) shown in fig. 2, the on and off of each driving amplifier is controlled by a corresponding bit in the power control signal A, A'. For example, the balun in the primary driving power splitting unit 201 splits the input into four outputs (t is 4), and 4 driving amplifiers connected downstream from the balun are controlled by a [0] to a [3 ]; the balun in the first second-stage driving power-dividing subunit 202 divides the input into 4 paths of outputs, and 4 driving amplifiers connected behind the balun are respectively controlled by A '[0] to A' [3 ]; the second stage drives 4 of the work molecule units and is controlled by A '4-A' 7.

The specific structure of the digital power amplifier array 102 is shown in fig. 4 and 5 (m is 4, and n is 4). The input of the differential digital power amplifier with high uniform weight is connected with the output (total 16 paths) of the driving amplifier in the second-stage driving power molecular unit 202, wherein the on-off state of each differential digital power amplifier is influenced by the on-off state of the driving amplifier at the previous stage. The bias of the differential digital power amplifier is controlled by a corresponding bit of the codeword of the quiescent voltage control signal B, B'. For example, the bias of the differential digital power amplifier subarray 1 with high uniform weight is controlled by static voltage control signal code words B [00] to B [03], the bias of the subarray 2 is controlled by static voltage control signal code words B [10] to B [13], and so on.

The on-off state of the high-uniform-weight differential digital power amplifier is consistent with the on-off state of the drive amplifier in the last-stage drive power molecule unit connected with the high-uniform-weight differential digital power amplifier, as shown in fig. 4, when the differential digital power amplifiers in the digital power amplifier subarrays 401-404 are on, effective bias is provided for the differential digital power amplifier through a static voltage control signal B; meanwhile, the front-stage drive amplifier is controlled to be switched on. If the differential digital power amplifier is in a turn-off state, the static voltage control signal B is set at a low level; meanwhile, the front-end drive discharge is controlled to be closed. The two steps can ensure that each pair of high uniform weight differential power amplifiers is in an on/off state.

The input impedance of the digital power amplifier sub-array is modulated by the power distribution network 101 driven by multiple stages. As shown in fig. 3, each stage of the driving power sub-unit may be equivalent to a network with 5(t ═ 4) ports. The input port is the input of the balun, and the output port is the output of the 4-way drive amplifier. Each output port of the second-stage driving power sub-unit is correspondingly connected to a difference in the digital power amplifier sub-arrays 401-404 in the figureDividing a digital power amplifier, wherein the input impedance of the digital power amplifier subarray is the equivalent load of the second-stage driving power divider unit 202; similarly, the input impedance of the secondary driving power molecular unit is the equivalent load of the primary driving power molecular unit 201. The input impedance of the digital power amplifier subarray is subjected to impedance transformation through the second-stage driving power dividing unit 202, and is represented as the input impedance of the second-stage driving power dividing unit 202; similarly, the input impedance of the second-stage driving power dividing unit 202 obtains impedance transformation through the primary-stage driving power dividing unit 201, and finally appears as the input impedance of the driving power dividing network 102, i.e. Z shown in fig. 1_DPAin*。

When the baseband signal power changes, the high-uniform-weight differential digital power amplifiers in the on state are controlled to be uniformly distributed in 4 sub-arrays 401 to 404(m is 4) shown in fig. 4, the serial numbers of the amplifiers are 1, 2, 3 and 4 respectively, for example, the on differential power amplifiers are sequentially positioned in sub-arrays 1, 4, 3, 2, 1, 4, 3, 2 and … …, the equivalent loads loaded by the 4 driving power dividing sub-units of the second stage are equivalent, and the structures of the equivalent loads are the same, namely the input impedances of the equivalent loads are equivalent. Furthermore, for the primary driving power splitting unit 201, the equivalent load of each driving amplifier is equivalent, and then the balun structure is combined to keep the variation of the input impedance value of the primary driving power splitting unit 201 in a small range. Finally, the input impedance of the digital power amplifier array 102 keeps good matching with the output impedance of the previous stage after impedance transformation by the driving power distribution network 101. Meanwhile, the power control signals a to a ″ control the differential power amplifiers in the on state to be uniformly distributed in the 4 sub-arrays 401 to 404 shown in fig. 4, so that the differential digital power amplifiers in the on state are more uniformly distributed on the circuit layout, for example, the power amplifiers in the on state are sequentially located in sub-arrays 1, 4, 3, 2, and … …, and the number of the differential digital power amplifiers in the on state in each sub-array is equivalent, thereby improving the heat dissipation area of the chip and avoiding the phenomena of performance deterioration and reliability reduction caused by local overheating of the chip.

As shown in FIG. 10, the variable parameter control signal is applied while the output pre-matching unit is operatingThe signal C adjusts the capacitance of the switched capacitor array 1002 to change the impedance transformation of the transmit chip load impedance through the array and transmission line, shown as Z in FIG. 1_load*And further changes the signal v₃₀₁'～v_30m' impedance at position xZ_load*And the fine adjustment of the output matching impedance modulation is realized.

The digital control module transcodes the power coding signal into a static voltage control signal B, and a mobile temperature coding mode is adopted. In the embodiment, the power coding signal is designed to be 8 bits, the high 4 bits of the power coding signal are adopted for transcoding, and the rest low 4 bits are used as static voltage control signals B' and are directly used for controlling the digital power amplifier with low non-uniform weight. And the moving temperature coding is to decode the progressive binary original code with the step length of 1 into the moving temperature code changing to 1 every 3 bits. That is, the number of bits from the lowest bit (0 th bit) is counted from the lower bit to the higher bit at an interval of 3 bits, and the 4 th bit is the next bit to be changed to 1, and so on; if the number of the highest digit of a certain digit is less than 4, the digit jumps to the lowest digit to continue counting after the highest digit is counted. If the high 4 bits of the power coded signal are 0101, the transcoding result is 001000100010011; when the upper 4 bits are 0110, the result of transcoding is 001000100110011.

The truth table of the mobile temperature encoding scheme in this embodiment is shown in table 1.

TABLE 1

The power control signal a needs to control 2 (N-2) stage driving. The primary driving power dividing unit is a one-to-four driving power dividing unit, and 4 driving amplifiers are respectively set as a, b, c and d. The second stage driving power dividing unit is 4 identical one-to-four driving power dividing units, which are respectively set as units p, q, u and v, wherein the control words for driving are respectively A '[0] to A' [3], A '[4] to A' [7], A '[8] to A' [11] and A '[12] to A' [15] (m is 4, n is 4), and the same as the static voltage control signal B. The unit p corresponds to the driving and amplifying a in the primary driving power dividing unit, the control word A [0] of the driving and amplifying a, and the OR of the control words A '[0] to A' [3] driven and amplified in the unit p. For example, when the high 4 bits of the power encoded signal are 0101, the signal B is 001000100010011, the A '[0] to A' [3] are 0011, the A '[4] to A' [7] are 0001, the A '[8] to A' [11] are 0001, and the A '[12] to A' [15] are 0001; then A0 is equal to or from A '0 to A' 3, or 1.

The variable parameter control signal C has r bits in total, a temperature coding mode is adopted, and when the capacitance value of the required switched capacitor array is large, more switched capacitors are switched on; when the capacitance value of the required switched capacitor array is small, more switched capacitors are disconnected. The capacitance value of the required switched capacitor array is determined according to the specific requirement when the load impedance of the chip is transformed.

While the invention has been described with reference to specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.