阅读说明：本技术 一种缓存设备的数据下刷方法和系统 (Data flushing method and system of cache device ) 是由 张英杰 孟祥瑞 于 2021-08-16 设计创作，主要内容包括：本发明公开一种缓存设备的数据下刷方法和系统,其中,缓存设备的数据下刷方法包括：当缓存设备需要下刷数据时,根据所述缓存设备的LRU队列提取数据对象；按照所述数据对象在所述缓存设备的逻辑区块地址,对所述数据对象进行排序；将排序后的所述数据对象依次插入在所述缓存设备的下刷工作队列中,以下刷至主存设备。本发明的技术方案能解决现有技术中缓存设备读写性能不佳的问题。(The invention discloses a data flushing method and a data flushing system of cache equipment, wherein the data flushing method of the cache equipment comprises the following steps: when the cache equipment needs to flush data, extracting a data object according to the LRU queue of the cache equipment; sorting the data objects according to the logical block addresses of the data objects in the cache equipment; and sequentially inserting the sequenced data objects into a lower brushing work queue of the cache device, and brushing the data objects to the main memory device. The technical scheme of the invention can solve the problem of poor read-write performance of the cache device in the prior art.)

1. A data flushing method of a cache device is characterized by comprising the following steps:

when the cache equipment needs to flush data, extracting a data object according to the LRU queue of the cache equipment;

sorting the data objects according to the logical block addresses of the data objects in the cache equipment;

and sequentially inserting the sequenced data objects into a lower brushing work queue of the cache device, and brushing the data objects to the main memory device.

2. The data flushing method of the cache device according to claim 1, wherein the step of extracting the data object according to the LRU queue of the cache device comprises:

acquiring a preset number of object pointers at the tail part in the LRU queue;

and extracting the data objects corresponding to the preset number of object pointers from the lower brushing work queue.

3. The data flushing method of the cache device according to claim 1, wherein the step of sorting the data objects according to their logical block addresses in the cache device comprises:

acquiring a logical block address of the data object in a data logical interval of the cache device;

and sequencing the data objects in sequence according to the increasing rule of the address linearity of the logic block.

4. The data flushing method of the cache device according to claim 3, wherein the step of sorting the data objects according to the rule that the address of the logical block is increased linearly comprises:

acquiring the physical address of the data object mapped by the logical block address;

and reordering the logical block addresses of the data object in sequence according to the front and back sequence of the physical addresses.

5. The data brushing method of the cache device according to claim 3, further comprising:

and refreshing the logical block address information of the data object so that the main memory device searches and reads the data object according to the corresponding relation between the logical block address in the logical block address information and the CHS address.

6. The data flushing method of the cache device according to claim 1, further comprising:

and after the data object is flushed to the main memory device, deleting the object pointer of the data object from the LRU queue.

7. A data flushing system of a cache device, comprising:

the object extraction module is used for extracting data objects according to the LRU queue of the cache equipment when the cache equipment needs to refresh data;

the object sorting module is used for sorting the data objects according to the logical block addresses of the data objects in the cache equipment;

and the object inserting module is used for sequentially inserting the sequenced data objects into the lower brushing work queue of the cache device and brushing the data objects to the main memory device.

8. The data flushing system of the cache device of claim 7, wherein the object extraction module comprises:

a pointer obtaining submodule for obtaining a predetermined number of object pointers at the tail of the LRU queue;

and the object acquisition submodule is used for extracting the data objects corresponding to the preset number of object pointers from the lower-brushing work queue.

9. The data flushing system of the cache device of claim 7, wherein the object ordering module comprises:

the address acquisition submodule is used for acquiring a logical block address of the data object in a data logical interval of the cache device;

and the data sorting submodule is used for sequentially sorting the data objects according to the increasing rule of the address linearity of the logic block.

10. The data flushing system of the cache device of claim 7, further comprising:

and the pointer deleting module is used for deleting the object pointer of the data object from the LRU queue after the data object is flushed to the main memory device.

Technical Field

The invention relates to the technical field of distributed storage, in particular to a data flushing method and system of a cache device.

Background

There are generally two types of storage media in a distributed storage system: one is a mechanical hard disk HDD with large storage capacity and low price; the solid state disk SSD has the advantages of small storage capacity, high access speed, randomness and better concurrency performance. As shown in fig. 1, in a distributed storage system, generally, an SSD is used as a cache device 100, an HDD is used as a main storage device 200, a read-write success message is returned after data is written into the cache device 100, and then the data in the cache device 100 (i.e., the SSD) is asynchronously printed onto the main storage device 200, so that response time of a read-write request can be increased, and requirements in both cost and performance are taken into consideration.

However, the capacity of the cache device (i.e., SSD) is limited, when the space of the cache device is insufficient, the data in the cache device needs to be flushed to release the space, and the slow data flushing speed of the cache device may adversely affect the response delay of the data request. The data brushing speed of the cache device is related to the reading and writing speed of the main memory device, and the reading and writing speed of the HDD serving as the main memory device is greatly influenced by the physical structure of the HDD. When the HDD sequentially executes read and write requests, it operates on the physical medium in the hierarchical order of three layers, sector, head, and cylinder, to perform data acquisition/write operations. However, during cylinder switching, the disk must be mechanically switched to the head position, and the suspension is moved to move the head to the track corresponding to the data location, i.e., a seek operation. Seek operations are the most time consuming part of the disk read/write process, far exceeding the time consumed by other processes such as disk rotation delay, data access and data transfer. When the HDD executes random read and write requests, seek operations need to be performed more frequently, and thus performance is significantly different from sequential read and write operations.

In a distributed storage system, the flushing of data in a cache device usually adopts a least recently used policy LRU algorithm, which selects a data object with the lowest liveness in an LRU queue to be dequeued and written into a main storage device during the flushing. Because the flushed cold data is often unrelated, the main memory device may be confronted with a large number of random write requests, and a large amount of time is wasted in performing a track change operation on the disk, thereby resulting in poor read/write performance.

Disclosure of Invention

The invention provides a data refreshing method and a data refreshing system of cache equipment, and aims to solve the problem that data reading and writing performance is poor due to refreshing of data objects by an LRU (least recently used) algorithm in the prior art.

According to a first aspect of the present invention, the present invention provides a data flushing method for a cache device, including:

when the cache equipment needs to refresh data, extracting a data object according to an LRU queue of the cache equipment;

sorting the data objects according to the logical block addresses of the data objects in the cache equipment;

and sequentially inserting the sorted data objects into a lower brushing work queue of the cache device, and brushing the data objects to the main memory device from the lower brushing work queue.

Preferably, the step of extracting the data object according to the LRU queue of the cache device includes:

acquiring a preset number of object pointers at the tail part in an LRU queue;

and extracting data objects corresponding to the preset number of object pointers from the lower brushing work queue.

Preferably, the step of sorting the data objects according to the logical block addresses of the data objects in the cache device includes:

acquiring a logical block address of a data object in a data logical interval of a cache device;

and sequencing the data objects in sequence according to the increasing rule of the address linearity of the logic block.

Preferably, the step of sorting the data objects according to the ascending rule of the address linearity of the logic block includes:

acquiring a physical address of a data object mapped by a logical block address;

and reordering the logical block addresses of the data object in sequence according to the front-back sequence of the physical addresses.

Preferably, the data flushing method of the cache device further includes:

and refreshing the logical block address information of the data object so that the main memory device searches and reads the data object according to the corresponding relation between the logical block address in the logical block address information and the CHS address.

Preferably, the data flushing method of the cache device further includes:

and after the data object is flushed to the main memory device, deleting the object pointer of the data object from the LRU queue.

According to a second aspect of the present invention, the present invention further provides a data flushing system of a cache device, including:

the object extraction module is used for extracting the data object according to the LRU queue of the cache equipment when the cache equipment needs to refresh data;

the object sorting module is used for sorting the data objects according to the logical block addresses of the data objects in the cache equipment;

and the object inserting module is used for sequentially inserting the sequenced data objects into the lower brushing work queue of the cache device and brushing the data objects to the main memory device.

Preferably, the object extraction module includes:

the pointer acquisition submodule is used for acquiring a preset number of object pointers at the tail part in the LRU queue;

and the object acquisition submodule is used for extracting the data objects corresponding to the preset number of object pointers from the lower-brushing work queue.

Preferably, the object sorting module includes:

the address acquisition submodule is used for acquiring the logical block address of the data object in the data logical interval of the cache device;

and the data sorting submodule is used for sequentially sorting the data objects according to the increasing rule of the address linearity of the logic block.

Preferably, the data flushing system of the cache device further includes:

and the pointer deleting module is used for deleting the object pointer of the data object from the LRU queue after the data object is flushed to the main memory device.

According to the data brushing scheme of the cache device, the data objects are extracted from the cache device according to the LRU queue of the cache device, then the data objects are arranged according to the logical block addresses of the data objects in the cache device, and the sorted data objects are sequentially inserted into the brushing work queue of the cache device, so that the data objects are brushed down to the main memory device. Because the addressing mode CHS addressing of the main memory device addresses the data object according to the cylinder, the magnetic head and the sector of the main memory device, and the CHS addressing has a mapping relation with the logical block address of the cache device, the main memory device can quickly read the data object after the data object is sequenced in the logical block address of the cache device, the data writing speed of the cache device is positively correlated with the reading speed of the main memory device, and the storage space is released because the data object in the cache device is flushed, so the flushing speed of the cache device is greatly improved, and the reading and writing performance and the stability of the storage system are improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

FIG. 1 is a schematic diagram of a distributed storage system according to an embodiment of the present invention;

fig. 2 is a schematic flowchart of a data flushing method of a first cache device according to an embodiment of the present invention;

FIG. 3 is a flow chart of a data object extraction method provided by the embodiment shown in FIG. 2;

FIG. 4 is a flow chart illustrating a data object sorting method provided by the embodiment shown in FIG. 2;

FIG. 5 is a flowchart illustrating a method for sequentially ordering data objects according to the embodiment shown in FIG. 4;

fig. 6 is a schematic flowchart of a data flushing method of a second cache device according to an embodiment of the present invention;

fig. 7 is a flowchart illustrating a data flushing method of a third cache device according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a data flushing system of a first cache device according to an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of an object extraction module provided in the embodiment shown in FIG. 8;

FIG. 10 is a block diagram illustrating an object sorting module according to the embodiment shown in FIG. 8;

fig. 11 is a schematic structural diagram of a data flushing system of a second cache device according to an embodiment of the present invention.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Reference numerals	Name (R)	Reference numerals	Name (R)
				100	Cache device	200	Main memory device

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The main technical problems of the embodiment of the invention are as follows:

in a distributed storage system, the flushing of data in a cache device usually adopts a least recently used policy LRU algorithm, which selects a data object with the lowest liveness in an LRU queue to be dequeued and written into a main storage device during the flushing. Because the flushed cold data is often unrelated, the main memory device may be confronted with a large number of random write requests, and a large amount of time is wasted in performing a track change operation on the disk, thereby resulting in poor read/write performance.

In order to solve the above problem, specifically referring to fig. 2, fig. 2 is a schematic flow chart of a data flushing method of a cache device according to an embodiment of the present invention, as shown in fig. 2, according to a first aspect of the present invention, the present invention provides a data flushing method of a cache device, including:

s110: when the cache equipment needs to refresh data, extracting a data object according to an LRU queue of the cache equipment; generally, when the cache device flushes data, the data object is stored in a flushing work queue of the cache device, and the LRU queue stores an object pointer of the data object, so that the position of the data object in the flushing work queue can be found by searching the object pointer of the data object in the LRU queue.

As a preferred embodiment, as shown in fig. 3, the step of extracting the data object according to the LRU queue of the cache device specifically includes:

s111: a predetermined number of object pointers at the tail of the LRU queue are obtained. The LRU queue is a container for maintaining the cold and hot degree of data, and the hot degree of the data object corresponding to the object pointer at the tail of the LRU queue is usually low, so that if the cold data object with low hot degree can be first flushed to the HDD of the main storage device, the storage space of the cache device can be made free, and the flushing efficiency of the cache device can be improved.

S112: and extracting the data objects corresponding to the object pointers with the preset number from the lower brushing work queue. By extracting the data objects corresponding to the preset number of object pointers in the brushing-down work queue, reordering the data objects according to the logical block address, and brushing the data objects down to the main memory device, the main memory device can quickly and efficiently read and write the data objects in a CHS (chip size cut) addressing mode, so that the brushing-down efficiency of the cache device can be further improved.

As shown in fig. 2, after step S110, the data flushing method of the above-mentioned cache device further includes the following steps:

s120: sorting the data objects according to the logical block addresses of the data objects in the cache equipment; the logical block addresses correspond to the physical addresses of the data objects in the cache device, when the data objects are sorted according to the logical block addresses of the data objects in the cache device, that is, according to the physical addresses, a certain sequence of data objects can be obtained, for example, the data addresses in a linear increasing sequence, because the logical block addresses have a mapping relation with the CHS addressing mode of the main memory device, after the data objects are sorted according to the logical block addresses, the main memory device can regularly use CHS addressing according to three layers of sectors, magnetic heads and cylinders, and frequent mechanical switching of the positions of the magnetic heads is not needed.

Specifically, as a preferred embodiment, as shown in fig. 4, the step of sorting the data objects according to the logical block addresses of the data objects in the cache device specifically includes:

s121: and acquiring the logical block address of the data object in the data logical interval of the cache equipment. The logical block address is located in a data logical interval of the cache device, the data logical interval contains logical block addresses of a large number of data objects, and the physical address of the data object in the cache device can be obtained by inquiring the logical block address of the data logical interval.

S122: and sequencing the data objects in sequence according to the increasing rule of the address linearity of the logic block.

As a preferred embodiment, as shown in fig. 5, the step of sorting the data objects according to the rule of linear increase of the logical block addresses includes:

s1221: acquiring a physical address of a data object mapped by a logical block address;

s1222: and reordering the logical block addresses of the data object in sequence according to the front-back sequence of the physical addresses.

The logical block address LBA corresponds to the physical address of the data object in the cache device, so that the data object can be sequentially ordered in an increasing manner according to the increasing rule of the logical block address linearity, that is, according to the increasing rule of the physical address linearity of the data object.

As shown in fig. 2, after step S120, the data flushing method of the above-mentioned cache device further includes the following steps:

s130: and sequentially inserting the sorted data objects into a lower brushing work queue of the cache device, and brushing the data objects to the main memory device from the lower brushing work queue.

According to the data flushing method of the cache device, the data objects are extracted from the cache device according to the LRU queue of the cache device, then the data objects are arranged according to the logical block addresses of the data objects in the cache device, and the sorted data objects are sequentially inserted into the flushing work queue of the cache device, so that the data objects are flushed to the main memory device. Because the addressing mode CHS addressing of the main memory device addresses the data object according to the cylinder, the magnetic head and the sector of the main memory device, and the CHS addressing has a mapping relation with the logical block address of the cache device, the main memory device can quickly read the data object after the data object is sequenced in the logical block address of the cache device, the data writing speed of the cache device is positively correlated with the reading speed of the main memory device, and the storage space is released because the data object in the cache device is flushed, so the flushing speed of the cache device is greatly improved, and the reading and writing performance and the stability of the storage system are improved.

As a preferred embodiment, as shown in fig. 6, the data flushing method of the cache device provided in the embodiment of the present application further includes, in addition to the above steps:

s210: and refreshing the logical block address information of the data object so that the main memory device searches and reads the data object according to the corresponding relation between the logical block address in the logical block address information and the CHS address.

Because the logical block address information includes the logical block address of each data object to be flushed down and because the logical block address corresponds to the CHS address of the main memory device, the main memory device can search and read the data object according to the correspondence, the reading efficiency of the data object is improved, and the flushing speed of the cache device is further improved.

Specifically, the mapping relationship between the LBA and the CHS addressing mode is as follows:

the CHS address can be converted to an LBA using the following equation:

#lba＝(#c*H+#h)*S+#s-1。

the LBA address can correspond to the CHS address with the following formula:

#chs＝#lba/(S*H)#h＝(#lba/S)％H#s＝(#lba％S)+1。

wherein, # c, # h, and # s are numbers of cylinder, head, and sector, respectively;

# lba is the logical block number;

h is the number of heads per cylinder;

s is the number of sectors per track.

As a preferred embodiment, as shown in fig. 7, the data flushing method of the cache device according to the embodiment of the present application further includes the following steps in addition to the above steps:

s310: and after the data object is flushed to the main memory device, deleting the object pointer of the data object from the LRU queue.

According to the technical scheme, after the data objects are flushed to the main memory device, the object pointers of the data objects are deleted from the LRU queue, the situation that the flushed data objects are searched wrongly when the address is flushed next time can be avoided, the space of the cache device is released, and the flushing efficiency of the cache device is improved.

In addition, based on the same concept of the above method embodiment, an embodiment of the present invention further provides a data flushing system of a cache device, which is used for implementing the above method of the present invention.

Referring to fig. 8, fig. 8 is a schematic structural diagram of a data flushing system of a cache device according to an embodiment of the present invention, and as shown in fig. 8, the data flushing system of the cache device includes:

the object extraction module 110 is configured to extract a data object according to an LRU queue of the cache device when the cache device needs to flush data;

the object sorting module 120 is configured to sort the data objects according to the logical block addresses of the data objects in the cache device;

and the object inserting module 130 is configured to sequentially insert the sorted data objects into a lower-flushing work queue of the cache device, and then flush the sorted data objects to the main memory device.

According to the data flushing system of the cache device, the data objects are extracted from the cache device according to the LRU queue of the cache device, then the data objects are arranged according to the logical block addresses of the data objects in the cache device, and the sorted data objects are sequentially inserted into the flushing work queue of the cache device, so that the data objects are flushed to the main storage device. Because the addressing mode CHS addressing of the main memory device addresses the data object according to the cylinder, the magnetic head and the sector of the main memory device, and the CHS addressing has a mapping relation with the logical block address of the cache device, the main memory device can quickly read the data object after the data object is sequenced in the logical block address of the cache device, the data writing speed of the cache device is positively correlated with the reading speed of the main memory device, and the storage space is released because the data object in the cache device is flushed, so the flushing speed of the cache device is greatly improved, and the reading and writing performance and the stability of the storage system are improved.

As a preferred embodiment, as shown in fig. 9, the object extracting module 110 includes:

a pointer obtaining submodule 111, configured to obtain a predetermined number of object pointers at the tail in the LRU queue;

and the object obtaining sub-module 112 is configured to extract data objects corresponding to a predetermined number of object pointers from the lower-brushing work queue.

As a preferred embodiment, as shown in fig. 10, the object sorting module 120 includes:

the address obtaining submodule 121 is configured to obtain a logical block address of the data object in a data logical interval of the cache device;

and the data sorting submodule 122 is used for sequentially sorting the data objects according to the increasing rule of the address linearity of the logic block.

As a preferred embodiment, as shown in fig. 11, the data flushing system of the above-mentioned cache device further includes:

and the pointer deleting module 140 is used for deleting the pointer of the data object from the LRU queue after the data object is flushed to the main storage device.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.