阅读说明：本技术 芯片组件及芯片封装方法 (Chip assembly and chip packaging method ) 是由 曹啸 于 2021-10-28 设计创作，主要内容包括：本发明提供一种芯片组件及芯片封装方法,其中芯片封装方法包括：在散热盖的底面形成浸润膜；在芯片本体的背面形成散热膜,所述浸润膜用于在通过助焊剂将散热盖与芯片本体焊接在一起时,与散热膜熔融接触在一起；在所述散热膜上涂布助焊剂；将助焊剂与浸润膜贴合；对所述芯片本体和散热盖进行焊接处理,以使所述芯片本体和散热盖通过所述浸润膜和散热膜结合在一起。本发明简化了芯片本体与散热盖封装的工艺流程,降低了芯片本体与散热盖封装的成本。(The invention provides a chip assembly and a chip packaging method, wherein the chip packaging method comprises the following steps: forming a wetting film on the bottom surface of the heat dissipation cover; forming a heat dissipation film on the back of the chip body, wherein the infiltration film is used for being in melting contact with the heat dissipation film when the heat dissipation cover and the chip body are welded together through soldering flux; coating soldering flux on the heat dissipation film; attaching the soldering flux to the infiltration film; and welding the chip body and the heat dissipation cover so as to combine the chip body and the heat dissipation cover together through the infiltration film and the heat dissipation film. The invention simplifies the process flow of packaging the chip body and the heat dissipation cover and reduces the packaging cost of the chip body and the heat dissipation cover.)

1. A method of chip packaging, comprising:

forming a wetting film on the bottom surface of the heat dissipation cover;

forming a heat dissipation film on the back of the chip body, wherein the infiltration film is used for being in melting contact with the heat dissipation film when the heat dissipation cover and the chip body are welded together through soldering flux;

coating soldering flux on the heat dissipation film;

attaching the soldering flux to the infiltration film;

and welding the chip body and the heat dissipation cover so as to combine the chip body and the heat dissipation cover together through the infiltration film and the heat dissipation film.

2. The chip packaging method according to claim 1, wherein the material of the wetting film comprises: indium or an indium alloy.

3. The chip packaging method according to claim 1, wherein the thickness of the wetting film is 10-400 μm.

4. The chip packaging method according to claim 1, wherein the material of the heat dissipation film comprises: aluminum, titanium, nickel, gold, vanadium, and indium.

5. The chip packaging method according to claim 1, wherein the thickness of the heat dissipation film is 0.4-2 nm.

6. The chip packaging method according to claim 1, wherein the weight of the flux is 0.1-1 mg.

7. The chip packaging method according to claim 1, wherein the ratio of the area of the wetting film to the area of the bonding surface of the chip body is 0.80-2.25;

the chip body bonding surface is a plane area where the chip body is used for being bonded with the heat dissipation cover;

the coverage rate of the heat dissipation film relative to the back surface of the chip body is not less than 0.995;

the coverage rate of the soldering flux relative to the back surface of the chip body is not less than 0.99.

8. A chip assembly, comprising: the chip comprises a chip body and a heat dissipation cover;

the surface of the heat dissipation cover facing the chip body is plated with a soaking film, and the surface of the chip body facing the heat dissipation cover is plated with a heat dissipation film;

the infiltration film is used for being in melting contact with the heat dissipation film when the heat dissipation cover and the chip body are welded together through the soldering flux;

the heat dissipation cover is welded with the chip body through the heat dissipation film and the infiltration film.

9. The chip assembly of claim 8, wherein the material of the wetting film comprises: indium;

the material of the heat dissipation film comprises: at least one of aluminum, titanium, nickel, gold, and indium.

10. The chip assembly according to claim 8 or 9, wherein the wetting film has a thickness of 10 to 400 μm;

the thickness of the heat dissipation film is 0.4-2 nanometers.

Technical Field

The invention relates to the technical field of chip packaging, in particular to a chip assembly and a chip packaging method.

Background

With the development of the microelectronic industry toward light weight, thin profile, miniaturization and function diversification, the packaging technology and the packaging material are two most important factors influencing the reliability of electronic packaging, and the factors promote and restrict each other.

In the semiconductor industry, high heat dissipation is also a concern when packaging high-end processors. In the existing flip chip packaging technology, pure gold is plated on the Back surface of a heat dissipation cover, and then a structure of soldering flux + preformed indium sheet + soldering flux is adopted on the Back surface of a chip with a BSM (Back Side Metal) to be attached to the Back surface of the heat dissipation cover so as to dissipate heat of the chip. However, the method for radiating the chip is high in radiating cost and complex in process flow, and the reliability of connection between the chip and the radiating cover through various metal interfaces is poor.

Disclosure of Invention

In order to solve the problems, according to the chip assembly and the chip packaging method provided by the invention, the infiltration film is plated on the surface of the heat dissipation cover, so that the heat dissipation cover is packaged with the chip through the infiltration film and the heat dissipation film, the process flow of packaging the chip body and the heat dissipation cover is simplified, and the cost of packaging the chip body and the heat dissipation cover is reduced.

In a first aspect, the present invention provides a chip packaging method, including:

forming a wetting film on the bottom surface of the heat dissipation cover;

forming a heat dissipation film on the back of the chip body, wherein the infiltration film is used for being in melting contact with the heat dissipation film when the heat dissipation cover and the chip body are welded together through soldering flux;

coating soldering flux on the heat dissipation film;

attaching the soldering flux to the infiltration film;

and welding the chip body and the heat dissipation cover so as to combine the chip body and the heat dissipation cover together through the infiltration film and the heat dissipation film.

Optionally, the material of the wetting film comprises: indium or an indium alloy.

Optionally, the thickness of the wetting film is 10-400 microns.

Optionally, the material of the heat dissipation film includes: aluminum, titanium, nickel, gold, vanadium, and indium.

Optionally, the thickness of the heat dissipation film is 0.4-2 nanometers.

Optionally, the weight of the flux is 0.1-1 mg.

Optionally, the ratio of the area of the infiltration film to the area of the chip body bonding surface is 0.80-2.25;

the chip body bonding surface is a plane area where the chip body is used for being bonded with the heat dissipation cover;

the coverage rate of the heat dissipation film relative to the back surface of the chip body is not less than 0.995;

the coverage rate of the soldering flux relative to the back surface of the chip body is not less than 0.99.

In a second aspect, the present invention provides a chip assembly comprising: the chip comprises a chip body and a heat dissipation cover;

the surface of the heat dissipation cover facing the chip body is plated with a soaking film, and the surface of the chip body facing the heat dissipation cover is plated with a heat dissipation film;

the infiltration film is used for being in melting contact with the heat dissipation film when the heat dissipation cover and the chip body are welded together through the soldering flux;

the heat dissipation cover is welded with the chip body through the heat dissipation film and the infiltration film.

Optionally, the material of the wetting film comprises: indium;

the material of the heat dissipation film comprises: at least one of aluminum, titanium, nickel, gold, and indium.

Optionally, the thickness of the infiltration film is 10-400 micrometers;

the thickness of the heat dissipation film is 0.4-2 nanometers.

According to the chip assembly and the chip packaging method provided by the embodiment of the invention, the infiltration film is plated on the surface of the heat dissipation cover, so that the heat dissipation cover is packaged with the chip through the infiltration film and the heat dissipation film, the process flow of packaging the chip body and the heat dissipation cover is simplified, the cost of packaging the chip body and the heat dissipation cover is reduced, the heat dissipation efficiency of the chip is improved, and the reliability of connection between the chip and the heat dissipation cover is improved.

Drawings

Fig. 1 is a bottom view of a heat dissipation cover according to an embodiment of the present application;

fig. 2a to 2g are schematic views of a packaged chip assembly according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a chip assembly according to an embodiment of the present application.

Reference numerals

1. A chip body; 11. a heat dissipating film; 2. a heat dissipation cover; 21. infiltrating a film; 3. a substrate; 4. soldering flux; 5. a melt interface; 6. and (7) sealing the glue.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It is to be noted that, in the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Example one

The present embodiment provides a chip assembly, which combines fig. 1, fig. 2f and fig. 2g, the chip assembly includes: chip body 1 and radiating cover 2.

The bottom surface of the heat dissipation cover 2 is provided with a storage tank, and the bottom surface of the storage tank is plated with a wetting film 21. The back of the substrate in the chip body 1 is positioned in the storage groove, and the back of the chip body 1 is plated with a heat dissipation film 11. The wetting film 21 is used for being in melting contact with the heat dissipation film 11 when the heat dissipation cover 2 and the chip body 1 are welded together through the soldering flux 4. The heat dissipation cover 2 is connected with the chip body 1 through the heat dissipation film 11 and the infiltration film 21.

In the embodiment, since the film plating process is performed on the contact portion of the back surface of the chip body 1 and the heat dissipation cover 2 and the contact portion of the bottom surface of the heat dissipation cover 2 and the chip body 1, the wetting angle between the formed liquid heat dissipation film 11 and the wetting film 21 will be smaller during the melting process, so that the wetting effect is better, the cracks or bubbles between the melting interfaces 5 can be effectively reduced or eliminated, and the heat dissipation performance and the long-term use reliability of the chip body 1 are improved.

The material of the wetting film 21 is a single material, the heat dissipation film 11 is a multi-layer multi-metal structure or a single-layer structure, and the material of the heat dissipation film 11 includes the material of the wetting film 21. The material of the infiltration film 21 comprises: indium or an indium alloy. In this embodiment, the material of the wetting film 21 is indium, and the material of the heat dissipation cover 2 is copper, but not limited thereto. The thickness of the wetting film 21 is 10-400 micrometers, and in the embodiment, the thickness of the wetting film 21 is 200 micrometers. The material of the heat dissipation film 11 includes: in this embodiment, the heat dissipation film 11 is a multi-layer multi-metal structure, and the material of the heat dissipation film 11 includes: aluminum, titanium and indium, and further, the material of each metal layer in the heat dissipation film is at least one metal of aluminum, titanium and indium, wherein the material of the metal layer farthest from the chip body 1 is the same as the material of the wetting film. The thickness of the heat dissipation film 11 is 0.4-2 nanometers, and in this embodiment, the thickness of the heat dissipation film 11 is 1.2 nanometers. Optionally, the material of the heat dissipation film 11 is the same as the material of the wetting film 21. In this optional embodiment, the material of the heat dissipation film 11 and the material of the heat dissipation film 11 are both indium, so that not only can the cost of the chip assembly be further reduced, but also the heat dissipation film 11 and the wetting film 21 are made of the same material, so that the effect of the melting contact between the heat dissipation film 11 and the wetting film 21 is better, the structure of the formed melting interface 5 is more stable, the heat conduction effect is better, the thickness is smaller, and the thickness of the chip assembly is saved.

The thickness of the melting interface 5 formed by melting the wetting film 21 and the heat dissipation film 11 is 150-250 micrometers, the specific thickness of the melting interface 5 is determined by the specific design structure of the chip assembly, the actual engineering capability and the like, and the embodiment is not particularly limited.

In this embodiment, the chip assembly further includes: a substrate 3. The heat dissipation cover 2 covers the chip body 1 on the upper surface of the substrate 3; the chip body 1 is inversely attached to the upper surface of the substrate 3; the bottom of the heat dissipation cover 2 is fixedly connected with the substrate 3 through a sealant 6 so as to cover the chip body 1 in the heat dissipation cover 2.

The chip assembly is characterized in that the infiltration film 21 is plated on the surface of the heat dissipation cover 2, so that the heat dissipation cover 2 is packaged with the chip through the infiltration film 21 and the heat dissipation film 11, the coating times of the soldering flux 4 are reduced, and the heat dissipation cover 2 can be combined with the chip body 1 only by coating a layer of the soldering flux 4 between the infiltration film 21 and the heat dissipation film 11, so that the packaging process of the chip body 1 and the heat dissipation cover 2 is simplified, the packaging cost of the chip body 1 and the heat dissipation cover 2 is reduced, the heat dissipation efficiency of the chip is improved, and the connection reliability between the chip and the heat dissipation cover 2 is improved.

Example two

The present embodiment provides a chip assembly, which is different from the chip assembly of the first embodiment in that the thickness of the wetting film 21 is 20 to 300 μm. When the thickness of the wetting film 21 is smaller than the threshold thickness, a preformed indium sheet is arranged between the heat dissipation cover 2 and the chip body 1, and two opposite surfaces of the preformed indium sheet are respectively fused with the wetting film 21 and the heat dissipation film 11 to combine the heat dissipation cover 2 and the chip body 1 together; when the thickness of the wetting film 21 is larger than the threshold thickness, the heat dissipation cover 2 and the chip body 1 are directly fused and combined together through the wetting film 21 and the heat dissipation film 11. In this embodiment, the threshold thickness is 200 microns.

EXAMPLE III

The present embodiment provides a chip packaging method, which can be used to package the chip assembly in the first embodiment with reference to fig. 2a to 2g and fig. 3. The chip packaging method comprises the following steps from S101 to S101:

step S101: a heat sink cover 2 is provided. The material of the heat dissipation cover 2 is copper.

Step S102: a wetting film 21 is formed on the bottom surface of the heat dissipation cover 2.

The wetting film 21 is used for being in melting contact with the heat dissipation film 11 when the heat dissipation cover 2 and the chip body 1 are welded together through the soldering flux 4. The thickness of the infiltration film 21 is 10-400 microns. The material of the infiltration film 21 comprises: indium, but is not limited thereto, and any Material satisfying TIM (Thermal Interface Material, Interface heat sink Material such as silicone grease, metal, etc.) may be used. In the present embodiment, the wetting film 21 is formed on the bottom surface of the heat dissipation cover 2 by a plating process, such as electroplating, PVD (physical vapor deposition), or the like.

Step S103: a chip body 1 is provided.

Step S104: a heat dissipation film 11 is formed on the back surface of the chip body 1.

The thickness of the heat dissipation film 11 is 0.4-2 nanometers. The coverage rate of the heat dissipation film 11 relative to the back surface of the chip body 1 is not less than 0.995. The material of the heat dissipation film 11 includes: at least one of aluminum, titanium, nickel, gold, and indium. In this embodiment, the material of the heat dissipation film 11 is indium. In the present embodiment, the heat dissipation film 11 is formed on the back surface of the chip body 1 by a plating process, such as electroplating, PVD (physical vapor deposition), or the like.

Step S105: and coating the soldering flux 4 on the heat dissipation film 11. The weight of the soldering flux 4 is 0.1-1 mg.

Step S106: the flux 4 is attached to the wetting film 21.

In the process of attaching the flux 4 to the wetting film 21, the geometric center of the wetting film 21 and the geometric center of the heat dissipation film 11 are overlapped on a horizontal plane. In the present embodiment, step S106 includes: providing a substrate 3; flip-chip mounting the chip body 1 on the substrate 3; and encapsulating the heat dissipation cover 2 on the substrate 3 to cover the chip body 1 in the heat dissipation cover 2, so that the heat dissipation film 11 is attached to the soaking film 21.

Step S107: and performing reflow soldering treatment on the chip body 1 and the heat dissipation cover 2 so as to combine the chip body 1 and the heat dissipation cover 2 together through the heat dissipation film 11 and the wetting film 21.

Steps S101 to S102 may be exchanged with steps S103 to S105. The ratio of the area of the infiltration film 21 to the area of the bonding surface of the chip body 1 is 0.80-2.25, and the bonding surface of the chip body 1 is a planar area where the chip body 1 is used for being bonded with the heat dissipation cover 2; the coverage rate of the soldering flux 4 relative to the back surface of the chip body 1 is not less than 0.99. The phenomenon of metal diffusion can be avoided by limiting the weight and the coverage rate of the soldering flux 4, so that the coverage rate of the melting interface 5 is insufficient, and the heat dissipation effect of the chip body can be influenced.

According to the chip packaging method, the infiltration film 21 is plated on the surface of the heat dissipation cover 2, so that the heat dissipation cover 2 is packaged with the chip through the infiltration film 21 and the heat dissipation film 11, the coating times of the soldering flux 4 are reduced, and the heat dissipation cover 2 and the chip body 1 can be combined only by coating a layer of the soldering flux 4 between the infiltration film 21 and the heat dissipation film 11, so that the packaging process of the chip body 1 and the heat dissipation cover 2 is simplified, the packaging cost of the chip body 1 and the heat dissipation cover 2 is reduced, the heat dissipation efficiency of the chip is improved, and the connection reliability between the chip and the heat dissipation cover 2 is improved.

Optionally, when the thickness of the wetting film 21 is smaller than the threshold thickness, before step S107, the chip packaging method in the third embodiment further includes: the threshold indium sheet is placed above the flux 4, so that the structural stability of the melting interface 5 and the good heat dissipation effect can be ensured, and meanwhile, the chip packaging method eliminates the gold plating mode on the surface of the heat dissipation cover 2 in the prior art, so that the manufacturing cost of the chip assembly formed by adopting the chip packaging method in the first embodiment or the second embodiment is reduced.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.