阅读说明：本技术 一种半导体测试结构及其形成方法 (Semiconductor test structure and forming method thereof ) 是由 张斯日古楞 于 2020-06-18 设计创作，主要内容包括：本申请提供一种半导体测试结构及其形成方法,所述半导体测试结构包括衬底,所述衬底上包括：第一接触结构；第一层内互连结构和第一层内辅助连接结构,所述第一层内互连结构和所述第一接触结构电连接,且所述第一层内辅助连接结构不与所述第一层内互连结构以及第一接触结构电连接；第二层内互连结构和第二层内辅助连接结构,所述第一层内互连结构与所述第二层内辅助连接结构电连接,所述第一层内辅助连接结构与所述第二层内互连结构电连接；第三层内互连结构,所述第三层内互连结构与所述第二层内互连结构和第二层内辅助连接结构电连接。可以同时实现半导体正面和背面的测试,并且芯片面积利用率较高。(The application provides a semiconductor test structure and a forming method thereof, wherein the semiconductor test structure comprises a substrate, and the substrate comprises: a first contact structure; a first intra-level interconnect structure and a first intra-level auxiliary connection structure, the first intra-level interconnect structure and the first contact structure being electrically connected, and the first intra-level auxiliary connection structure not being electrically connected with the first intra-level interconnect structure and the first contact structure; the first-layer interconnection structure is electrically connected with the second-layer auxiliary connection structure, and the first-layer auxiliary connection structure is electrically connected with the second-layer interconnection structure; a third intra-level interconnect structure electrically connected to the second intra-level interconnect structure and the second intra-level auxiliary connection structure. The testing of the front surface and the back surface of the semiconductor can be realized simultaneously, and the area utilization rate of the chip is higher.)

1. A semiconductor test structure comprising a substrate, the substrate comprising a first surface, the first surface comprising thereon:

a first contact structure;

a first intra-level interconnect structure and a first intra-level auxiliary connection structure, the first intra-level interconnect structure and the first contact structure being electrically connected, and the first intra-level auxiliary connection structure not being electrically connected with the first intra-level interconnect structure and the first contact structure;

the first-layer interconnection structure is electrically connected with the second-layer auxiliary connection structure, and the first-layer auxiliary connection structure is electrically connected with the second-layer interconnection structure;

a third intra-level interconnect structure electrically connected to the second intra-level interconnect structure and the second intra-level auxiliary connection structure.

2. The semiconductor test structure of claim 1, wherein the first intra-level interconnect structure and the second intra-level auxiliary connection structure are electrically connected through a first inter-level connection structure, and the first intra-level auxiliary connection structure and the second intra-level interconnect structure are electrically connected through the first inter-level connection structure.

3. The semiconductor test structure of claim 1, wherein the third intra-level interconnect structure is electrically connected to the second intra-level interconnect structure through a second inter-level connection structure, and the third intra-level interconnect structure is electrically connected to the second intra-level auxiliary connection structure through a second inter-level connection structure.

4. The semiconductor test structure of claim 1, wherein the substrate includes a second surface including a pad thereon, the pad being electrically connected to the first contact structure.

5. The semiconductor test structure of claim 4, wherein the bond pad is electrically connected to the first contact structure through a second contact structure that extends through the substrate.

6. The semiconductor test structure of claim 1, further comprising: the first insulating layer is positioned on the first surface of the substrate, and the first contact structure penetrates through the first insulating layer.

7. The semiconductor test structure of claim 6, wherein the first insulating layer is a stack of at least one insulating layer.

8. The semiconductor test structure of claim 7, wherein the first insulating layer comprises a silicon nitride layer and a silicon oxide layer, wherein the silicon nitride layer is on the first surface of the substrate and the silicon oxide layer is on the surface of the silicon nitride layer.

9. A method for forming a semiconductor test structure, comprising:

providing a substrate, the substrate comprising a first surface;

forming a first contact structure on the first surface;

forming a first intra-level interconnect structure and a first intra-level auxiliary connection structure on the first contact structure, the first intra-level interconnect structure and the first contact structure being electrically connected, and the first intra-level auxiliary connection structure not being electrically connected with the first intra-level interconnect structure and the first contact structure;

forming a second-layer interconnection structure and a second-layer auxiliary connection structure on the first-layer interconnection structure and the first-layer auxiliary connection structure, wherein the first-layer interconnection structure is electrically connected with the second-layer auxiliary connection structure, and the first-layer auxiliary connection structure is electrically connected with the second-layer interconnection structure;

and forming a third-layer inner interconnection structure on the second-layer inner interconnection structure and the second-layer auxiliary connection structure, wherein the third-layer inner interconnection structure is electrically connected with the second-layer inner interconnection structure and the second-layer auxiliary connection structure.

10. The method of forming a semiconductor test structure of claim 9, wherein the substrate includes a second surface, the method further comprising: and forming a welding pad on the second surface, wherein the welding pad is electrically connected with the first contact structure.

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to a semiconductor test structure and a method for forming the same.

Background

Wafer bonding and through silicon via interconnect processes are essential for 3D packaged memories and backside incident imaging chips. In order to monitor whether the electrical characteristics of the device are affected by bonding or other processes, it is usually necessary to perform electrical measurements on the front and back surfaces of the test unit.

However, the conventional test unit capable of simultaneously performing front and back tests has the problems of requiring a larger chip area, and the like, and therefore, a more effective and reliable technical solution is needed.

Disclosure of Invention

The application provides a semiconductor test structure and a forming method thereof, which can simultaneously realize the test of the front surface and the back surface of a semiconductor and have higher chip area utilization rate.

One aspect of the present application provides a semiconductor test structure comprising a substrate including a first surface comprising thereon: a first contact structure; a first intra-level interconnect structure and a first intra-level auxiliary connection structure, the first intra-level interconnect structure and the first contact structure being electrically connected, and the first intra-level auxiliary connection structure not being electrically connected with the first intra-level interconnect structure and the first contact structure; the first-layer interconnection structure is electrically connected with the second-layer auxiliary connection structure, and the first-layer auxiliary connection structure is electrically connected with the second-layer interconnection structure; a third intra-level interconnect structure electrically connected to the second intra-level interconnect structure and the second intra-level auxiliary connection structure.

In some embodiments of the present application, the first intra-layer interconnect structure and the second intra-layer auxiliary connection structure are electrically connected through a first inter-layer connection structure, and the first intra-layer auxiliary connection structure and the second intra-layer interconnect structure are electrically connected through a first inter-layer connection structure.

In some embodiments of the present application, the third intra-layer interconnect structure and the second intra-layer interconnect structure are electrically connected through a second interlayer connection structure, and the third intra-layer interconnect structure and the second intra-layer auxiliary connection structure are electrically connected through a second interlayer connection structure.

In some embodiments of the present application, the substrate includes a second surface including a pad thereon, the pad being electrically connected to the first contact structure.

In some embodiments of the present application, the pad is electrically connected to the first contact structure through a second contact structure that extends through the substrate.

In some embodiments of the present application, the semiconductor test structure further comprises: the first insulating layer is positioned on the first surface of the substrate, and the first contact structure penetrates through the first insulating layer.

In some embodiments of the present application, the first insulating layer is a stacked structure of at least one insulating layer.

In some embodiments of the present application, the first insulating layer includes a silicon nitride layer and a silicon oxide layer, wherein the silicon nitride layer is on the first surface of the substrate and the silicon oxide layer is on the surface of the silicon nitride layer.

Another aspect of the present application also provides a method for forming a semiconductor test structure, including: providing a substrate, the substrate comprising a first surface; forming a first contact structure on the first surface; forming a first intra-level interconnect structure and a first intra-level auxiliary connection structure on the first contact structure, the first intra-level interconnect structure and the first contact structure being electrically connected, and the first intra-level auxiliary connection structure not being electrically connected with the first intra-level interconnect structure and the first contact structure; forming a second-layer interconnection structure and a second-layer auxiliary connection structure on the first-layer interconnection structure and the first-layer auxiliary connection structure, wherein the first-layer interconnection structure is electrically connected with the second-layer auxiliary connection structure, and the first-layer auxiliary connection structure is electrically connected with the second-layer interconnection structure; and forming a third-layer inner interconnection structure on the second-layer inner interconnection structure and the second-layer auxiliary connection structure, wherein the third-layer inner interconnection structure is electrically connected with the second-layer inner interconnection structure and the second-layer auxiliary connection structure.

In some embodiments of the present application, the substrate includes a second surface, and the forming method further includes: and forming a welding pad on the second surface, wherein the welding pad is electrically connected with the first contact structure.

According to the semiconductor test structure and the forming method thereof, the unit to be tested can be subjected to front test through the interconnection structure in the second layer, then the unit to be tested is subjected to back test through the welding pad, the front and back tests of a semiconductor can be simultaneously realized, and the area utilization rate of a chip is high.

Drawings

The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:

FIG. 1 is a schematic diagram of a semiconductor test structure;

FIG. 2 is a schematic diagram of a semiconductor test structure according to an embodiment of the present application;

FIG. 3 is a top view of a first level interconnect structure and a first level auxiliary interconnect structure in a semiconductor test structure according to an embodiment of the present application;

FIG. 4 is a top view of an interconnect structure in a second level and an auxiliary interconnect structure in the second level in a semiconductor test structure according to an embodiment of the present application;

FIG. 5 is a top view of a third level of interconnect structures in a semiconductor test structure according to an embodiment of the present application.

Detailed Description

The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.

FIG. 1 is a schematic diagram of a semiconductor test structure 100.

Referring to fig. 1, the semiconductor test structure 100 includes a substrate 110, a contact structure 130, a first intra-layer interconnect structure 140, a first inter-layer connection structure 150, a second intra-layer interconnect structure 160, a second inter-layer connection structure 170, and a third intra-layer interconnect structure are sequentially formed on a surface of the substrate 110, and an insulating layer 120 is further formed on the surface of the substrate 110, and the insulating layer 120 electrically isolates the contact structure 130, the first intra-layer interconnect structure 140, the first inter-layer connection structure 150, the second intra-layer interconnect structure 160, the second inter-layer connection structure 170, and the third intra-layer interconnect structure 180.

The contact structure 130 is electrically connected to the first intra-layer interconnect structure 140, the first intra-layer interconnect structure 140 is electrically connected to the first inter-layer connection structure 150, the first inter-layer connection structure 150 is electrically connected to the second intra-layer interconnect structure 160, the second intra-layer interconnect structure 160 is electrically connected to the second inter-layer connection structure 170, and the second inter-layer connection structure 170 is electrically connected to the third intra-layer interconnect structure 180.

The units under test (not shown) in the semiconductor test structure 100 can be front tested through the third intra-level interconnect structure 180. However, the leakage path introduced by the contact structure 130 in the substrate 110 may interfere with the test structure and even cause the front side test to be impossible.

In order to be able to carry out the testing of the front and back sides of the unit to be tested, two sets of identical test units may be provided in some semiconductor test structures, one of which is provided with contact structures for back side testing and the other is not provided with contact structures for front side testing.

In other semiconductor test structures, one additional pad can be added for each pad for testing to serve as a back lead terminal to be provided with a contact structure, and after the front test is finished through the pads without the contact structures, two welding wires are electrically connected through a layer of metal connecting structure to be used for the back test.

However, as the number of layers of the wafer increases, the number of test units required to be formed into the through silicon vias increases. The through-silicon via wiring scheme described above will result in a reduced utilization of the scribe lane area. In order to improve the utilization rate of the area of a chip and realize the interconnection of silicon through holes under the condition of not increasing the area of a test unit, the application provides a semiconductor test structure.

Fig. 2 is a schematic diagram of a semiconductor test structure 200 according to an embodiment of the present application.

Embodiments of the present application provide a semiconductor test structure, and referring to fig. 2, the semiconductor test structure 200 includes a substrate 210, the substrate 210 includes a first surface (the first surface may be regarded as a front surface), and the first surface includes thereon: the first contact structure 230; a first intra-layer interconnect structure 240 and a first intra-layer auxiliary connection structure 241, the first intra-layer interconnect structure 240 and the first contact structure 230 being electrically connected, and the first intra-layer auxiliary connection structure 241 not being electrically connected with the first intra-layer interconnect structure 240 and the first contact structure 230, the first intra-layer auxiliary connection structure 241 being electrically connected with a unit to be tested (not shown in the figure) within the substrate; a second-layer interconnect structure 260 and a second-layer auxiliary connection structure 261, wherein the first-layer interconnect structure 240 is electrically connected to the second-layer auxiliary connection structure 261, and the first-layer auxiliary connection structure 241 is electrically connected to the second-layer interconnect structure 260; a third-layer internal interconnection structure 280, wherein the third-layer internal interconnection structure 280 is electrically connected with the second-layer internal interconnection structure 260 and the second-layer auxiliary connection structure 261.

After the second-layer interconnection structure 260 is formed, the front-side test is performed on the unit to be tested through the second-layer interconnection structure 260, and since the first-layer auxiliary connection structure 241 is not connected to the substrate 210, a leakage channel is not formed in the substrate 210, and the test is not disturbed. After the front test is completed, the second-layer interconnect structure 260 and the second-layer auxiliary interconnect structure 261 are electrically connected through the third-layer interconnect structure 280, so as to perform a back test. The semiconductor test structure can simultaneously realize the test of the front side and the back side of a semiconductor, and the area utilization rate of a chip is higher.

In some embodiments of the present application, the substrate 210 may include, but is not limited to, a semiconductor substrate and a corresponding semiconductor structure (e.g., a gate, a source, a drain, etc.) on the semiconductor substrate.

In some embodiments of the present application, the semiconductor test structure 200 further comprises: a first insulating layer 220 on the first surface of the substrate 210, wherein the first contact structure 230 penetrates through the first insulating layer 220. The first insulating layer 220 may electrically isolate adjacent first contact structures 230 from the substrate 210 and the first in-layer interconnect structure 240 and the first in-layer auxiliary connection structure 241.

In some embodiments of the present application, the first insulating layer 220 is a stacked structure of at least one insulating layer. In some embodiments of the present application, the first insulating layer 220 includes a silicon nitride layer 221 and a silicon oxide layer 222, wherein the silicon nitride layer 221 is located on the first surface of the substrate 210, and the silicon oxide layer 222 is located on the surface of the silicon nitride layer 221.

In other embodiments of the present application, the first insulating layer 220 may have other structures and include other suitable insulating materials, as long as the first insulating layer 220 can perform its electrical insulating function.

In some embodiments of the present application, the material of the first contact structure 230 includes copper or tungsten or aluminum, etc. In some embodiments of the present application, the first contact structures 230 are arranged in an array. The number and density of the first contact structures 230 can be designed according to actual needs.

In some embodiments of the present application, the first intra-layer interconnect structure 240 and the first intra-layer auxiliary connection structure 241 are located at the same layer. The first in-layer interconnect structure 240 and the first in-layer auxiliary connection structure 241 are electrically isolated by the second insulating layer 223.

In some embodiments of the present application, the first intra-layer interconnect structure 240 and the second intra-layer auxiliary connection structure 261 are electrically connected through a first inter-layer connection structure 250, and the first intra-layer auxiliary connection structure 241 and the second intra-layer interconnect structure 260 are electrically connected through the first inter-layer connection structure 250.

In some embodiments of the present application, the first interlayer connection structure 250 is, for example, a through silicon via.

Fig. 3 is a top view of a first intra-level interconnect structure 240 and a first intra-level auxiliary connection structure 241 in a semiconductor test structure according to an embodiment of the present application. The schematic diagram of the intra-first-layer interconnect structure 240 and the intra-first-layer auxiliary connection structure 241 shown in fig. 2 is a cross-sectional view taken along a dotted line in fig. 3. Fig. 4 is a top view of an interconnect structure 260 in a second layer and an auxiliary link structure 261 in the second layer in a semiconductor test structure according to an embodiment of the present application. The schematic diagram of the interconnect structure 260 in the second layer and the auxiliary link structure 261 in the second layer shown in fig. 2 is a cross-sectional view taken along a dotted line in fig. 4.

In some embodiments of the present application, the third intra-layer interconnect structure 280 and the second intra-layer interconnect structure 260 are electrically connected through a second inter-layer connection structure 251, and the third intra-layer interconnect structure 280 and the second intra-layer auxiliary connection structure 261 are electrically connected through the second inter-layer connection structure 251.

In some embodiments of the present application, the second-layer interconnect structure 260 and the second-layer auxiliary link structure 261 are located in the same layer. The second-layer interconnect structure 260 and the second-layer auxiliary link structure 261 are electrically isolated by the second insulating layer 223.

In some embodiments of the present application, the second interlayer connection structure 251 is, for example, a through silicon via.

FIG. 5 is a top view of a third level of interconnect structures 280 in a semiconductor test structure according to an embodiment of the present application. The schematic diagram of the third intra-level interconnect structure 280 shown in fig. 2 is a cross-sectional view taken along the dashed line in fig. 5.

The substrate 210 has a second insulating layer 223 formed on a first surface thereof, and the second insulating layer 223 is higher than the surface of the third intra-layer interconnect structure 280. The second insulating layer 223 may electrically isolate the adjacent first interlayer connection structures 250 and the adjacent second interlayer connection 251 structures. The second insulating layer 223 may also electrically isolate the first intra-layer interconnect structure 240, the second intra-layer interconnect structure 260, the third intra-layer interconnect structure 280, and the like of different layers.

In some embodiments of the present application, the material of the second insulating layer 223 may include a low-K material or an ultra-low-K material, such as silicon nitride, silicon oxide, silicon carbide, silicon oxycarbide, silicon oxynitride, organic siloxane polymers, fluorocarbons, and the like.

In some embodiments of the present application, the substrate 210 includes a second surface, the second surface includes a solder pad 290 thereon, and the solder pad 290 is electrically connected to the first contact structure 230. The pad 290 is electrically connected to the unit to be tested, and the back side of the unit to be tested can be tested through the pad 290.

In some embodiments of the present application, the solder pad 290 is electrically connected to the first contact structure 230 through a second contact structure 231, and the second contact structure 231 penetrates through the substrate 210.

In some embodiments of the present application, the material of the bonding pad 290 includes aluminum or copper.

In some embodiments of the present application, the sidewalls of the second contact structure 231 and the second surface of the substrate 210 are further formed with a third insulating layer 224. The third insulating layer 224 may electrically isolate the second contact structure 231 from the substrate 210. The material of the third insulating layer 224 is, for example, silicon nitride.

In some embodiments of the present application, a fourth insulating layer 225 is further formed on the surface of the third insulating layer 224, and the bonding pad 290 penetrates through the fourth insulating layer 225.

In some embodiments of the present application, the material of the fourth insulating layer 225 may include a low-K material or an ultra-low-K material, such as silicon nitride, silicon oxide, silicon carbide, silicon oxycarbide, silicon oxynitride, organosiloxane polymer, fluorocarbon, and the like.

The semiconductor test structure can carry out front test on the unit to be tested through the interconnection structure in the second layer, then the welding pad carries out back test on the unit to be tested, the front and back test of a semiconductor can be simultaneously realized, and the chip area utilization rate is higher.

Embodiments of the present application further provide a method for forming a semiconductor test structure, with reference to fig. 2, including: providing a substrate 210, the substrate 210 comprising a first surface; forming a first contact structure 230 on the first surface; forming a first intra-layer interconnect structure 240 and a first intra-layer auxiliary connection structure 241 on the first contact structure 230, the first intra-layer interconnect structure 240 and the first contact structure 230 being electrically connected, and the first intra-layer auxiliary connection structure 241 not being electrically connected with the first intra-layer interconnect structure 240 and the first contact structure 230; forming a second-layer interconnect structure 260 and a second-layer auxiliary connection structure 261 on the first-layer interconnect structure 240 and the first-layer auxiliary connection structure 241, wherein the first-layer interconnect structure 240 is electrically connected to the second-layer auxiliary connection structure 261, and the first-layer auxiliary connection structure 241 is electrically connected to the second-layer interconnect structure 260.

After the second-layer interconnection structure 260 is formed, the front-side test is performed on the unit to be tested through the second-layer interconnection structure 260, and since the first-layer auxiliary connection structure 241 is not connected to the substrate 210, a leakage channel is not formed in the substrate 210, and the test is not disturbed.

With continued reference to fig. 2, after the front test is completed, a third-layer interconnect structure 280 is formed on the second-layer interconnect structure 260 and the second-layer auxiliary interconnect structure 261, and the third-layer interconnect structure 280 is electrically connected to the second-layer interconnect structure 260 and the second-layer auxiliary interconnect structure 261. The second-layer interconnect structure 260 and the second-layer auxiliary connection structure 261 are electrically connected through the third-layer interconnect structure 280.

With continued reference to fig. 2, the substrate 210 includes a second surface on which a solder pad 290 is formed, the solder pad 290 being electrically connected to the first contact structure 230. The unit to be tested can be back tested through the pad 290.

In some embodiments of the present application, the method of forming a semiconductor test structure further comprises: a first insulating layer 220 is formed on the first surface of the substrate 210, and the first contact structure 230 penetrates through the first insulating layer 220.

In some embodiments of the present application, the method of forming a semiconductor test structure further comprises: a first inter-layer connection structure 250 is formed on the first intra-layer interconnect structure 240 and the first intra-layer auxiliary connection structure 241. The first intra-layer interconnect structure 240 and the second intra-layer auxiliary interconnect structure 261 are electrically connected through a first inter-layer connection structure 250, and the first intra-layer auxiliary connection structure 241 and the second intra-layer interconnect structure 260 are electrically connected through the first inter-layer connection structure 250.

In some embodiments of the present application, the method of forming a semiconductor test structure further comprises: a second interlayer connection structure 251 is formed on the second-layer interconnect structure 260 and the second-layer auxiliary connection structure 261. The third intra-layer interconnect structure 280 and the second intra-layer interconnect structure 260 are electrically connected through a second inter-layer connection structure 251, and the third intra-layer interconnect structure 280 and the second intra-layer auxiliary connection structure 261 are electrically connected through a second inter-layer connection structure 251.

In some embodiments of the present application, the method of forming a semiconductor test structure further comprises: a second contact structure 231 is formed on the second surface of the substrate 210. The bonding pad 290 is electrically connected to the first contact structure 230 through a second contact structure 231, and the second contact structure 231 penetrates through the substrate 210.

The forming method of the semiconductor test structure can simultaneously realize the test of the front side and the back side of the semiconductor, and the area utilization rate of a chip is high.

In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.

It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, as the terminology or phraseology of the present specification is to be interpreted by those skilled in the relevant art in light of the teachings of the present specification.

The term "high k" as used herein refers to a high dielectric constant. In the field of semiconductor device structures and fabrication processes, high-k refers to greater than SiO₂A dielectric constant of (e.g., greater than 3.9).

The term "low k" as used herein refers to a low dielectric constant. In the field of semiconductor device structures and fabrication processes, low-k refers to less than SiO₂A dielectric constant of (e.g., less than 3.9).

It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements.

It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.

Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.