阅读说明：本技术 打印头、液体喷出装置以及电容性负载驱动用集成电路装置 (Printhead, liquid ejecting apparatus, and integrated circuit device for driving capacitive load ) 是由 古川亮太 于 2021-03-25 设计创作，主要内容包括：本发明提供降低在驱动压电元件等电容性负载的集成电路装置中产生误动作的可能性的打印头、液体喷出装置以及电容性负载驱动用集成电路装置,切换是否向多个压电元件供给驱动信号的集成电路装置具有：切换是否向第一压电元件组供给驱动信号的第一电路块；切换是否向第二压电元件组供给驱动信号的第二电路块；切换是否向第三压电元件组供给驱动信号的第三电路块；用于根据从输入端子输入的信号进行动作,或者从输出端子输出信号的第四电路块；未设置电路元件的第一缓冲区域、第二缓冲区域以及第三缓冲区域,第一缓冲区域位于第一电路块与第四电路块之间,第二缓冲区域位于第二电路块与第四电路块之间,第三缓冲区域位于第三电路块与第四电路块之间。(The present invention provides a printhead, a liquid ejecting apparatus, and an integrated circuit device for driving a capacitive load, which reduce the possibility of malfunction in the integrated circuit device for driving the capacitive load such as a piezoelectric element, wherein the integrated circuit device for switching whether to supply a drive signal to a plurality of piezoelectric elements comprises: a first circuit block that switches whether or not to supply a drive signal to the first piezoelectric element group; a second circuit block that switches whether or not to supply a drive signal to the second piezoelectric element group; a third circuit block for switching whether or not to supply a drive signal to the third piezoelectric element group; a fourth circuit block for operating in accordance with a signal input from the input terminal or outputting a signal from the output terminal; the circuit includes a first buffer region, a second buffer region, and a third buffer region where circuit elements are not provided, the first buffer region being located between the first circuit block and the fourth circuit block, the second buffer region being located between the second circuit block and the fourth circuit block, and the third buffer region being located between the third circuit block and the fourth circuit block.)

1. A print head is provided with:

a plurality of piezoelectric elements driven by being supplied with a drive signal;

an integrated circuit device that switches whether or not to supply the drive signal to the plurality of piezoelectric elements; and

a wiring substrate which transmits the driving signal and is provided with the integrated circuit device,

the integrated circuit device has:

a first side;

a second edge located opposite the first edge;

a first terminal group located at a position along the first edge and electrically connected to a first piezoelectric element group including a first piezoelectric element of the plurality of piezoelectric elements;

a second terminal group located at a position along the second side and electrically connected to a second piezoelectric element group including a second piezoelectric element of the plurality of piezoelectric elements;

a third terminal group located at a position along the second side and electrically connected to a third piezoelectric element group including a third piezoelectric element of the plurality of piezoelectric elements;

a fourth terminal set along the second side between the second terminal set and the third terminal set and comprising an input terminal and an output terminal;

a first circuit block that switches whether or not the drive signal is supplied from the first terminal group to the first piezoelectric element group;

a second circuit block that switches whether or not the drive signal is supplied from the second terminal group to the second piezoelectric element group;

a third circuit block that switches whether or not the drive signal is supplied from the third terminal group to the third piezoelectric element group;

a fourth circuit block that operates in accordance with a signal input from the input terminal or outputs a signal from the output terminal; and

a first buffer region, a second buffer region and a third buffer region where no circuit element is provided,

the first buffer region is located between the first circuit block and the fourth circuit block,

the second buffer region is located between the second circuit block and the fourth circuit block,

the third buffer region is located between the third circuit block and the fourth circuit block.

2. The printhead of claim 1,

the integrated circuit device has:

a third side that intersects both the first side and the second side; and

a fourth edge intersecting both the first edge and the second edge and located opposite the third edge,

the first circuit block is located along the first edge,

the second circuit block, the third circuit block, and the fourth circuit block are located along the second side from the third side toward the fourth side in a position in which the second circuit block, the fourth circuit block, and the third circuit block are arranged in this order.

3. The printhead according to claim 1 or 2,

the fourth circuit block includes a residual vibration detection circuit that detects residual vibration generated after the drive signal is supplied to the plurality of piezoelectric elements.

4. A printhead according to any of claims 1 to 3,

the fourth circuit block includes a power-on reset circuit that resets an operation of the integrated circuit device in accordance with a voltage value of a power supply voltage supplied to the integrated circuit device.

5. A printhead according to any of claims 1 to 4,

the fourth circuit block includes an internal voltage generation circuit that outputs an internal voltage used inside the integrated circuit device.

6. A printhead according to any of claims 1 to 5,

the first circuit block includes: a switch circuit that switches whether or not the drive signal is supplied from the first terminal group to the first piezoelectric element group; and a switching control circuit that controls switching of the switching circuit,

the shortest distance between the switch circuit and the first side is shorter than the shortest distance between the switching control circuit and the first side.

7. The printhead of claim 6,

the shortest distance between the first circuit block and the fourth circuit block is shorter than the shortest distance between the second circuit block and the fourth circuit block.

8. A liquid ejecting apparatus includes:

a drive signal output circuit that outputs a drive signal; and

a print head that ejects liquid based on the drive signal,

the print head has:

a plurality of piezoelectric elements driven by being supplied with the drive signal;

an integrated circuit device that switches whether or not to supply the drive signal to the plurality of piezoelectric elements; and

a wiring substrate which transmits the driving signal and is provided with the integrated circuit device,

the integrated circuit device has:

a first side;

a second edge located opposite the first edge;

a first terminal group located at a position along the first edge and electrically connected to a first piezoelectric element group including a first piezoelectric element of the plurality of piezoelectric elements;

a second terminal group located at a position along the second side and electrically connected to a second piezoelectric element group including a second piezoelectric element of the plurality of piezoelectric elements;

a third terminal group located at a position along the second side and electrically connected to a third piezoelectric element group including a third piezoelectric element of the plurality of piezoelectric elements;

a fourth terminal set along the second side between the second terminal set and the third terminal set and comprising an input terminal and an output terminal;

a first circuit block that switches whether or not the drive signal is supplied from the first terminal group to the first piezoelectric element group;

a second circuit block that switches whether or not the drive signal is supplied from the second terminal group to the second piezoelectric element group;

a third circuit block that switches whether or not the drive signal is supplied from the third terminal group to the third piezoelectric element group;

a fourth circuit block that operates in accordance with a signal input from the input terminal or outputs a signal from the output terminal; and

a first buffer region, a second buffer region and a third buffer region where no circuit element is provided,

the first buffer region is located between the first circuit block and the fourth circuit block,

the second buffer region is located between the second circuit block and the fourth circuit block,

the third buffer region is located between the third circuit block and the fourth circuit block.

9. An integrated circuit device for driving a capacitive load, which controls driving of a plurality of capacitive loads driven by being supplied with a driving signal by switching whether or not to supply the driving signal to the plurality of capacitive loads, comprising:

a first side;

a second edge located opposite the first edge;

a first terminal set located along the first edge and electrically connected to a first capacitive load set comprising a first capacitive load of the plurality of capacitive loads;

a second terminal set located along the second side and electrically connected to a second capacitive load set including a second capacitive load of the plurality of capacitive loads;

a third terminal set located along the second edge and electrically connected with a third capacitive load set comprising a third capacitive load of the plurality of capacitive loads;

a fourth terminal set along the second side between the second terminal set and the third terminal set and comprising an input terminal and an output terminal;

a first circuit block that switches whether or not the drive signal is supplied from the first terminal group to the first capacitive load group;

a second circuit block that switches whether or not the drive signal is supplied from the second terminal group to the second capacitive load group;

a third circuit block that switches whether or not the drive signal is supplied from the third terminal group to the third capacitive load group;

a fourth circuit block that operates in accordance with a signal input from the input terminal or outputs a signal from the output terminal; and

a first buffer region, a second buffer region and a third buffer region where no circuit element is provided,

the first buffer region is located between the first circuit block and the fourth circuit block,

the second buffer region is located between the second circuit block and the fourth circuit block, and the third buffer region is located between the third circuit block and the fourth circuit block.

Technical Field

The present invention relates to a printhead, a liquid ejecting apparatus, and an integrated circuit device for driving a capacitive load.

Background

As an ink jet printer (liquid ejecting apparatus) that ejects ink as liquid to print an image or a document, an ink jet printer using a capacitive load such as a piezoelectric element is known. In such a liquid ejecting apparatus, the piezoelectric elements are provided in the print head that ejects the ink, in correspondence with the plurality of nozzles, respectively. Then, a drive signal is supplied to the piezoelectric element at a predetermined timing to drive the piezoelectric element, and a predetermined amount of ink is ejected from the corresponding nozzle in accordance with the driving of the piezoelectric element, thereby forming a desired image, document, or the like on the medium.

In such a liquid ejecting apparatus, the print head includes a large number of nozzles corresponding to the plurality of piezoelectric elements and an integrated circuit device that controls output of drive signals supplied to the plurality of piezoelectric elements. The number of terminals for outputting drive signals included in the integrated circuit device has increased with the recent increase in the number of nozzles included in the print head.

Patent document 1 discloses a technique for reducing the possibility of an increase in the size of a semiconductor device (integrated circuit device) even when the number of nozzles included in a print head is increased, the print head including the semiconductor device (integrated circuit device) for controlling the output of drive signals for ejecting ink from a plurality of nozzles.

[ Prior art documents ]

[ patent document ]

[ patent document 1] Japanese patent laid-open No. 2015-150844

In recent years, market demand for improvement in printing efficiency of liquid ejecting apparatuses has been met by increasing the ejection amount of ink ejected from a print head. However, in order to increase the ejection amount of ink ejected from the print head, a large current needs to be supplied to a capacitive load such as a piezoelectric element, and thus a large current is supplied to the integrated circuit device. When the amount of current supplied to the integrated circuit device increases, noise components due to the current increase, and as a result, malfunction may occur in the integrated circuit device. However, there is no description in patent document 1 of malfunctions of an integrated circuit device that may occur due to market demands for improvement in printing efficiency, and there is still room for improvement.

Disclosure of Invention

One embodiment of a print head according to the present invention includes:

a plurality of piezoelectric elements driven by being supplied with a drive signal;

an integrated circuit device that switches whether or not to supply the drive signal to the plurality of piezoelectric elements; and

a wiring substrate which transmits the driving signal and is provided with the integrated circuit device,

the integrated circuit device has:

a first side;

a second edge located opposite the first edge;

a first terminal group located at a position along the first edge and electrically connected to a first piezoelectric element group including a first piezoelectric element of the plurality of piezoelectric elements;

a second terminal group located at a position along the second side and electrically connected to a second piezoelectric element group including a second piezoelectric element of the plurality of piezoelectric elements;

a third terminal group located at a position along the second side and electrically connected to a third piezoelectric element group including a third piezoelectric element of the plurality of piezoelectric elements;

a fourth terminal set along the second side between the second terminal set and the third terminal set and comprising an input terminal and an output terminal;

a first circuit block that switches whether or not the drive signal is supplied from the first terminal group to the first piezoelectric element group;

a second circuit block that switches whether or not the drive signal is supplied from the second terminal group to the second piezoelectric element group;

a third circuit block that switches whether or not the drive signal is supplied from the third terminal group to the third piezoelectric element group;

a fourth circuit block that operates in accordance with a signal input from the input terminal or outputs a signal from the output terminal; and

a first buffer region, a second buffer region and a third buffer region where no circuit element is provided,

the first buffer region is located between the first circuit block and the fourth circuit block,

the second buffer region is located between the second circuit block and the fourth circuit block,

the third buffer region is located between the third circuit block and the fourth circuit block.

One aspect of the liquid ejecting apparatus according to the present invention includes:

a drive signal output circuit that outputs a drive signal; and

a print head that ejects liquid based on the drive signal,

the print head has:

a plurality of piezoelectric elements driven by being supplied with the drive signal;

an integrated circuit device that switches whether or not to supply the drive signal to the plurality of piezoelectric elements; and

a wiring substrate which transmits the driving signal and is provided with the integrated circuit device,

the integrated circuit device has:

a first side;

a second edge located opposite the first edge;

a first terminal group located at a position along the first edge and electrically connected to a first piezoelectric element group including a first piezoelectric element of the plurality of piezoelectric elements;

a second terminal group located at a position along the second side and electrically connected to a second piezoelectric element group including a second piezoelectric element of the plurality of piezoelectric elements;

a third terminal group located at a position along the second side and electrically connected to a third piezoelectric element group including a third piezoelectric element of the plurality of piezoelectric elements;

a fourth terminal set along the second side between the second terminal set and the third terminal set and comprising an input terminal and an output terminal;

a first circuit block that switches whether or not the drive signal is supplied from the first terminal group to the first piezoelectric element group;

a second circuit block that switches whether or not the drive signal is supplied from the second terminal group to the second piezoelectric element group;

a third circuit block that switches whether or not the drive signal is supplied from the third terminal group to the third piezoelectric element group;

a fourth circuit block that operates in accordance with a signal input from the input terminal or outputs a signal from the output terminal; and

a first buffer region, a second buffer region and a third buffer region where no circuit element is provided,

the first buffer region is located between the first circuit block and the fourth circuit block,

the second buffer region is located between the second circuit block and the fourth circuit block,

the third buffer region is located between the third circuit block and the fourth circuit block.

In one embodiment of the capacitive load driving integrated circuit device according to the present invention,

the integrated circuit device for driving a capacitive load controls driving of a plurality of capacitive loads driven by supply of a driving signal by switching whether or not to supply the driving signal to the plurality of capacitive loads, and includes:

a first side;

a second edge located opposite the first edge;

a first terminal set located along the first edge and electrically connected to a first capacitive load set comprising a first capacitive load of the plurality of capacitive loads;

a second terminal set located along the second side and electrically connected to a second capacitive load set including a second capacitive load of the plurality of capacitive loads;

a third terminal set located along the second edge and electrically connected with a third capacitive load set comprising a third capacitive load of the plurality of capacitive loads;

a fourth terminal set along the second side between the second terminal set and the third terminal set and comprising an input terminal and an output terminal;

a first circuit block that switches whether or not the drive signal is supplied from the first terminal group to the first capacitive load group;

a second circuit block that switches whether or not the drive signal is supplied from the second terminal group to the second capacitive load group;

a third circuit block that switches whether or not the drive signal is supplied from the third terminal group to the third capacitive load group;

a fourth circuit block that operates in accordance with a signal input from the input terminal or outputs a signal from the output terminal; and

a first buffer region, a second buffer region and a third buffer region where no circuit element is provided,

the first buffer region is located between the first circuit block and the fourth circuit block,

the second buffer region is located between the second circuit block and the fourth circuit block,

the third buffer region is located between the third circuit block and the fourth circuit block.

Drawings

Fig. 1 is a diagram showing a schematic configuration of a liquid ejecting apparatus.

Fig. 2 is a diagram showing a functional configuration of the liquid ejecting apparatus.

Fig. 3 is a diagram showing a schematic configuration of the ejection section.

Fig. 4 is a diagram showing a circuit configuration of the drive signal selection control circuit.

Fig. 5 is a diagram showing an electrical configuration of the selection control circuit.

Fig. 6 is a diagram showing the content of decoding performed by the decoder.

Fig. 7 is a diagram for explaining the operation of the selection control circuit in the unit operation period.

Fig. 8 is a diagram showing an example of the waveform of the drive signal Vin.

Fig. 9 is a diagram showing the electrical configuration of the switching circuit and the residual signal detection circuit.

Fig. 10 is a diagram showing an electrical configuration of the residual vibration detection circuit.

Fig. 11 is a diagram for explaining an operation of the periodic signal generating unit.

Fig. 12 is a diagram showing an example of the arrangement of internal circuits in an integrated circuit.

Fig. 13 is a diagram showing an example of the terminal arrangement of the integrated circuit.

[ description of reference numerals ]

1: a liquid ejecting device; 2: a liquid container; 10: a control mechanism; 20: a bracket; 21: a print head; 30: a moving mechanism; 31: a bracket motor; 32: an endless belt; 40: a conveying mechanism; 41: a conveying motor; 42: a conveying roller; 50: a drive circuit; 50 a: a drive signal output circuit; 50 b: a reference voltage signal output circuit; 51: a selection control circuit; 52: a residual vibration detection circuit; 53: a switching circuit; 57: a waveform shaping unit; 58: a periodic signal generation unit; 60: a piezoelectric element; 90: a linear encoder; 91: a notification mechanism; 92: an input section; 100: a control circuit; 110: a power supply circuit; 190: a cable; 200: a drive signal selection control circuit; 201: an integrated circuit; 202. 203, 204, 205: an edge; 206: a circuit mounting surface; 207: a terminal mounting surface; 210: FPC; 310: a circuit block; 311. 312, 313, 314: a circuit mounting area; 320: a circuit block; 321. 322, 323, 324: a circuit mounting area; 330: a circuit block; 331. 332, 333, 334: a circuit mounting area; 340: a circuit block; 341. 342, 343, 344: a terminal; 600: a discharge section; 601: a piezoelectric body; 611. 612: an electrode; 621: a vibrating plate; 627: a fixed part; 631: a chamber; 632: a nozzle plate; 641: a reservoir; 649: an island portion; 651: a nozzle; 661: an ink supply port; AB: an analog circuit region; BS1, BS2, BS 3: a buffer region; DC: a decoder; IO: an input-output circuit; LT: a latch circuit; OTN: an output end; p: a medium; SR: a shift register; TG, TGa, TGb, TGc: a transmission gate; u: and (6) switching a switch.

Detailed Description

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The drawings are used for ease of illustration. The embodiments described below are not intended to unduly limit the scope of the present invention set forth in the claims. All the configurations described below are not limited to the essential components of the present invention.

1. Outline of liquid ejecting apparatus

Fig. 1 is a diagram showing a schematic configuration of a liquid ejecting apparatus 1. The liquid discharge apparatus 1 is an ink jet printer of a serial printing system that forms an image on a medium P by reciprocating a carriage 20 on which a print head 21 that discharges ink as an example of liquid is mounted, and discharges the ink onto the medium P that is conveyed. In the following description, the direction in which the carriage 20 reciprocates is referred to as the X direction, the direction in which the medium P is conveyed is referred to as the Y direction, and the direction in which ink is ejected is referred to as the Z direction. The X direction, the Y direction, and the Z direction are described as directions orthogonal to each other, but the directions are not limited to those in which various structures constituting the liquid discharge apparatus 1 are provided orthogonally. As the medium P, any printing object such as printing paper, resin film, fabric, or the like can be used. In the following description, a direction along the Y direction in which the medium P is conveyed is referred to as a conveyance direction, a direction intersecting the conveyance direction in which the medium P is conveyed and along the X direction in which the carriage 20 reciprocates to scan the medium P is referred to as a main scanning direction, and a direction intersecting both the conveyance direction and the main scanning direction and along the Z direction in which ink is ejected onto the medium P is referred to as an ejection direction.

The liquid ejecting apparatus 1 includes a liquid container 2, a control mechanism 10, a carriage 20, a moving mechanism 30, and a conveying mechanism 40.

The liquid container 2 stores a plurality of kinds of ink discharged to the medium P. Examples of the color of the ink stored in the liquid container 2 include black, cyan, magenta, yellow, red, and gray. As the liquid container 2 storing ink, an ink cartridge, a bag-shaped ink pack formed of a flexible film, an ink tank capable of replenishing ink, and the like can be used.

The control means 10 includes a Processing circuit such as a CPU (Central Processing Unit) or an FPGA (Field Programmable Gate Array) and a memory circuit such as a semiconductor memory, and controls each element of the liquid ejecting apparatus 1.

A print head 21 is mounted on the carriage 20. The carriage 20 is fixed to an endless belt 32 included in the moving mechanism 30. The liquid container 2 may be mounted on the bracket 20.

The control signal Ctrl-H for controlling the print head 21 and one or more drive signals COM for driving the print head 21, which are output by the control mechanism 10, are input to the print head 21. Then, the print head 21 ejects the ink supplied from the liquid tank 2 in the Z direction, which is an ejection direction, based on the control signal Ctrl-H and the drive signal COM.

The moving mechanism 30 includes a carriage motor 31 and an endless belt 32. The carriage motor 31 operates based on a control signal Ctrl-C input from the control mechanism 10. The endless belt 32 rotates in accordance with the operation of the carriage motor 31. Thereby, the carriage 20 fixed to the endless belt 32 reciprocates in the X direction.

The conveying mechanism 40 includes a conveying motor 41 and a conveying roller 42. The conveyance motor 41 operates based on a control signal Ctrl-T input from the control mechanism 10. The conveying roller 42 rotates in accordance with the operation of the conveying motor 41. With the rotation of the conveying roller 42, the medium P is conveyed along the Y direction as the conveying direction.

As described above, the liquid discharge apparatus 1 discharges ink from the print head 21 mounted on the carriage 20 in conjunction with the conveyance of the medium P by the conveyance mechanism 40 and the reciprocating movement of the carriage 20 by the movement mechanism 30, and thereby discharges ink to an arbitrary position on the surface of the medium P to form a desired image on the medium P.

2. Functional structure of liquid ejecting apparatus

Fig. 2 is a diagram showing a functional configuration of the liquid discharge apparatus 1. The liquid ejecting apparatus 1 includes a control mechanism 10, a print head 21, a carriage motor 31, a conveyance motor 41, a linear encoder 90, a notification mechanism 91, an input unit 92, and a cable 190.

The cable 190 electrically connects the control mechanism 10 and the print head 21, and transmits various signals transmitted between the control mechanism 10 and the print head 21. Here, as described above, the print head 21 is mounted on the carriage 20 and reciprocates in the X direction. As such a Cable 190, a Flexible Flat Cable (FFC) or the like in which a plurality of signal lines are arranged substantially in parallel with an insulator layer interposed therebetween may be used.

The input section 92 includes a switch, not shown in the drawings, for a user to operate the liquid ejection device 1. Then, the user inputs various commands for operating the liquid ejection device 1 to the input unit 92 via the switch. The command input to the input unit 92 is input to the control mechanism 10. Information indicating the state of the liquid discharge apparatus 1 is input from the control means 10 to the notification means 91. The notification unit 91 notifies the user of information indicating the state of the liquid discharge apparatus 1 based on the input information. The notification means 91 may be, for example, a liquid crystal panel or a display lamp using an LED or an incandescent lamp. The notification mechanism 91 may notify the user by sound or vibration. Here, the input unit 92 and the notification mechanism 91 may be integrally formed as a touch panel or the like.

The control mechanism 10 includes a drive circuit 50, a control circuit 100, and a power supply circuit 110. The control circuit 100 includes, for example, a processor such as a microcontroller. The control circuit 100 generates and outputs data or various signals for controlling the liquid ejection apparatus 1 based on various signals such as image data input from a host computer, the input unit 92, and the like.

The operation of the control circuit 100 will be specifically described. The control circuit 100 grasps the scanning position of the print head 21 based on the detection signal input from the linear encoder 90. Then, the control circuit 100 generates and outputs various signals corresponding to the scanning position of the print head 21. Specifically, the control circuit 100 generates a control signal Ctrl-C for controlling the reciprocating movement of the print head 21 mounted on the carriage 20, and outputs the control signal Ctrl-C to the carriage motor 31. Further, the control circuit 100 generates a control signal Ctrl-T for controlling the conveyance of the medium P, and outputs the control signal Ctrl-T to the conveyance motor 41. The control signal Ctrl-C may be converted by a drive circuit not shown in the figure and then input to the carriage motor 31, and similarly, the control signal Ctrl-T may be converted by a drive circuit not shown in the figure and input to the conveyance motor 41.

The control circuit 100 outputs a drive control signal dA as a digital signal to the drive circuit 50.

The drive circuit 50 includes a drive signal output circuit 50a and a reference voltage signal output circuit 50 b. The drive control signal dA is input to the drive signal output circuit 50 a. The drive signal output circuit 50a performs digital/analog signal conversion on the drive control signal dA, and then performs D-class amplification on the converted analog signal to generate the drive signal COM. That is, the drive control signal dA is a digital signal that defines the waveform of the drive signal COM, and the drive signal output circuit 50a generates the drive signal COM by performing D-class amplification on the waveform defined by the drive control signal dA and outputs the drive signal COM to the print head 21. Therefore, the drive control signal dA may be an analog signal as long as it can define the waveform of the drive signal COM. The drive signal output circuit 50a may be a class a amplifier circuit, a class B amplifier circuit, or an AB amplifier circuit, as long as it can amplify a waveform defined by the drive control signal dA.

The reference voltage signal output circuit 50b generates a reference voltage signal VBS indicating the reference potential of the drive signal COM and outputs it to the print head 21. The reference voltage signal VBS may be, for example, a signal of a ground potential having a voltage value of 0V, or may be a signal of a dc voltage having a voltage value of 5.5V, 6V, or the like.

The power supply circuit 110 generates voltages VHV, VDD and a ground signal GND. The voltage VHV is a signal of a dc voltage having a voltage value of, for example, 42V. The voltage VDD is a signal of a dc voltage having a voltage value of, for example, 3.3V. The ground signal GND is a signal indicating the reference potential of the voltages VHV and VDD, and is a signal of a ground potential having a voltage value of 0V, for example. The voltage VHV is used for an amplification voltage and the like in the drive signal output circuit 50a, and the voltage VDD is used for a power supply voltage, a control voltage and the like of various configurations in the control mechanism 10. Further, the voltages VHV, VDD and the ground signal GND are also output to the print head 21. The voltage values of the voltages VHV, VDD and the ground signal GND are not limited to 42V, 3.3V and 0V. The power supply circuit 110 may generate and output signals having a plurality of voltage values other than the voltages VHV and VDD and the ground signal GND.

The control circuit 100 generates a print data signal SI, a conversion signal CH, a latch signal LAT, a clock signal SCK, and a switching control signal Sw as control signals Ctrl-H for controlling the print head 21 based on various signals such as image data input from the host computer, the scanning position of the print head 21 detected by the linear encoder 90, and the like, and outputs the print data signal SI, the conversion signal CH, the latch signal LAT, the clock signal SCK, and the switching control signal Sw to the print head 21.

The print head 21 includes a drive signal selection control circuit 200 and a plurality of ejection portions 600.

The drive signal selection control circuit 200 receives voltages VHV and VDD, a drive signal COM, a print data signal SI, a clock signal SCK, a latch signal LAT, a switching signal CH, and a switching control signal Sw. The voltages VHV and VDD function as a power supply voltage and a control voltage of the drive signal selection control circuit 200. Then, the drive signal selection control circuit 200 generates the drive signal Vin by selecting or not selecting the voltage waveform included in the drive signal COM based on the input print data signal SI, the clock signal SCK, the latch signal LAT, the switching signal CH, and the switching control signal Sw, and supplies the drive signal Vin to one end of the piezoelectric element 60 included in the corresponding ejection section 600. The reference voltage signal VBS is supplied to the other end of the piezoelectric element 60. Then, the piezoelectric element 60 is driven by the potential difference between the driving signal Vin and the reference voltage signal VBS. Ink is ejected from the ejection section 600 by an amount corresponding to the driving of the piezoelectric element 60.

The residual vibration Vout generated after the piezoelectric element 60 is driven by the supply of the drive signal Vin is input to the drive signal selection control circuit 200. Then, the drive signal selection control circuit 200 generates a residual vibration signal NVT corresponding to the residual vibration Vout and outputs the residual vibration signal NVT to the control circuit 100. The details of the drive signal selection control circuit 200 will be described later.

Here, an example of the structure of the discharge section 600 will be described with reference to fig. 3. Fig. 3 is a diagram showing a schematic configuration of the ejection section 600. As shown in fig. 3, the ejection section 600 includes a piezoelectric element 60, a vibration plate 621, a chamber 631, and a nozzle 651.

The piezoelectric element 60 is a laminated piezoelectric vibrator in which electrodes 611 and 612 are laminated with a piezoelectric body 601 interposed therebetween and are cut into a long and thin comb-like shape. The drive signal Vin is supplied from the drive signal selection control circuit 200 to the electrode 611. In addition, the electrode 612 is supplied with a reference voltage signal VBS. Then, the piezoelectric element 60 is driven in accordance with the potential difference between the driving signal Vin supplied to the electrode 611 and the reference voltage signal VBS supplied to the electrode 612. Specifically, the piezoelectric element 60 is displaced in the vertical direction shown in fig. 3 and in the longitudinal direction of the piezoelectric element 60. That is, the piezoelectric element 60 in the present embodiment is a so-called longitudinal vibration type piezoelectric vibrator. The fixed end portion of the piezoelectric element 60 is joined to the fixed portion 627, and the free end portion of the piezoelectric element 60 protrudes outward beyond the front end edge of the fixed portion 627. That is, in the ejection section 600, the piezoelectric element 60 is provided in a state of a so-called cantilever beam. The tip end surface of the free end portion of the piezoelectric element 60 is joined to an island 649 provided above the vibration plate 621.

The vibration plate 621 is located below the island 649 in fig. 3. The vibration plate 621 deforms in accordance with the displacement of the piezoelectric element 60 provided with the island 649 interposed therebetween. Further, a chamber 631 is provided below the vibration plate 621. That is, the vibration plate 621 functions as a diaphragm that expands and contracts the internal volume of the chamber 631 by being deformed in accordance with the displacement of the piezoelectric element 60. The chamber 631 is filled with ink supplied through the ink supply port 661 and the reservoir 641. The nozzle 651 is formed on the nozzle plate 632, and is an aperture portion communicating with the chamber 631.

In the discharge unit 600 configured as described above, the vibration plate 621 deforms according to the displacement of the piezoelectric element 60, and the internal volume of the chamber 631 changes according to the deformation of the vibration plate 621. As a result, the internal pressure of the chamber 631 changes, and the ink stored in the chamber 631 is ejected from the nozzle 651.

Here, the drive signal selection control circuit 200 is mounted on an integrated circuit 201. Further, as shown in fig. 3, an integrated circuit 201 mounted with a drive signal selection control circuit 200 is provided on an FPC (Flexible Printed Circuits) 210. That is, the integrated circuit 201 mounted with the drive signal selection control circuit 200 switches whether or not to supply the drive signal COM to the piezoelectric element 60 as the drive signal Vin. The integrated circuit 201 is an example of an integrated circuit device, and more specifically, is an example of a capacitive load driving integrated circuit device that drives the piezoelectric element 60, which is an example of a capacitive load. Further, the FPC210 transmits a drive signal COM input to the drive signal selection control circuit 200 mounted on the integrated circuit 201 and a drive signal Vin output from the drive signal selection control circuit 200. The FPC210 to which the integrated circuit 201 is provided and to which the driving signal COM and the driving signal Vin are transmitted is an example of a wiring substrate.

3. Circuit structure of drive signal selection control circuit

Next, the circuit configuration and operation of the drive signal selection control circuit 200 will be described. Fig. 4 is a diagram showing a circuit configuration of the drive signal selection control circuit 200. The drive signal selection control circuit 200 includes a selection control circuit 51, a residual vibration detection circuit 52, and a switching circuit 53.

The selection control circuit 51 is input with a clock signal SCK, a print data signal SI, a latch signal LAT, a conversion signal CH, and a drive signal COM output from the drive signal output circuit 50 a. Then, the selection control circuit 51 generates a drive signal Vin based on the clock signal SCK, the print data signal SI, the latch signal LAT, and the conversion signal CH and the drive signal COM, and outputs the drive signal Vin to the switching circuit 53. Specifically, the selection control circuit 51 generates the drive signal Vin based on the signal waveform included in the selection or non-selection drive signal COM based on the clock signal SCK, the print data signal SI, the latch signal LAT, and the conversion signal CH, and supplies the drive signal Vin to the piezoelectric element 60 included in the corresponding ejection section 600. Here, the drive signal COM output by the drive signal output circuit 50a is an example of a drive signal. The drive signal Vin generated by the drive signal selection control circuit 200 selecting or unselecting the signal waveform included in the drive signal COM is also an example of the drive signal.

The switching circuit 53 performs switching based on the switching control signal Sw to supply the driving signal Vin to the corresponding piezoelectric element 60 or to supply the residual vibration Vout generated in the piezoelectric element 60 to the residual vibration detection circuit 52 after supplying the driving signal Vin to the piezoelectric element 60. In other words, the switching circuit 53 switches between electrically connecting the corresponding piezoelectric element 60 to the selection control circuit 51 and electrically connecting the piezoelectric element 60 to the residual vibration detection circuit 52.

The residual vibration detection circuit 52 detects the input residual vibration Vout. Then, the residual vibration detection circuit 52 generates a residual vibration signal NVT based on the detected residual vibration Vout, and outputs the signal to the control circuit 100. In other words, the residual vibration detection circuit 52 generates the residual vibration signal NVT based on the residual vibration Vout generated by the driving of the piezoelectric element 60.

First, a specific example of the configuration and operation of the selection control circuit 51 will be described with reference to fig. 5 to 8. Fig. 5 is a diagram showing an electrical configuration of the selection control circuit 51. As shown in fig. 5, the selection control circuit 51 has M groups of shift registers SR, latch circuits LT, decoders DC, and transfer gates TG so as to correspond to the M ejection sections 600. In the following description, each element of the M groups may be referred to as 1-stage, 2-stage, … …, and M-stage in order from the top in fig. 5. In the following description, the shift registers SR corresponding to the 1-stage, 2-stage, … …, and M-stage may be referred to as shift registers SR [1], SR [2], … …, and SR [ M ], the latch circuits LT, LT [2], … …, and LT [ M ], the decoders DC, DC [1], DC [2], … …, and DC [ M ], the transmission gates TG [1], the transmission gates TG [2], … …, and the transmission gates TG [ M ], and the driving signals Vin, Vin [1], Vin [2], … …, and Vin [ M ].

The selection control circuit 51 is supplied with a clock signal SCK, a print data signal SI, a latch signal LAT, a conversion signal CH, and a drive signal COM. Here, details will be described later, but as shown in fig. 5, the drive signal COM in the present embodiment includes three drive signals COM-A, Com-B, Com-C.

The print data signal SI is a digital signal that defines the amount of ink ejected from the corresponding nozzle 651 when 1 dot (dot) of an image is formed. Specifically, the print data signal SI includes 3-bit print data [ b1, b2, b3], and the amount of ink ejected from the nozzles 651 is defined by the print data [ b1, b2, b3 ]. The print data signal SI is input to the selection control circuit 51 as a serial signal synchronized with the clock signal SCK. The selection control circuit 51 generates a drive signal Vin corresponding to the amount of ink discharged from the nozzles 651 based on the input print data signal SI. Then, the driving signal Vin outputted from the selection control circuit 51 is supplied to the corresponding piezoelectric element 60, whereby 4-gradation ink for expressing non-recording, small dots, middle dots, and large dots is ejected from the nozzle 651. The selection control circuit 51 generates a drive signal Vin for inspection for inspecting the state of the discharge unit 600 based on the print data signal SI input thereto, and outputs the drive signal Vin to the corresponding discharge unit 600.

The shift register SR temporarily holds the print data signal SI for each of the 3-bit information corresponding to the ejection section 600, and sequentially transfers the print data signal SI to the shift register SR at the subsequent stage in accordance with the clock signal SCK. Specifically, M shift registers SR corresponding to the M ejection units 600 are cascade-connected. The print data signal SI supplied in series is sequentially transferred to the shift register SR at the subsequent stage in accordance with the clock signal SCK. Then, at the time when the print data signal SI is transmitted to all of the M shift registers SR, the supply of the clock signal SCK is stopped. Thus, the print data [ b1, b2, b3] corresponding to the M ejection sections 600 are held in the M shift registers SR, respectively.

The M latch circuits LT latch 3-bit print data [ b1, b2, b3] held by the M shift registers SR, respectively, all at once in synchronization with the rise of the latch signal LAT, respectively. Here, SI [1] to SI [ M ] shown in FIG. 5 are held by M shift registers SR [1] to SR [ M ], respectively, and represent M print data [ b1, b2, b3] latched by corresponding latch circuits LT [1] to LT [ M ].

Here, the operation period in which the liquid ejecting apparatus 1 performs printing includes a plurality of unit operation periods Tu. Each unit operation period Tu includes a control period Ts1 and a subsequent control period Ts 2. The plurality of unit operation periods Tu include a unit operation period Tu during which the printing process is executed, a unit operation period Tu during which the discharge abnormality detection process is executed, a unit operation period Tu during which both the printing process and the discharge abnormality detection process are executed, and the like.

The control circuit 100 controls the selection control circuit 51 so that the print data signal SI is supplied to the selection control circuit 51 every unit operation period Tu and the latch circuit LT latches the print data signal SI every unit operation period Tu. That is, the control circuit 100 controls the selection control circuit 51 so as to supply the drive signal Vin to the piezoelectric elements 60 included in the M ejection sections 600 per unit operation period Tu.

Specifically, when the liquid ejecting apparatus 1 executes only the printing process during the unit operation period Tu, the control circuit 100 controls the selection control circuit 51 so as to supply the driving signal Vin for printing to the piezoelectric elements 60 included in the M ejection sections 600. In this case, ink of an amount corresponding to the image data input from each of the M ejection sections 600 to the liquid ejection device 1 is ejected to the medium P. Accordingly, an image corresponding to the image data is formed on the medium P.

On the other hand, when the liquid ejecting apparatus 1 executes only the ejection failure detection process during the unit operation period Tu, the control circuit 100 controls the selection control circuit 51 so as to supply the driving signal Vin for inspection to the piezoelectric elements 60 included in the M ejection portions 600.

In addition, when the liquid ejecting apparatus 1 executes both the printing process and the ejection failure detection process during the unit operation period Tu, the control circuit 100 controls the selection control circuit 51 so as to supply the driving signal Vin for printing to a part of the piezoelectric elements 60 included in the M ejection units 600, and controls the selection control circuit 51 so as to supply the driving signal Vin for inspection to the piezoelectric elements 60 included in the remaining ejection units 600.

The decoder DC decodes the 3-bit print data [ b1, b2, b3] latched by the latch circuit LT, and outputs the H-level or L-level selection signals Sa, Sb, and Sc during the control periods Ts1 and Ts2, respectively.

Fig. 6 is a diagram showing the contents of decoding performed by the decoder DC. As shown in fig. 6, when the print data [ b1, b2, b3] is [1, 0, 0], the corresponding decoder DC sets the select signal Sa to the H level and the select signals Sb and Sc to the L level in the control period Ts1, and sets the select signals Sa and Sc to the L level and the select signal Sb to the H level in the control period Ts 2.

Returning to fig. 5, the selection control circuit 51 includes M sets of transmission gates TG. Each transfer gate TG includes transfer gates TGa, TGb, and TGc. That is, in the selection control circuit 51, groups of the transfer gates TGa, TGb, and TGc are provided so as to correspond to the M ejection sections 600.

The selection signal Sa is input to the transmission gate TGa. The transmission gate TGa is turned on when the selection signal Sa is at the H level and is turned off when the selection signal Sa is at the L level. Similarly, the selection signal Sb is input to the transmission gate TGb. The transmission gate TGb is turned on when the selection signal Sb is at the H level and is turned off when the signal Sb is at the L level. In addition, the selection signal Sc is similarly input to the transfer gate TGc. The transmission gate TGc is conductive when the selection signal Sc is at the H level, and is nonconductive when the selection signal Sc is at the L level.

For example, in the case where the print data [ b1, b2, b3] is [1, 0, 0], the transfer gate TGa is controlled to be on and the transfer gates TGb and TGc are controlled to be off during the control period Ts 1. In addition, during the control period Ts2, the transfer gate TGb is controlled to be on, and the transfer gates TGa and TGc are controlled to be off.

As shown in fig. 5, the drive signal COM-a of the drive signal COM is supplied to one end of the transmission gate TGa, the drive signal COM-B of the drive signal COM is supplied to one end of the transmission gate TGb, and the drive signal COM-C of the drive signal COM is supplied to one end of the transmission gate TGc. Further, the other ends of the transmission gates TGa, TGb, and TGc are commonly connected to the output terminal OTN of the switch circuit 53.

Here, as shown in fig. 6, the selection signals Sa, Sb, Sc are exclusively at the H level. Therefore, the transmission gates TGa, TGb, TGc are exclusively turned on during the control periods Ts1, Ts2, respectively. Thereby, the drive signal Com-A, Com-B, Com-C exclusively selected in each of the control periods Ts1, Ts2 is output as the drive signal Vin to the output terminal OTN, and is supplied to the corresponding piezoelectric element 60 via the switching circuit 53.

Fig. 7 is a diagram for explaining the operation of the selection control circuit 51 in the unit operation period Tu. As shown in fig. 7, the unit operation period Tu is defined by the latch signal LAT. The control periods Ts1 and Ts2 included in the unit operation period Tu are defined by the latch signal LAT and the conversion signal CH.

The drive signal COM-a of the drive signal COM supplied from the drive signal output circuit 50a is a signal for generating the drive signal Vin for printing in the unit operation period Tu, and includes a waveform in which the unit waveform PA1 arranged in the control period Ts1 and the unit waveform PA2 arranged in the control period Ts2 are continuous. The potentials at the start timing and the end timing of the unit waveforms PA1 and PA2 are both the reference potential V0. Further, the potential difference between the potential Va11 and the potential Va12 of the unit waveform PA1 is larger than the potential difference between the potential Va21 and the potential Va22 of the unit waveform PA 2. Therefore, the amount of ink ejected from the nozzle 651 corresponding to the piezoelectric element 60 when the piezoelectric element 60 is driven by the unit waveform PA1 is larger than the amount of ink ejected from the nozzle 651 when the piezoelectric element 60 is driven by the unit waveform PA 2. Here, the amount of ink ejected from the nozzle 651 corresponding to the piezoelectric element 60 when the piezoelectric element 60 is driven by the unit waveform PA1 is referred to as a medium amount, and the amount of ink ejected from the nozzle 651 corresponding to the piezoelectric element 60 when the piezoelectric element 60 is driven by the unit waveform PA2 is referred to as a small amount.

The drive signal COM-B of the drive signal COM supplied from the drive signal output circuit 50a during the unit operation period Tu is a signal for generating the drive signal Vin for printing, and includes a waveform in which the unit waveform PB1 disposed during the control period Ts1 and the unit waveform PB2 disposed during the control period Ts2 are continuous. The potential of the unit waveform PB1 at the start timing and the end timing is the reference potential V0, and the potential of the unit waveform PB2 is held at the reference potential V0 throughout the control period Ts 2. The potential difference between the potential Vb11 of the unit waveform PB1 and the reference potential V0 is smaller than the potential difference between the potential Va21 and the potential Va22 of the unit waveform PA 2. When the piezoelectric element 60 corresponding to the nozzle 651 is driven by the unit waveform PB1, the piezoelectric element 60 is driven to such an extent that ink is not ejected from the corresponding nozzle 651. In addition, when the unit waveform PB2 is supplied to the piezoelectric element 60, the piezoelectric element 60 does not displace. Therefore, the ink is not ejected from the nozzle 651.

The drive signal COM-C of the drive signal COM supplied from the drive signal output circuit 50a during the unit operation period Tu is a signal for generating the drive signal Vin for inspection, and includes a waveform in which the unit waveform PC1 disposed during the control period Ts1 and the unit waveform PC2 disposed during the control period Ts2 are continuous. The potentials at the timing of the start of the unit waveform PC1 and the timing of the end of the unit waveform PC2 are both the reference potential V0. The unit waveform PC1 transitions from the reference potential V0 to the potential Vc11, then transitions from the potential Vc11 to the potential Vc12, and then remains at the potential Vc12 until the end of the control period Ts 1. After the potential Vc12 is maintained, the unit waveform PC2 transitions from the potential Vc12 to the reference potential V0 before the control period Ts2 ends.

As shown in FIG. 7, SI [1] to SI [ M ] supplied as the print data signal SI and as the serial signal are sequentially transferred to the shift register SR by the clock signal SCK. Then, when the clock signal SCK is stopped, SI 1-SI M is held in the corresponding shift registers SR 1-SR M. Then, at the timing of rising of the latch signal LAT, that is, at the timing of starting the unit operation period Tu, the M latch circuits LT included in the selection control circuit 51 latch the SI [1] to SI [ M ] held in the shift registers SR [1] to SR [ M ], respectively.

The M decoders DC output the selection signals Sa, Sb, and Sc of the logic levels corresponding to the SI [1] to SI [ M ] latched by the latch circuit LT in the control periods Ts1 and Ts2, respectively, in accordance with the contents shown in fig. 6.

Then, the M transfer gates TGa, TGb, TGc are controlled to be conductive or non-conductive, respectively, based on the logic levels of the input selection signals Sa, Sb, Sc. Thus, the drive signals COM-A, Com-B, Com-C included in the drive signal COM are selected or unselected, respectively, to generate the drive signal Vin. Then, the generated drive signal Vin is output to the switching circuit 53.

Next, an example of the waveform of the drive signal Vin output from the selection control circuit 51 in the unit operation period Tu will be described with reference to fig. 8. Fig. 8 is a diagram showing an example of the waveform of the drive signal Vin.

When the print data [ b1, b2, b3] included in the print data signal SI supplied to the selection control circuit 51 in the unit operation period Tu is [1, 1, 0], the decoder DC sets the logic level of the selection signals Sa, Sb, Sc in the control period Ts1 to H, L, L level and sets the logic level of the selection signals Sa, Sb, Sc in the control period Ts2 to H, L, L level. Therefore, the drive signal Com-a is selected in the control period Ts1, and the drive signal Com-a is selected in the control period Ts 2. Therefore, the selection control circuit 51 outputs the drive signal Vin having a waveform in which the unit waveform PA1 and the unit waveform PA2 are continuous in the unit operation period Tu. As a result, during the unit operation period Tu, a medium amount of ink based on the unit waveform PA1 and a small amount of ink based on the unit waveform PA2 are ejected from the corresponding ejection section 600. Then, the ink discharged from the discharge unit 600 is combined with the medium P, thereby forming large dots on the medium P.

When the print data [ b1, b2, b3] included in the print data signal SI supplied to the selection control circuit 51 in the unit operation period Tu is [1, 0, 0], the decoder DC sets the logic level of the selection signals Sa, Sb, Sc in the control period Ts1 to H, L, L level and sets the logic level of the selection signals Sa, Sb, Sc in the control period Ts2 to L, H, L level. Therefore, the drive signal Com-a is selected in the control period Ts1, and the drive signal Com-B is selected in the control period Ts 2. Therefore, the selection control circuit 51 outputs the drive signal Vin having a waveform in which the unit waveform PA1 and the unit waveform PB2 are continuous in the unit operation period Tu. As a result, during the unit operation period Tu, a medium amount of ink based on the unit waveform PA1 is ejected from the corresponding ejection unit 600, and a midpoint is formed on the medium P.

When the print data [ b1, b2, b3] included in the print data signal SI supplied to the selection control circuit 51 in the unit operation period Tu is [0, 1, 0], the decoder DC sets the logic level of the selection signals Sa, Sb, Sc in the control period Ts1 to L, H, L level and sets the logic level of the selection signals Sa, Sb, Sc in the control period Ts2 to H, L, L level. Therefore, the drive signal Com-B is selected in the control period Ts1, and the drive signal Com-a is selected in the control period Ts 2. Therefore, the selection control circuit 51 outputs the drive signal Vin having a waveform in which the unit waveform PB1 and the unit waveform PA2 are continuous in the unit operation period Tu. As a result, in the unit operation period Tu, the ink of the small-scale amount based on the unit waveform PA2 is ejected from the corresponding ejection unit 600, and a small dot is formed on the medium P.

When the print data [ b1, b2, b3] included in the print data signal SI supplied to the selection control circuit 51 in the unit operation period Tu is [0, 0, 0], the decoder DC sets the logic level of the selection signals Sa, Sb, Sc in the control period Ts1 to L, H, L level and sets the logic level of the selection signals Sa, Sb, Sc in the control period Ts2 to L, H, L level. Therefore, the drive signal Com-B is selected in the control period Ts1, and the drive signal Com-B is selected in the control period Ts 2. Thus, the selection control circuit 51 outputs the drive signal Vin having a waveform in which the unit waveform PB1 and the unit waveform PB2 are continuous in the unit operation period Tu. As a result, the ink is not ejected from the corresponding ejection portion 600 during the unit operation period Tu. Therefore, dots are not formed on the medium P. In this case, the selection control circuit 51 outputs the drive signal Vin to drive the piezoelectric element 60 to such an extent that the ink is not ejected from the ejection section 600, thereby reducing the possibility of ink thickening in the vicinity of the nozzle 651, i.e., a so-called micro-vibration waveform.

When the print data [ b1, b2, b3] included in the print data signal SI supplied to the selection control circuit 51 in the unit operation period Tu is [0, 0, 1], the decoder DC sets the logic level of the selection signals Sa, Sb, Sc to L, L, H level in the control period Ts1 and sets the logic level of the selection signals Sa, Sb, Sc to L, L, H level in the control period Ts 2. Therefore, the drive signal Com-C is selected in the control period Ts1, and the drive signal Com-C is selected in the control period Ts 2. Therefore, the selection control circuit 51 outputs the drive signal Vin having a waveform in which the unit waveform PC1 and the unit waveform PC2 are continuous in the unit operation period Tu. As a result, the ink is not ejected from the corresponding ejection portion 600 during the unit operation period Tu. Therefore, dots are not formed on the medium P. In this case, the drive signal Vin output from the selection control circuit 51 corresponds to an inspection waveform for detecting residual vibration of the piezoelectric element 60.

Next, a specific example of the configuration and operation of the switching circuit 53 and the residual vibration detection circuit 52 will be described. Fig. 9 is a diagram showing the electrical configuration of the switching circuit 53 and the residual vibration detection circuit 52. In the following description, the switches U corresponding to the 1 st, 2 nd, … … nd, and M th stages are referred to as switches U [1], U [2], … …, and U [ M ], the ejection unit 600 is referred to as an ejection unit 600[1], 600[2], … …, and 600[ M ], the piezoelectric element 60 is referred to as a piezoelectric element 60[1], 60[2], … …, and 60[ M ], the switching control signal Sw is referred to as a switching control signal Sw [1], Sw [2], … …, and Sw [ M ], and the residual vibration Vout is referred to as residual vibration Vout [1], Vout [2], … …, and Vout [ M ].

As shown in fig. 9, the switching circuit 53 has M switching switches U corresponding to the M piezoelectric elements 60 included in each of the M ejection sections 600. Each of the changeover switches U performs switching based on the changeover control signal Sw so as to supply the drive signal Vin input from the selection control circuit 51 to the piezoelectric element 60 included in the corresponding ejection section 600 or so as to supply the residual vibration Vout generated in the ejection section 600 to the residual vibration detection circuit 52 after supplying the drive signal Vin to the piezoelectric element 60.

Specifically, the switching control signal Sw [1] is input to the switching switch U [1 ]. Then, the changeover switch U [1] performs switching such that the drive signal Vin [1] is supplied to the piezoelectric element 60[1] based on the changeover control signal Sw [1], or such that the residual vibration Vout [1] generated in the discharge section 600[1] is supplied to the residual vibration detection circuit 52 after the drive signal Vin [1] is supplied to the piezoelectric element 60[1 ].

Likewise, the switching control signal Sw [ M ] is input to the switching switch U [ M ]. Then, the changeover switch U [ M ] performs switching such that the drive signal Vin [ M ] is supplied to the piezoelectric element 60[ M ] based on the changeover control signal Sw [ M ], or such that the residual vibration Vout [ i ] generated in the discharge section 600[ i ] is supplied to the residual vibration detection circuit 52 after the drive signal Vin [ M ] is supplied to the piezoelectric element 60[ M ].

The switching control signals Sw [1] to Sw [ M ] control the switching of the M switching switches U [1] to U [ M ] so that any one of the M piezoelectric elements 60[1] to 60[ M ] is electrically connected to the residual vibration detection circuit 52 in the unit operation period Tu. In other words, the residual vibration detection circuit 52 detects any one of the residual vibrations Vout [1] to Vout [ M ] corresponding to the respective M ejection sections 600[1] to 600[ M ] based on the switching control signal Sw, and generates the corresponding residual vibration signal NVT. Therefore, the switching control signal Sw may be configured so that the M switching switches U [1] to U [ M ] are sequentially controlled to be on, and for example, the switching control signal Sw output from the control circuit 100 may be sequentially transmitted through a shift register or the like to sequentially switch the M switching switches U.

Next, the structure of the residual vibration detection circuit 52 will be described. Fig. 10 is a diagram showing an electrical configuration of the residual vibration detection circuit 52. The residual vibration detection circuit 52 detects the residual vibration Vout, generates a residual vibration signal NVT indicating at least one of the period and the vibration frequency of the detected residual vibration Vout, and outputs the residual vibration signal NVT to the control circuit 100.

As shown in fig. 10, the residual vibration detection circuit 52 includes a waveform shaping section 57 and a periodic signal generation section 58. The waveform shaping unit 57 generates a shaped waveform signal Vd from which the noise component is removed from the residual vibration Vout. The waveform shaping unit 57 includes, for example, a high-pass filter for outputting a signal in which frequency components lower than the frequency band of the residual vibration Vout are attenuated, a low-pass filter for outputting a signal in which frequency components higher than the frequency band of the residual vibration Vout are attenuated, and the like. Then, the waveform shaping unit 57 limits the frequency range of the residual vibration Vout and outputs a shaped waveform signal Vd from which noise components are removed. The waveform shaping unit 57 may include a negative feedback type amplifier circuit for adjusting the amplitude of the residual vibration Vout, a voltage follower circuit for converting the impedance of the residual vibration Vout, and the like.

The period signal generating unit 58 generates a residual vibration signal NVT indicating the period and the vibration frequency of the residual vibration Vout based on the shaped waveform signal Vd, and outputs the residual vibration signal NVT to the control circuit 100. The shaped waveform signal Vd, the mask signal Msk, and the threshold potential Vth are input to the periodic signal generation unit 58. Here, the mask signal Msk and the threshold potential Vth may be stored in the control circuit 100, for example, or may be information stored in a memory not shown in the figure.

Fig. 11 is a diagram for explaining the operation of the periodic signal generation unit 58. As shown in fig. 11, the threshold potential Vth is a threshold determined to be a predetermined level in the amplitude of the shaped waveform signal Vd, and is, for example, a potential determined to be the center level of the amplitude of the shaped waveform signal Vd. Then, the period signal generating section 58 generates and outputs the residual vibration signal NVT based on the input shaped waveform signal Vd and the threshold potential Vth.

Specifically, the periodic signal generation unit 58 compares the potential of the shaped waveform signal Vd with the threshold potential Vth. Then, the period signal generating unit 58 generates a residual vibration signal NVT which is at the H level when the potential of the shaped waveform signal Vd is equal to or higher than the threshold potential Vth, and at the L level when the potential of the shaped waveform signal Vd is lower than the threshold potential Vth. That is, the period during which the logic level of the residual vibration signal NVT is shifted from the H level to the L level and is again at the H level corresponds to the period of the residual vibration Vout, and the reciprocal of the period corresponds to the vibration frequency.

The mask signal Msk is a signal that is at the H level from the time t0 when the supply of the shaped waveform signal Vd starts to a predetermined period Tmsk. The period signal generating section 58 stops the generation of the residual vibration signal NVT during the period when the mask signal Msk is at the H level, and generates the residual vibration signal NVT during a period other than the period when the mask signal Msk is at the H level. That is, the periodic signal generation unit 58 generates the residual vibration signal NVT for only the shaped waveform signal Vd after the elapse of the period Tmsk among the shaped waveform signals Vd. Thus, the periodic signal generation unit 58 can eliminate the noise component superimposed immediately after the residual vibration Vout occurs, and can generate the residual vibration signal NVT with high accuracy.

As described above, the drive signal selection control circuit 200 switches whether or not to supply the waveform of the drive signal COM to the plurality of piezoelectric elements 60 included in the plurality of ejection sections 600 based on the clock signal SCK, the print data signal SI, the latch signal LAT, and the conversion signal CH. That is, the drive signal selection control circuit 200 generates the drive signals Vin to be supplied to the plurality of piezoelectric elements 60 included in the plurality of discharge units 600, and supplies the drive signals Vin to the corresponding piezoelectric elements 60 included in the discharge units 600.

4. Structure of integrated circuit

Here, as described above, the drive signal selection control circuit 200 is mounted on the integrated circuit 201. The integrated circuit 201 includes, in addition to the selection control circuit 51, the residual oscillation detection circuit 52, and the switching circuit 53 included in the drive signal selection control circuit 200, various circuits such as a power-on reset circuit, not shown, for resetting the inside of the integrated circuit 201 when a power supply voltage is supplied to the integrated circuit 201, a temperature detection circuit for detecting the internal temperature of the integrated circuit 201, and an internal voltage generation circuit for outputting an internal voltage used in the integrated circuit 201.

In addition, in response to market demands for improvement in printing efficiency of the liquid ejecting apparatus 1 in recent years, the number of nozzles provided in the print head 21 increases, and the amount of ink ejected from one nozzle 651 increases, and as a result, the amount of current supplied to the integrated circuit 201 increases. As the amount of current supplied to the integrated circuit 201 increases, a noise component generated in the integrated circuit 201 increases, and as a result, the integrated circuit 201 may malfunction due to the noise component.

In particular, the drive signal selection control circuit 200 controls switching of whether or not to supply the drive signal COM to the plurality of ejection units 600 included in the print head 21. Therefore, when the number of the ejection portions 600 included in the print head 21 increases, a large current flows in the drive signal selection control circuit 200 as the number of the ejection portions 600 increases. Further, since the drive signal selection control circuit 200 controls switching whether or not to supply the drive signal COM, switching noise due to the switching occurs. That is, in order to reduce the influence of noise components that increase with an increase in the amount of current supplied to the integrated circuit 201, it is required to appropriately configure the drive signal selection control circuit 200 mounted on the integrated circuit 201.

In view of the above, in the liquid ejecting apparatus 1, the print head 21, and the integrated circuit 201 according to the present embodiment, by appropriately arranging the drive signal selection control circuit 200 inside the integrated circuit 201 that controls the drive of the piezoelectric element 60, which is a capacitive load of the print head 21 used in the liquid ejecting apparatus 1, the influence of noise components, which increase with an increase in the amount of current, on the integrated circuit 201 is reduced, and the possibility of malfunction occurring in the integrated circuit 201 is reduced.

Fig. 12 is a diagram showing an example of the arrangement of internal circuits in the integrated circuit 201. Fig. 13 is a diagram showing an example of the arrangement of terminals of the integrated circuit 201 for electrically connecting the integrated circuit 201 and the FPC 210. Here, fig. 12 and 13 are views when the integrated circuit 201 is viewed from the same plane. Specifically, fig. 12 shows the circuit mounting surface 206 when the inside of the integrated circuit 201 is viewed from the circuit mounting surface 206 side on which the drive signal selection control circuit 200 and various circuits included in the integrated circuit 201 are mounted, and fig. 13 shows the terminal mounting surface 207 which electrically connects the integrated circuit 201 and the FPC210 when the inside of the integrated circuit 201 is viewed from the circuit mounting surface 206 side. In fig. 13, circuit blocks 310, 320, 330, and 340 indicating the arrangement of various circuits mounted on the circuit mounting surface 206 of the integrated circuit 201 are illustrated by broken lines.

As shown in fig. 12 and 13, the integrated circuit 201 has a substantially rectangular shape, and includes: an edge 202; an edge 203 located opposite the edge 202; an edge 204 that intersects both edge 202 and edge 203; and a side 205 intersecting both the side 202 and the side 203 and located at a position opposite to the side 204, and including a circuit mounting surface 206 on which various circuits included in the integrated circuit 201 are mounted and a terminal mounting surface 207 on which a plurality of terminals electrically connected to the FPC210 are provided. Here, the side 202 is an example of a first side, the side 203 is an example of a second side, the side 204 is an example of a third side, and the side 205 is an example of a fourth side.

As shown in fig. 12, four circuit blocks 310, 320, 330, 340 are provided on the circuit mounting surface 206 of the integrated circuit 201. Circuit block 310 is located on side 203 and on side 204 of integrated circuit 201, circuit block 320 is located on side 202 of integrated circuit 201, circuit block 330 is located on side 203 and on side 205 of integrated circuit 201, and circuit block 340 is located on side 203 of integrated circuit 201 and between circuit block 310 and circuit block 330 in a direction from side 204 toward side 205. That is, circuit block 320 is located along side 202, and circuit blocks 310, 330, and 340 are located along side 203, from side 204 to side 205, and are arranged in the order of circuit block 310, circuit block 340, and circuit block 330. Here, the circuit block 320 is an example of a first circuit block, the circuit block 310 is an example of a second circuit block, the circuit block 330 is an example of a third circuit block, and the circuit block 340 is an example of a fourth circuit block.

Specific configurations of the circuit blocks 310, 320, 330, 340 will be explained.

As shown in fig. 12, the circuit block 310 includes circuit mounting regions 311, 312, 313, 314. The circuit mounting region 311 is located at a position along the side 203 in the circuit block 310. In the circuit mounting region 311, the changeover switches U [1] -U [ i ] corresponding to the discharge portions 600[1] -600 [ i ] (i is 1-M-2) among the M discharge portions 600[1] -600 [ M ] are located at positions arranged in the order of the changeover switches U [1], U [2], … …, and U [ i ] from the side 205 toward the side 204 and along the side 203.

The circuit mounting region 312 is located at a position along the side 203 on the side 202 side of the circuit mounting region 311 in the circuit block 310. In the circuit mounting region 312, transfer gates TG [1] to TG [ i ] corresponding to the ejection portions 600[1] to 600[ i ] of the M ejection portions 600[1] to 600[ M ] are located at positions arranged in the order of the transfer gates TG [1], TG [2], … …, and TG [ i ] from the side 205 toward the side 204 and along the side 203.

The circuit mounting region 313 is located in the circuit block 310 at a position along the side 203 on the side 202 side of the circuit mounting region 312. In the circuit mounting region 313, the decoders DC [1] -DC [ i ] corresponding to the discharge portions 600[1] -600 [ i ] of the M discharge portions 600[1] -600 [ M ] are located at positions arranged in the order of the decoders DC [1], DC [2], … …, and DC [ i ] from the side 205 toward the side 204 and along the side 203.

The circuit mounting region 314 is located at a position along the side 203 on the side 202 side of the circuit mounting region 313 in the circuit block 310. In the circuit mounting region 314, the shift registers SR [1] -SR [ i ] corresponding to the discharge units 600[1] -600 [ i ] of the M discharge units 600[1] -600 [ M ] are located at positions that are arranged in the order of the shift registers SR [1], SR [2], … …, and SR [ i ] from the side 205 toward the side 204 and along the side 203.

As above, circuit block 310 includes: switching transmission gates TG [1] to TG [ i ] for supplying driving signals Vin [1] to Vin [ i ] based on the driving signal COM to the piezoelectric elements 60[1] to 60[ i ] included in the ejection units 600[1] to 600[ i ]; decoders DC [1] DC [ i ] and shift registers SR [1] SR [ i ] for controlling the switching of transmission gates TG [1] TG [ i ], transmission gates TG [1] TG [ i ] are located at positions such that the shortest distance between transmission gates TG [1] TG [ i ] and edge 203 is shorter than the shortest distance between decoders DC [1] DC [ i ] and shift registers SR [1] SR [ i ] and edge 203.

As shown in fig. 13, in integrated circuit 201, terminals 341[1] to 341[ i ], terminals 342[1] to 342[ i ], terminals 343[1] to 343[ i ], and terminals 344[1] to 344[ i ] are located at positions corresponding to the region where circuit block 310 is located on terminal mounting surface 207.

The terminals 341[1] to 341[ i ] electrically connect the respective changeover switches U [1] to U [ i ] and the piezoelectric elements 60[1] to 60[ i ] included in the respective discharge units 600[1] to 600[ i ], respectively. That is, the terminal 341[1] outputs the drive signal Vin [1] supplied to the piezoelectric element 60[1] from the integrated circuit 201, and inputs the residual vibration Vout [1] to the integrated circuit 201. Similarly, the terminal 341[ i ] outputs the drive signal Vin [ i ] supplied to the piezoelectric element 60[ i ] from the integrated circuit 201, and inputs the residual vibration Vout [ i ] to the integrated circuit 201. The terminals 341[1] to 341[ i ] are located along the side 203 and are arranged in the order of the terminals 341[1], 341[2], … …, and 341[ i ] in the direction from the side 205 to the side 204.

The terminals 342[1] to 342[ i ] are electrically connected to the transmission gates TGa included in the transmission gates TG [1] to TG [ i ], respectively. Then, the drive signal Com-a is supplied to the transmission gate TGa via the respective terminals 342[1] to 342[ i ]. The terminals 342[1] to 342[ i ] are located on the side 202 of the terminals 341[1] to 341[ i ] arranged along the side 203, and are located at positions arranged in the order of the terminals 342[1], 342[2], … …, and 342[ i ] in the direction from the side 205 toward the side 204.

The terminals 343[1] to 343[ i ] are electrically connected to the transmission gates TGb included in the respective transmission gates TG [1] to TG [ i ], respectively. Then, the drive signal Com-B is supplied to the transmission gate TGb via the respective terminals 343[1] to 343[ i ]. The terminals 343[1] to 343[ i ] are located on the side 202 of the terminals 342[1] to 342[ i ] arranged along the side 203, and are located at positions arranged in the order of the terminals 343[1], 343[2], … …, 343[ i ] in the direction from the side 205 toward the side 204.

The terminals 344[1] to 344[ i ] are electrically connected to the transmission gates TGc included in the transmission gates TG [1] to TG [ i ], respectively. Then, the drive signal Com-C is supplied to the transmission gate TGc via the respective terminals 344[1] to 344[ i ]. The terminals 344[1] to 344[ i ] are located on the side 202 of the terminals 343[1] to 343[ i ] arranged along the side 203, and are located at positions in the order of the terminals 344[1], 344[2], … …, and 344[ i ] in the direction from the side 205 toward the side 204.

Here, any one of the piezoelectric elements 60[1] to 60[ i ] included in the ejection sections 600[1] to 600[ i ] is an example of the second piezoelectric element and the second capacitive load, and the piezoelectric elements 60[1] to 60[ i ] are an example of the second piezoelectric element group and the second capacitive load group. Terminals 341[1] to 341[ i ] electrically connected to piezoelectric elements 60[1] to 60[ i ] of the plurality of piezoelectric elements 60 at positions along the side 203 are an example of the second terminal group.

As shown in fig. 12, the circuit block 320 includes circuit mounting areas 321, 322, 323, 324. The circuit mounting area 321 is located along the side 202 in the circuit block 320. In the circuit mounting region 321, the changeover switches U [ i +1] - [ U [ j ] corresponding to the discharge portions 600[ i +1] - [ 600[ j ] (j ═ i +1 to M-1) of the M discharge portions 600[1] - [ 600 ] are located at positions arranged in the order of the changeover switches U [ i +1], U [ i +2], … …, and U [ j ] from the side 204 toward the side 205 and along the side 202.

The circuit mounting region 322 is located at a position along the side 202 on the side 203 side of the circuit mounting region 321 in the circuit block 320. In the circuit mounting region 322, transfer gates TG [ i +1] -TG [ j ] corresponding to the ejection portions 600[ i +1] -600 [ j ] of the M ejection portions 600[1] -600 [ M ] are located at positions which are arranged in the order of the transfer gates TG [ i +1], TG [ i +2], … …, TG [ j ] from the side 204 toward the side 205 and along the side 202.

The circuit mounting region 323 is located at a position along the side 202 on the side 203 side of the circuit mounting region 322 in the circuit block 320. In the circuit mounting region 323, the decoders DC [ i +1] -DC [ j ] corresponding to the ejection portions 600[ i +1] -600 [ j ] of the M ejection portions 600[1] -600 [ M ] are located at positions that are arranged in the order of the decoders DC [ i +1], DC [ i +2], … …, DC [ j ] from the side 204 toward the side 205 and along the side 202.

The circuit mounting region 324 is located at a position along the side 202 on the side 203 side of the circuit mounting region 323 in the circuit block 320. In the circuit mounting region 324, the shift registers SR [ i +1] SR [ j ] corresponding to the discharge units 600[ i +1] 600[ j ] of the M discharge units 600[1] 600[ M ] are located at positions along the side 202 from the side 204 to the side 205, in the order of the shift registers SR [ i +1], SR [ i +2], … …, SR [ j ].

As above, circuit block 320 includes: switching transfer gates TG [ i +1] to TG [ j ] for supplying drive signals Vin [ i +1] to Vin [ j ] based on the drive signal COM to the piezoelectric elements 60[ i +1] to 60[ j ] included in the ejection sections 600[ i +1] to 600[ j ]; decoders DC [ i +1] DC [ j ] and shift registers SR [ i +1] SR [ j ] for controlling switching of transmission gates TG [ i +1] TG [ j ], wherein the transmission gates TG [ i +1] TG [ j ] are located at positions where shortest distances between the transmission gates TG [ i +1] TG [ j ] and the edge 202 are shorter than shortest distances between the decoders DC [ i +1] DC [ j ] and the shift registers SR [ i +1] SR [ j ] and the edge 202. Here, any one of the transmission gates TG [ i +1] to TG [ j ] is an example of a switch circuit, and any one of the corresponding decoders DC [ i +1] to DC [ j ] and shift registers SR [ i +1] to SR [ j ] is an example of a switching control circuit.

As shown in fig. 13, in the integrated circuit 201, the terminals 341[ i +1] to 341[ j ], the terminals 342[ i +1] to 342[ j ], the terminals 343[ i +1] to 343[ j ] and the terminals 344[ i +1] to 344[ j ] are located at positions corresponding to the regions of the terminal mounting surface 207 where the circuit blocks 320 are located.

The terminals 341[ i +1] to 341[ j ] electrically connect the respective changeover switches U [ i +1] to U [ j ] and the piezoelectric elements 60[ i +1] to 60[ j ] included in the respective discharge sections 600[ i +1] to 600[ j ], respectively. That is, the terminal 341[ i +1] outputs the drive signal Vin [ i +1] supplied to the piezoelectric element 60[ i +1] from the integrated circuit 201, and inputs the residual vibration Vout [ i +1] to the integrated circuit 201. Similarly, the terminal 341[ j ] outputs a drive signal Vin [ j ] supplied to the piezoelectric element 60[ j ] from the integrated circuit 201, and inputs the residual vibration Vout [ j ] to the integrated circuit 201. The terminals 341[ i +1] to 341[ j ] are located at positions along the side 202 and arranged in the order of the terminals 341[ i +1], 341[ i +2], … …, and 341[ j ] in the direction from the side 204 to the side 205.

The terminals 342[ i +1] to 342[ j ] are electrically connected to the transmission gates TGa included in the transmission gates TG [ i +1] to TG [ j ], respectively. Then, the drive signal Com-a is supplied to the transmission gate TGa via the respective terminals 342[ i +1] to 342[ j ]. The terminals 342[ i +1] to 342[ j ] are located on the side 203 of the terminals 341[ i +1] to 341[ j ] arranged along the side 202, and are located at positions where the terminals 342[ i +1], 342[ i +2], … …, and 342[ j ] are arranged in this order in the direction from the side 204 toward the side 205.

The terminals 343[ i +1] to 343[ j ] are electrically connected to the transmission gates TGb included in the respective transmission gates TG [ i +1] to TG [ j ], respectively. Then, the drive signal Com-B is supplied to the transmission gate TGb via the respective terminals 343[ i +1] to 343[ j ]. The terminals 343[ i +1] to 343[ j ] are located on the side 203 of the terminals 342[ i +1] to 342[ j ] arranged along the side 202, and are located at positions arranged in the order of the terminals 343[ i +1], 343[ i +2], … …, 343[ j ] in the direction from the side 204 toward the side 205.

The terminals 344[ i +1] to 344[ j ] are electrically connected to the transmission gates TGc included in the transmission gates TG [ i +1] to TG [ j ], respectively. Then, the drive signal Com-C is supplied to the transmission gate TGc via the respective terminals 344[ i +1] to 344[ j ]. The terminals 344[ i +1] to 344[ j ] are located on the side 203 of the terminals 343[ i +1] to 343[ j ] arranged along the side 202, and are located at positions in the order of the terminals 344[ i +1], 344[ i +2], … …, and 344[ j ] in the direction from the side 204 toward the side 205.

Here, any one of the piezoelectric elements 60[ i +1] to 60[ j ] included in the ejection sections 600[ i +1] to 600[ j ] is an example of the first piezoelectric element and the first capacitive load, and the piezoelectric elements 60[ i +1] to 60[ j ] are an example of the first piezoelectric element group and the first capacitive load group. Terminals 341[ i +1] to 341[ j ] electrically connected to piezoelectric elements 60[ i +1] to 60[ j ] of the plurality of piezoelectric elements 60 at positions along the side 202 are an example of the first terminal group.

As shown in fig. 12, the circuit block 330 includes circuit mounting regions 331, 332, 333, 334. The circuit mounting area 331 is located at a position along the side 203 in the circuit block 330. In the circuit mounting region 331, the changeover switches U [ j +1] -U [ M ] corresponding to the ejection portions 600[ j +1] -600 [ M ] of the M ejection portions 600[1] -600 [ M ] are located at positions along the side 203 from the side 205 toward the side 204 in the order of the changeover switches U [ j +1], U [ j +2], … …, U [ M ].

The circuit mounting region 332 is located at a position along the side 203 on the side 202 side of the circuit mounting region 331 in the circuit block 330. In the circuit mounting region 332, transfer gates TG [ j +1] -TG [ M ] corresponding to the ejection portions 600[ j +1] -600 [ M ] of the M ejection portions 600[1] -600 [ M ] are located at positions arranged in the order of the transfer gates TG [ j +1], TG [ j +2], … …, TG [ M ] from the side 205 toward the side 204 along the side 203.

The circuit mounting region 333 is located in the circuit block 330 at a position along the side 203 on the side 202 side of the circuit mounting region 332. In the circuit mounting region 333, the decoders DC [ j +1] -DC [ M ] corresponding to the ejection portions 600[ j +1] -600 [ M ] of the M ejection portions 600[1] -600 [ M ] are located at positions arranged in the order of the decoders DC [ j +1], DC [ j +2], … …, DC [ M ] from the side 205 toward the side 204 and along the side 203.

The circuit mounting region 334 is located in the circuit block 330 at a position along the side 203 on the side 202 side of the circuit mounting region 333. In the circuit mounting region 334, the shift registers SR [ j +1] -SR [ M ] corresponding to the discharge units 600[ j +1] -600 [ M ] of the M discharge units 600[1] -600 [ M ] are located at positions along the side 203 from the side 205 toward the side 204, in the order of the shift registers SR [ j +1], SR [ j +2], … …, and SR [ M ].

As above, the circuit block 330 includes: switching transmission gates TG [ j +1] to TG [ M ] for supplying driving signals Vin [ j +1] to Vin [ M ] based on the driving signal COM to the piezoelectric elements 60[ j +1] to 60[ M ] included in the ejection sections 600[ j +1] to 600[ M ]; decoders DC [ j +1] -DC [ M ] and shift registers SR [ j +1] -SR [ M ] for controlling the switching of transmission gates TG [ j +1] -TG [ M ], wherein the transmission gates TG [ j +1] -TG [ M ] are located at positions where the shortest distances between the transmission gates TG [ j +1] -TG [ M ] and the edge 203 are shorter than the shortest distances between the decoders DC [ j +1] -DC [ M ] and the shift registers SR [ j +1] -SR [ M ] and the edge 203.

As shown in fig. 13, in the integrated circuit 201, the terminals 341[ j +1] to 341[ M ], the terminals 342[ j +1] to 342[ M ], the terminals 343[ j +1] to 343[ M ], and the terminals 344[ j +1] to 344[ M ] are located at positions corresponding to the region where the circuit block 330 is located on the terminal mounting surface 207.

The terminals 341[ j +1] to 341[ M ] electrically connect the respective changeover switches U [ j +1] to U [ M ] and the piezoelectric elements 60[ j +1] to 60[ M ] included in the respective discharge sections 600[ j +1] to 600[ M ], respectively. That is, the terminal 341[ j +1] outputs the drive signal Vin [ j +1] supplied to the piezoelectric element 60[ j +1] from the integrated circuit 201, and inputs the residual vibration Vout [ j +1] to the integrated circuit 201. Similarly, the terminal 341[ M ] outputs the drive signal Vin [ M ] supplied to the piezoelectric element 60[ M ] from the integrated circuit 201, and inputs the residual vibration Vout [ M ] to the integrated circuit 201. The terminals 341[ j +1] to 341[ M ] are located along the side 203 and are arranged in the order of the terminals 341[ j +1], 341[ j +2], … …, and 341[ M ] in the direction from the side 205 to the side 204.

The terminals 342[ j +1] to 342[ M ] are electrically connected to the transmission gates TGa included in the transmission gates TG [ j +1] to TG [ M ], respectively. Then, the drive signal Com-a is supplied to the transmission gate TGa via the respective terminals 342[ j +1] to 342[ M ]. The terminals 342[ j +1] to 342[ M ] are located on the side 202 of the terminals 341[ j +1] to 341[ M ] arranged along the side 203, and are located at positions in the order of the terminals 342[ j +1], 342[ j +2], … …, and 342[ M ] in the direction from the side 205 toward the side 204.

The terminals 343[ j +1] to 343[ M ] are electrically connected to the transmission gates TGb included in the respective transmission gates TG [ j +1] to TG [ M ], respectively. Then, the drive signal Com-B is supplied to the transmission gate TGb via the respective terminals 343[ j +1] to 343[ M ]. The terminals 343[ j +1] to 343[ M ] are located on the side 202 of the terminals 342[ j +1] to 342[ M ] arranged along the side 203, and are located at positions arranged in the order of the terminals 343[ j +1], 343[ j +2], … …, and 343[ M ] in the direction from the side 205 toward the side 204.

The terminals 344[ j +1] to 344[ M ] are electrically connected to the transmission gates TGc included in the transmission gates TG [ j +1] to TG [ M ], respectively. Then, the drive signal Com-C is supplied to the transmission gate TGc via the respective terminals 344[ j +1] to 344[ M ]. The terminals 344[ j +1] to 344[ M ] are located on the side 202 of the terminals 343[ j +1] to 343[ M ] arranged along the side 203, and are located at positions in the order of the terminals 344[ j +1], 344[ j +2], … …, and 344[ M ] in the direction from the side 205 toward the side 204.

Here, any one of the piezoelectric elements 60[ j +1] to 60[ M ] included in the ejection sections 600[ j +1] to 600[ M ] is an example of the third piezoelectric element and the third capacitive load, and the piezoelectric elements 60[ j +1] to 60[ M ] are an example of the third piezoelectric element group and the third capacitive load group. Terminals 341[ j +1] to 341[ M ] electrically connected to piezoelectric elements 60[ j +1] to 60[ M ] of the plurality of piezoelectric elements 60 at positions along the side 203 are examples of the third terminal group.

As described above, the M shift registers SR, the M decoders DC, the M transfer gates TG, and the M switches U corresponding to the M ejection sections 600 included in the drive signal selection control circuit 200 are located in the circuit blocks 310, 320, and 330.

As shown in fig. 12, the circuit block 340 includes an input-output circuit IO, a digital circuit area DB, and an analog circuit area AB.

The input/output circuit IO includes an input/output interface circuit that inputs the print data signal SI, the conversion signal CH, the latch signal LAT, the clock signal SCK, the switching control signal Sw, the voltages VDD and VHV, and the ground signal GND from the control mechanism 10, and outputs the residual vibration signal NVT to the control mechanism 10.

The digital circuit area DB includes a gate array circuit that performs various digital processes in the integrated circuit 201. The digital circuit including the gate array circuit provided in the digital circuit area DB performs buffering of the print data signal SI, the conversion signal CH, the latch signal LAT, the clock signal SCK, and the switching control signal Sw input from the control unit 10, and control of output timing of the print data signal SI, the conversion signal CH, the latch signal LAT, the clock signal SCK, and the switching control signal Sw to the drive signal selection control circuit 200.

The analog circuit area AB includes: the residual vibration detection circuit 52 detects residual vibration Vout generated after the drive signal Vin based on the drive signal COM is supplied to the plurality of piezoelectric elements 60, the power-on reset circuit that resets the operation of the integrated circuit 201 in accordance with the voltage value of the power supply voltage supplied to the integrated circuit 201, and the analog circuit such as the internal voltage generation circuit that outputs the internal voltage used in the integrated circuit 201.

That is, the circuit block 340 includes a circuit that operates in accordance with a signal input from the input/output circuit IO or generates a signal for output from the input/output circuit IO, and specifically includes an analog circuit such as the residual vibration detection circuit 52, the power-on reset circuit, and the internal voltage generation circuit, and a digital circuit such as the gate array circuit.

As shown in fig. 13, in the integrated circuit 201, the plurality of terminals 331 arranged along the side 203 are located at positions corresponding to the regions of the terminal mounting surface 207 where the circuit blocks 340 are located. Specifically, the plurality of terminals 331 arranged along the side 203 are located on the side 205 of the terminals 341[1] to 341[ i ] arranged along the side 203 corresponding to the circuit block 310, and on the side 204 of the terminals 341[ j +1] to 341[ M ] arranged along the side 203 corresponding to the circuit block 330. In other words, the plurality of terminals 331 arranged along side 203 are located between terminals 341[1] to 341[ i ] arranged along side 203 corresponding to circuit block 310 and terminals 341[ j +1] to 341[ M ] arranged along side 203 corresponding to circuit block 330.

The plurality of terminals 331 includes: an input terminal for inputting a print data signal SI, a conversion signal CH, a latch signal LAT, a clock signal SCK, a switching control signal Sw, voltages VDD and VHV, and a ground signal GND to the integrated circuit 201 via the input/output circuit IO; and an output terminal that outputs the residual vibration signal NVT from the integrated circuit 201 via the input-output circuit IO. The circuits included in the circuit blocks 310, 320, 330, and 340 operate based on signals input from the input terminals of the terminals 331, and signals corresponding to the operations of the circuits included in the circuit blocks 310, 320, 330, and 340 are output from the output terminals of the terminals 331. The plurality of terminals 331 exemplify a fourth terminal group.

In addition, as shown in fig. 12 and 13, the integrated circuit 201 includes buffer areas BS1, BS2, BS3 in which no circuit element is provided. The buffer areas BS1, BS2, and BS3 are areas for reducing signal interference between the respective circuit blocks 310, 320, 330, and 340.

Specifically, the buffer area BS1 is located between the circuit block 310 and the circuit block 340, and the buffer area BS3 is located between the circuit block 330 and the circuit block 340. That is, the circuit blocks 310, 330, 340 and the buffer regions BS1, BS3 are located at positions along the side 203 and from the side 204 toward the side 205 in the integrated circuit 201, in the order of the circuit block 310, the buffer region BS1, the circuit block 340, the buffer region BS3, and the circuit block 330.

In addition, the buffer area BS2 is located between the circuit block 320 and the circuit block 340. That is, circuit blocks 320 and 340 and buffer region BS2 are located at positions along side 204 and from side 202 toward side 203 in integrated circuit 201, in the order of circuit block 320, buffer region BS2, and circuit block 340.

In this case, the length of buffer region BS2 in the direction along side 204 is shorter than the length of buffer region BS1 in the direction along side 203, and the length of buffer region BS2 in the direction along side 204 is shorter than the length of buffer region BS3 in the direction along side 203. That is, the shortest distance between the circuit block 320 and the circuit block 340 between which the buffer region BS2 is located is shorter than the shortest distance between the circuit block 310 and the circuit block 340 between which the buffer region BS1 is located, and the shortest distance between the circuit block 320 and the circuit block 340 between which the buffer region BS2 is located is shorter than the shortest distance between the circuit block 330 and the circuit block 340 between which the buffer region BS3 is located.

Here, the buffer area BS2 is an example of a first buffer area, the buffer area BS1 is an example of a second buffer area, and the buffer area BS3 is an example of a third buffer area.

5. Effect of action

In the integrated circuit 201 provided in the print head 21 included in the liquid ejecting apparatus 1 of the present embodiment configured as described above, M shift registers SR corresponding to M ejecting parts 600 included in the drive signal selection control circuit 200, M decoders DC, M transfer gates TG, and shift registers SR 1 to SR [ i ], decoders DC [1 to DC [ i ], transfer gates TG [1 to TG [ i ], and transfer switches U1 to U [ i ] corresponding to the ejecting parts 600[1 to 600[ i ] among the M transfer switches U are provided in the circuit block 310, shift registers SR [ i +1 to SR [ j ], decoders DC [ i +1 to DC [ j ], transfer gates TG [ i +1 to TG [ j ], and transfer switches U [ i +1 to U [ j ] corresponding to the ejecting parts 600[ i +1 to 600[ j ] are provided in the circuit block 320, shift registers SR [ j +1] SR [ M ], decoders DC [ j +1] DC [ M ], transfer gates TG [ j +1] TG [ M ], and changeover switches U [ j +1] U [ M ] corresponding to the discharge sections 600[ j +1] 600[ M ] are provided in the circuit block 330.

The circuit block 340 is provided with an analog circuit such as the residual vibration detection circuit 52, the power-on reset circuit, and the internal voltage generation circuit, and a digital circuit such as a gate array circuit, which operate in accordance with a signal input from the input/output circuit IO or generate a signal for output from the input/output circuit IO.

Further, the buffer region BS1 in which no circuit element is provided is located between the circuit block 310 and the circuit block 340, the buffer region BS2 in which no circuit element is provided is located between the circuit block 320 and the circuit block 340, and the buffer region BS3 in which no circuit element is provided is located between the circuit block 330 and the circuit block 340.

As a result, the buffer regions BS1, BS2, and BS3 function as shielding members, and as a result, the possibility that noise components such as switching noise generated in the drive signal selection control circuit 200, which may become large due to an increase in the amount of current supplied to the integrated circuit 201, overlap with analog circuits and digital circuits provided in the circuit block 340 is reduced.

Therefore, even when the current supplied to the integrated circuit 201 increases, the possibility of malfunction in the integrated circuit 201 due to noise components is reduced, and the possibility of malfunction in the print head 21 and the liquid ejecting apparatus 1 including the integrated circuit 201 is reduced. That is, in the integrated circuit 201 provided in the print head 21 included in the liquid ejecting apparatus 1 according to the present embodiment, even when the amount of input current increases, the possibility of malfunction occurring in the integrated circuit 201, the print head 21 including the integrated circuit 201, and the liquid ejecting apparatus 1 including the print head 21 is reduced.

In the integrated circuit 201 provided in the print head 21 included in the liquid ejecting apparatus 1 according to the present embodiment having the above configuration, since the transfer gate TG needs a signal having a voltage sufficient for driving the piezoelectric element 60, a large current flows through each configuration included in the drive signal selection control circuit 200, and a circuit having a waveform included in the selection or non-selection drive signal COM is used, and therefore, a large noise component is generated also in each configuration included in the drive signal selection control circuit 200.

In the circuit block 320, by positioning the large transmission gate TG through which a large current flows and which is likely to generate a large noise component on the side 202 side of the position opposite to the side 203 on which the circuit block 340 is provided, the possibility that noise components such as switching noise generated in the circuit block 320, which is likely to become large due to an increase in the amount of current supplied to the integrated circuit 201, overlap with analog circuits and digital circuits provided in the circuit block 340 is further reduced.

That is, in circuit block 320, transmission gates TG [ i +1] to TG [ j ] are located at positions such that the shortest distances between transmission gates TG [ i +1] to TG [ j ] and side 202 are shorter than the shortest distances between decoders DC [ i +1] to DC [ j ] and shift registers SR [ i +1] to SR [ j ] and side 203, thereby further reducing the possibility that noise components such as switching noise generated in circuit block 320 overlap analog circuits and digital circuits provided in circuit block 340.

In addition, in this case, by making the shortest distance between the circuit block 320 and the circuit block 340 between which the buffer region BS2 is located shorter than the shortest distance between the circuit block 310 and the circuit block 340 between which the buffer region BS1 is located, and the shortest distance between the circuit block 320 and the circuit block 340 between which the buffer region BS2 is located shorter than the shortest distance between the circuit block 330 and the circuit block 340 between which the buffer region BS3 is located, the possibility of the integrated circuit 201 becoming large is reduced, and the possibility of noise components such as switching noise generated in the circuit blocks 310, 330 overlapping with analog circuits and digital circuits provided in the circuit block 340 is further reduced.

The transmission gates TG included in the circuit blocks 310 and 330, respectively, are located at positions arranged in the direction along the side 203. In addition, circuit blocks 310, 320, 340 are located at positions arranged in a direction along side 203. Therefore, it is difficult to provide the transmission gate TG included in each of the circuit blocks 310 and 330 separately from the circuit block 340, and therefore, in order to further reduce the possibility that noise components such as switching noise generated in the circuit blocks 310 and 330 overlap with analog circuits and digital circuits provided in the circuit block 340, it is required to enlarge the buffer region BS1 between the circuit blocks 310 and 340 and to enlarge the buffer region BS3 between the circuit blocks 330 and 340. However, in the case of enlarging the buffer area BS1 between the circuit block 310 and the circuit block 340, and enlarging the buffer area BS3 between the circuit block 330 and the circuit block 340, miniaturization of the integrated circuit 201 becomes difficult.

Therefore, in the integrated circuit 201 provided in the print head 21 included in the liquid ejecting apparatus 1 of the present embodiment, in the circuit block 320, by positioning the transfer gates TG [ i +1] to TG [ j ] at positions where the shortest distance between the transfer gates TG [ i +1] to TG [ j ] and the side 202 is shorter than the shortest distance between the decoder DC [ i +1] to DC [ j ] and the shift register SR [ i +1] to SR [ j ] and the side 203, the possibility of overlapping noise components such as switching noise generated in the circuit block 320 with analog circuits and digital circuits provided in the circuit block 340 is further reduced, whereby the possibility of an increase in size of the integrated circuit 201 can be reduced by reducing the buffer region BS2 provided between the circuit block 320 and the circuit block 340, increasing the buffer region BS1 provided between the circuit block 310 and the circuit block 340, and increasing the buffer region BS3 provided between the circuit block 330 and the circuit block 340, further, it is possible to further reduce the possibility that noise components such as switching noise generated in the circuit blocks 310 and 330 overlap with analog circuits and digital circuits provided in the circuit block 340.

The embodiments and the modifications have been described above, but the present invention is not limited to these embodiments, and can be implemented in various ways without departing from the scope of the invention. For example, the above embodiments can be combined as appropriate.

The present invention includes substantially the same structures (for example, structures having the same functions, methods, and results, or structures having the same objects and effects) as those described in the embodiments. The present invention includes a structure in which an immaterial part of the structure described in the embodiments is replaced. The present invention includes a configuration that can achieve the same operational effects as the configurations described in the embodiments or a configuration that can achieve the same object. The present invention includes a configuration in which a known technique is added to the configurations described in the embodiments.

The following is derived from the above-described embodiment and modification.

One embodiment of a print head includes:

a plurality of piezoelectric elements driven by being supplied with a drive signal;

an integrated circuit device that switches whether or not to supply the drive signal to the plurality of piezoelectric elements; and

a wiring substrate which transmits the driving signal and is provided with the integrated circuit device,

the integrated circuit device has:

a first side;

a second edge located opposite the first edge;

a first terminal group located at a position along the first edge and electrically connected to a first piezoelectric element group including a first piezoelectric element of the plurality of piezoelectric elements;

a second terminal group located at a position along the second side and electrically connected to a second piezoelectric element group including a second piezoelectric element of the plurality of piezoelectric elements;

a third terminal group located at a position along the second side and electrically connected to a third piezoelectric element group including a third piezoelectric element of the plurality of piezoelectric elements;

a fourth terminal set along the second side between the second terminal set and the third terminal set and comprising an input terminal and an output terminal;

a first circuit block that switches whether or not the drive signal is supplied from the first terminal group to the first piezoelectric element group;

a second circuit block that switches whether or not the drive signal is supplied from the second terminal group to the second piezoelectric element group;

a third circuit block that switches whether or not the drive signal is supplied from the third terminal group to the third piezoelectric element group;

a fourth circuit block that operates in accordance with a signal input from the input terminal or outputs a signal from the output terminal; and

a first buffer region, a second buffer region and a third buffer region where no circuit element is provided,

the first buffer region is located between the first circuit block and the fourth circuit block,

the second buffer region is located between the second circuit block and the fourth circuit block,

the third buffer region is located between the third circuit block and the fourth circuit block.

According to this print head, in the integrated circuit device, the first buffer region in which the circuit elements are not provided is located between the first circuit block for switching whether or not the drive signal is supplied from the first terminal group electrically connected to the first piezoelectric element group, and the fourth circuit block for operating in accordance with the signal input from the input terminal, or a signal is output from the output terminal, the second buffer region in which no circuit element is provided is located between the second circuit block and the fourth circuit block, the second circuit block switches whether or not to supply a drive signal from the second terminal group electrically connected to the second piezoelectric element group, the third buffer region in which no circuit element is provided is located between the third circuit block and the fourth circuit block, and the third circuit block switches whether or not to supply a drive signal from the third terminal group electrically connected to the third piezoelectric element group.

Since the first circuit block, the second circuit block, and the third circuit block switch whether or not to supply the drive signal to each of the first piezoelectric element group, the second piezoelectric element group, and the third piezoelectric element group, a large current flows when the number of piezoelectric elements driven by the drive signal increases, and as a result, large switching noise may be generated. By locating the first buffer region, the second buffer region, and the third buffer region, in which no circuit element is provided, between each of the first circuit block, the second circuit block, and the third circuit block and the fourth circuit block that operates in accordance with a signal input from the input terminal or outputs a signal from the output terminal, the first buffer region, the second buffer region, and the third buffer region function as shielding members for reducing switching noise, respectively, and as a result, the possibility that switching noise generated in the first circuit block, the second circuit block, and the third circuit block affects the fourth circuit block is reduced. This reduces the possibility of malfunction in the integrated circuit device through which a large current flows, and as a result, reduces the possibility of malfunction in the print head.

In one embodiment of the above print head, the print head may be,

the integrated circuit device has:

a third side that intersects both the first side and the second side; and

a fourth edge intersecting both the first edge and the second edge and located opposite the third edge,

the first circuit block is located along the first edge,

the second circuit block, the third circuit block, and the fourth circuit block are located along the second side from the third side toward the fourth side in a position in which the second circuit block, the fourth circuit block, and the third circuit block are arranged in this order.

In one embodiment of the above print head, the print head may be,

the fourth circuit block includes a residual vibration detection circuit that detects residual vibration generated after the drive signal is supplied to the plurality of piezoelectric elements.

The residual vibration is a signal whose voltage value generated after the drive signal is supplied to the piezoelectric element is small, and therefore detection accuracy is lowered when noise is superimposed. According to the print head, since the residual vibration detection circuit that detects the residual vibration is located in the fourth circuit block, the possibility that the switching noise generated in the first circuit block, the second circuit block, and the third circuit block affects the residual vibration detection circuit is reduced. Therefore, the possibility that the detection accuracy of the residual vibration in the residual vibration detection circuit is reduced by the noise component is reduced. Therefore, the possibility of malfunction in the integrated circuit device is further reduced, and as a result, the possibility of malfunction in the print head is further reduced.

In one embodiment of the above print head, the print head may be,

the fourth circuit block includes a power-on reset circuit that resets an operation of the integrated circuit device in accordance with a voltage value of a power supply voltage supplied to the integrated circuit device.

According to the print head, by locating the power-on-reset circuit at the fourth circuit block, the possibility that switching noise generated in the first, second, and third circuit blocks affects the power-on-reset circuit is reduced. Therefore, the possibility of malfunction of the power-on reset circuit due to noise components is reduced. Therefore, the possibility of malfunction in the integrated circuit device is further reduced, and as a result, the possibility of malfunction in the print head is further reduced.

In one embodiment of the above print head, the print head may be,

the fourth circuit block includes an internal voltage generation circuit that outputs an internal voltage used inside the integrated circuit device.

According to the print head, by locating the internal voltage generation circuit at the fourth circuit block, the possibility that switching noise generated in the first circuit block, the second circuit block, and the third circuit block affects the internal voltage generation circuit is reduced. Therefore, the possibility of variation in the voltage value of the internal voltage used in the integrated circuit device is reduced. Therefore, the possibility of malfunction in the integrated circuit device is further reduced, and as a result, the possibility of malfunction in the print head is further reduced.

In one embodiment of the above print head, the print head may be,

the first circuit block includes: a switch circuit that switches whether or not the drive signal is supplied from the first terminal group to the first piezoelectric element group; and a switching control circuit that controls switching of the switching circuit,

the shortest distance between the switch circuit and the first side is shorter than the shortest distance between the switching control circuit and the first side.

According to this print head, the switching circuit included in the first circuit block and configured to switch whether or not to supply the drive signal to the first piezoelectric element group can be located at a position farther from the fourth circuit block than the switching control circuit configured to control switching of the switching circuit. Therefore, the possibility that the switching noise generated in the first circuit block affects the fourth circuit block is further reduced. Therefore, the possibility of malfunction in the integrated circuit device is further reduced, and as a result, the possibility of malfunction in the print head is further reduced.

In one embodiment of the above print head, the print head may be,

the shortest distance between the first circuit block and the fourth circuit block is shorter than the shortest distance between the second circuit block and the fourth circuit block.

According to the print head, since the switching circuit included in the first circuit block and switching whether or not to supply the drive signal to the first piezoelectric element group is located at a position distant from the fourth circuit block, the possibility that switching noise generated in the first circuit block affects the fourth circuit block is reduced, and therefore the shortest distance between the first circuit block and the fourth circuit block can be made shorter than the shortest distance between the second circuit block and the fourth circuit block. As a result, the possibility of malfunction in the integrated circuit device can be reduced, and the possibility of an increase in size of the integrated circuit device can be reduced. Therefore, the possibility of malfunction in the print head can be reduced, and the possibility of an increase in the size of the print head can be reduced.

One embodiment of a liquid ejecting apparatus includes:

a drive signal output circuit that outputs a drive signal; and

a print head that ejects liquid based on the drive signal,

the print head has:

a plurality of piezoelectric elements driven by being supplied with the drive signal;

an integrated circuit device that switches whether or not to supply the drive signal to the plurality of piezoelectric elements; and

a wiring substrate which transmits the driving signal and is provided with the integrated circuit device,

the integrated circuit device has:

a first side;

a second edge located opposite the first edge;

a first terminal group located at a position along the first edge and electrically connected to a first piezoelectric element group including a first piezoelectric element of the plurality of piezoelectric elements;

a second terminal group located at a position along the second side and electrically connected to a second piezoelectric element group including a second piezoelectric element of the plurality of piezoelectric elements;

a third terminal group located at a position along the second side and electrically connected to a third piezoelectric element group including a third piezoelectric element of the plurality of piezoelectric elements;

a fourth terminal set along the second side between the second terminal set and the third terminal set and comprising an input terminal and an output terminal;

a first circuit block that switches whether or not the drive signal is supplied from the first terminal group to the first piezoelectric element group;

a second circuit block that switches whether or not the drive signal is supplied from the second terminal group to the second piezoelectric element group;

a third circuit block that switches whether or not the drive signal is supplied from the third terminal group to the third piezoelectric element group;

a fourth circuit block that operates in accordance with a signal input from the input terminal or outputs a signal from the output terminal; and

a first buffer region, a second buffer region and a third buffer region where no circuit element is provided,

the first buffer region is located between the first circuit block and the fourth circuit block,

the second buffer region is located between the second circuit block and the fourth circuit block,

the third buffer region is located between the third circuit block and the fourth circuit block.

According to this liquid ejecting apparatus, in the integrated circuit device included in the print head, the first buffer region in which the circuit element is not provided is located between the first circuit block for switching whether or not the drive signal is supplied from the first terminal group electrically connected to the first piezoelectric element group, and the fourth circuit block for operating in accordance with the signal input from the input terminal, or a signal is output from the output terminal, the second buffer region in which no circuit element is provided is located between the second circuit block and the fourth circuit block, the second circuit block switches whether or not to supply a drive signal from the second terminal group electrically connected to the second piezoelectric element group, the third buffer region in which no circuit element is provided is located between the third circuit block and the fourth circuit block, and the third circuit block switches whether or not to supply a drive signal from the third terminal group electrically connected to the third piezoelectric element group.

Since the first circuit block, the second circuit block, and the third circuit block switch whether or not to supply the drive signal to each of the first piezoelectric element group, the second piezoelectric element group, and the third piezoelectric element group, a large current flows when the number of piezoelectric elements driven by the drive signal increases, and as a result, large switching noise may be generated. By locating the first buffer region, the second buffer region, and the third buffer region, in which no circuit element is provided, between each of the first circuit block, the second circuit block, and the third circuit block and the fourth circuit block that operates in accordance with a signal input from the input terminal or outputs a signal from the output terminal, the first buffer region, the second buffer region, and the third buffer region function as shielding members for reducing switching noise, respectively, and as a result, the possibility that switching noise generated in the first circuit block, the second circuit block, and the third circuit block affects the fourth circuit block is reduced. This reduces the possibility of malfunction in the integrated circuit device that flows a large current, and as a result, reduces the possibility of malfunction in the liquid ejecting apparatus including the print head including the integrated circuit device.

One way of driving an integrated circuit device with a capacitive load,

the integrated circuit device for driving a capacitive load controls driving of a plurality of capacitive loads driven by supply of a driving signal by switching whether or not to supply the driving signal to the plurality of capacitive loads, and includes:

a first side;

a second edge located opposite the first edge;

a first terminal set located along the first edge and electrically connected to a first capacitive load set comprising a first capacitive load of the plurality of capacitive loads;

a second terminal set located along the second side and electrically connected to a second capacitive load set including a second capacitive load of the plurality of capacitive loads;

a third terminal set located along the second edge and electrically connected with a third capacitive load set comprising a third capacitive load of the plurality of capacitive loads;

a fourth terminal set along the second side between the second terminal set and the third terminal set and comprising an input terminal and an output terminal;

a first circuit block that switches whether or not the drive signal is supplied from the first terminal group to the first capacitive load group;

a second circuit block that switches whether or not the drive signal is supplied from the second terminal group to the second capacitive load group;

a third circuit block that switches whether or not the drive signal is supplied from the third terminal group to the third capacitive load group;

a fourth circuit block that operates in accordance with a signal input from the input terminal or outputs a signal from the output terminal; and

a first buffer region, a second buffer region and a third buffer region where no circuit element is provided,

the first buffer region is located between the first circuit block and the fourth circuit block,

the second buffer region is located between the second circuit block and the fourth circuit block,

the third buffer region is located between the third circuit block and the fourth circuit block.

According to the integrated circuit device for driving a capacitive load, the first buffer region in which no circuit element is provided is located between the first circuit block for switching whether or not the drive signal is supplied from the first terminal group electrically connected to the first capacitive load group, and the fourth circuit block for operating in accordance with the signal input from the input terminal, or a signal is output from the output terminal, the second buffer region in which the circuit element is not provided is located between the second circuit block and the fourth circuit block, the second circuit block switches whether or not the drive signal is supplied from the second terminal group electrically connected to the second capacitive load group, the third buffer region in which the circuit element is not provided is located between the third circuit block and the fourth circuit block, and the third circuit block switches whether or not the drive signal is supplied from the third terminal group electrically connected to the third capacitive load group.

Since the first circuit block, the second circuit block, and the third circuit block switch whether or not to supply the drive signal to the first capacitive load group, the second capacitive load group, and the third capacitive load group, respectively, a large current flows when the number of capacitive loads driven by the drive signal increases, and as a result, a large switching noise may be generated. By locating the first buffer region, the second buffer region, and the third buffer region, in which no circuit element is provided, between each of the first circuit block, the second circuit block, and the third circuit block and the fourth circuit block that operates in accordance with a signal input from the input terminal or outputs a signal from the output terminal, the first buffer region, the second buffer region, and the third buffer region function as shielding members for reducing switching noise, respectively, and as a result, the possibility that switching noise generated in the first circuit block, the second circuit block, and the third circuit block affects the fourth circuit block is reduced. This reduces the possibility of malfunction in the integrated circuit device through which a large current flows.