阅读说明：本技术 多抖动轮廓信号产生 (Multi-jitter profile signal generation ) 是由 S·Y·李 P·D·柯蒂斯 于 2020-05-18 设计创作，主要内容包括：本公开的至少一些方面提供一种系统(104)。在一些实例中,所述系统包含配置成产生脉冲宽度调制(PWM)信号(PWM1)的PWM产生器(218)。所述PWM产生器通过以下操作来产生所述PWM信号：产生具有第一抖动轮廓和第一频率带宽的第一信号；产生具有第二抖动轮廓和大于所述第一频率带宽的第二频率带宽的第二信号；用所述第一信号调制所述第二信号以产生双随机扩频信号；以及根据所述双随机扩频信号产生所述脉冲宽度调制信号。(At least some aspects of the present disclosure provide a system (104). In some examples, the system includes a Pulse Width Modulation (PWM) generator (218) configured to generate a PWM signal (PWM 1). The PWM generator generates the PWM signal by: generating a first signal having a first jitter profile and a first frequency bandwidth; generating a second signal having a second jitter profile and a second frequency bandwidth greater than the first frequency bandwidth; modulating the second signal with the first signal to generate a dual random spread spectrum signal; and generating the pulse width modulation signal according to the double random spread spectrum signal.)

1. A circuit, comprising:

a Linear Feedback Shift Register (LFSR) comprising a clock input terminal configured to receive a clock signal, a first output terminal, and a second output terminal;

a clock divider comprising a clock input terminal configured to receive the clock signal, a first input terminal coupled to the first output terminal of the LFSR, a second input terminal coupled to the second output terminal of the LFSR, and an output terminal;

a ramp generator comprising an input terminal and an output terminal coupled to the output terminal of the clock divider;

an adder comprising a first input terminal coupled to the output terminal of the ramp generator and a second input terminal coupled to the first output terminal of the LFSR and an output terminal; and

an oscillator including a first input terminal and an output terminal coupled to the output terminal of the adder.

2. The circuit of claim 1, wherein the LFSR further comprises a third output terminal, and wherein the clock divider further comprises a third input terminal coupled to the third output terminal of the LFSR.

3. The circuit of claim 1, wherein the ramp generator further comprises a second output terminal, a third output terminal, and a fourth output terminal, and wherein the adder further comprises a third input terminal coupled to the second output terminal of the ramp generator, a fourth input terminal coupled to the third output terminal of the ramp generator, a fifth input terminal coupled to the fourth output terminal of the ramp generator, and a fifth input terminal coupled to the second output terminal of the LFSR.

4. The circuit of claim 3, wherein the adder further comprises a second output terminal, a third output terminal, and a fourth output terminal, and wherein the oscillator further comprises a second input terminal coupled to the second output terminal of the adder, a third input terminal coupled to the third output terminal of the adder, and a fourth input terminal coupled to the fourth output terminal of the adder.

5. The circuit of claim 1, further comprising a power converter comprising a power transistor having a gate terminal configured to be coupled to the output terminal of the oscillator.

6. The circuit of claim 1, wherein the clock divider is configured to divide a received clock signal according to a value received by the clock divider from the LFSR as at least one bit of digital data, and wherein the ramp generator is configured to generate a ramp signal that varies in frequency between successive cycles of the divided clock and output the ramp signal as a digital value.

7. The circuit of claim 6, wherein the adder is configured to modulate the ramp signal according to at least one digital data bit received from the LFSR to generate a Double Random Spread Spectrum (DRSS) signal comprising a jitter profile of the ramp signal and a jitter profile associated with the at least one digital data bit received from the LFSR.

8. The circuit of claim 7, wherein the oscillator is configured to generate a pulse width modulated signal from the DRSS signal, wherein the pulse width modulated signal varies in frequency according to the ramp signal and the at least one digital data bit received by the adder from the LFSR.

9. A circuit, comprising:

a Linear Feedback Shift Register (LFSR) clocked by a clock signal and configured to output a pseudo-random value in a digital data format;

a clock divider configured to receive the clock signal and divide the clock signal by the pseudorandom value to generate and output a divided clock signal;

a ramp generator configured to receive the divided clock signal, generate a ramp signal according to the divided clock signal, and output the ramp signal in the digital data format;

an adder configured to modulate the ramp signal with the pseudorandom value to generate a dual random spread spectrum signal; and

an oscillator configured to receive the dual random spread spectrum signal and generate a pulse width modulated signal in accordance with the dual random spread spectrum signal.

10. The circuit of claim 9, further comprising a power transistor configured to be controlled by the pulse width modulation signal, wherein switching of the power transistor under control of the pulse width modulation signal generates electromagnetic interference having a smaller peak energy than a pulse width modulation signal generated from only the ramp signal or only the pseudo-random value.

11. The circuit of claim 9, wherein the adder modulates the ramp signal with the pseudorandom value such that the amount of frequency change of the dual random spread spectrum signal in a single cycle of the clock signal is greater than the amount of frequency change of the ramp signal during the single cycle of the clock signal.

12. The circuit of claim 11, wherein the adder modulates the ramp signal with the pseudo-random value by adding the pseudo-random value to the ramp signal during each period of the clock signal, and wherein the adder outputs the dual random spread spectrum signal in the digital data format.

13. The circuit of claim 9, wherein the frequency of the pulse width modulated signal varies between successive cycles of the clock signal.

14. The circuit of claim 9, wherein the oscillator generates the pulse width modulated signal by programming a current source to charge a capacitor with a current determined at least in part from the dual random spread spectrum signal.

15. A system, comprising:

a pulse width modulation generator configured to generate a pulse width modulated signal by:

generating a first signal having a first jitter profile and a first frequency bandwidth;

generating a second signal having a second jitter profile and a second frequency bandwidth greater than the first frequency bandwidth;

modulating the second signal with the first signal to generate a dual random spread spectrum signal; and

and generating the pulse width modulation signal according to the double random spread spectrum signal.

16. The system of claim 15, wherein the first signal is a pseudorandom spread spectrum signal, and wherein the second signal is a periodic analog type waveform.

17. The system of claim 16, wherein the pulse width modulation generator comprises:

a Linear Feedback Shift Register (LFSR) clocked by a clock signal and configured to output the pseudorandom spread spectrum signal;

a clock divider configured to receive the clock signal and divide the clock signal by at least a portion of the pseudorandom spread spectrum signal to generate and output a divided clock signal;

a ramp generator configured to receive the divided clock signal and generate the periodic analog-type waveform from the divided clock signal;

an adder configured to modulate the periodic analog-type waveform with the pseudorandom spread spectrum signal to generate the dual random spread spectrum signal; and

an oscillator configured to receive the dual random spread spectrum signal and to generate the pulse width modulated signal in accordance with the dual random spread spectrum signal.

18. The system of claim 17, wherein the degree of frequency variation of the dual random spread spectrum signal between successive cycles of the clock signal is greater than the degree of frequency variation of the periodic analog-type waveform or the pseudorandom spread spectrum signal, respectively.

19. The system of claim 17, wherein the oscillator generates the pulse width modulated signal that varies in frequency between successive cycles of the clock signal by programming a current source to charge a capacitor with a current determined at least in part from the dual random spread spectrum signal.

20. The system of claim 15, wherein the pulse width modulated signal mitigates the generation of electromagnetic interference in the turning on and off of the power transistors in a high frequency band based on components of the dual random spread spectrum signal attributable to the first signal and in a low frequency band based on components of the dual random spread spectrum signal attributable to the second signal.

21. The system of claim 15, wherein the first signal is a periodic analog type waveform, and wherein the second signal is a pseudorandom spread spectrum signal.

22. The system of claim 15, wherein the first signal is a periodic analog-type waveform, and wherein the second signal is a second periodic analog-type waveform.

23. The system of claim 15, wherein the first signal is a triangular ramp signal at a first frequency, and wherein the second signal is a triangular ramp signal at a second frequency.

24. The system of claim 15, further comprising:

a load;

a switch mode power supply coupled to the load and the pulse width modulation generator, wherein the switch mode power supply comprises a power transistor, and wherein the power transistor is switched on and off at least partially according to the pulse width modulation signal to generate an output voltage provided to the load.

Background

A Switched Mode Power Supply (SMPS) delivers power from an input power source to a load by switching one or more power transistors coupled via a switching node/terminal to an energy storage element (such as an inductor/transformer and/or capacitor) that is capable of being coupled to the load. The power transistor may be included in a power converter that includes or is capable of being coupled to an energy storage element. The SMPS may include an SMPS controller to provide one or more gate drive signals to the power transistor. SMPS operate at switching frequencies that can generate noise, resulting in electromagnetic interference (EMI) at the switching frequencies and their harmonic frequencies.

Disclosure of Invention

At least some aspects of the present disclosure provide a circuit. In at least some examples, a circuit includes a Linear Feedback Shift Register (LFSR), a clock divider, a ramp generator, an adder, and an oscillator. The LFSR includes a clock input terminal configured to receive a clock signal, a first output terminal, and a second output terminal. The clock divider includes a clock input terminal configured to receive a clock signal, a first input terminal coupled to a first output terminal of the LFSR, a second input terminal coupled to a second output terminal of the LFSR, and an output terminal. The ramp generator includes an input terminal and an output terminal coupled to the output terminal of the clock divider. The adder includes a first input terminal coupled to the output terminal of the ramp generator and a second input terminal coupled to the first output terminal of the LFSR and an output terminal. The oscillator includes a first input terminal coupled to the output terminal of the adder and an output terminal.

Other aspects of the disclosure provide a circuit. In at least some examples, a circuit includes an LFSR, a clock divider, a ramp generator, an adder, and an oscillator. The LFSR is clocked by a clock signal and is configured to output pseudo-random values in a digital data format. The clock divider is configured to receive a clock signal and divide the clock signal by a pseudorandom value to generate and output a divided clock signal. The ramp generator is configured to receive the divided clock signal, generate a ramp signal according to the divided clock signal, and output the ramp signal in a digital data format. The adder is configured to modulate the ramp signal with a pseudorandom value to generate a dual random spread spectrum signal. The oscillator is configured to receive the dual random spread spectrum signal and generate a pulse width modulated signal based on the dual random spread spectrum signal.

At least some aspects of the present disclosure provide a system. In some examples, a system includes a Pulse Width Modulation (PWM) generator configured to generate a PWM signal. The PWM generator generates a PWM signal by: generating a first signal having a first jitter profile and a first frequency bandwidth; generating a second signal having a second jitter profile and a second frequency bandwidth greater than the first frequency bandwidth; modulating a second signal with a first signal to generate a dual random spread spectrum signal; and generating a pulse width modulated signal based on the dual random spread spectrum signal.

Drawings

For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

FIG. 1 shows a block diagram of an illustrative system according to various examples;

figure 2 shows a schematic diagram of an illustrative SMPS, according to various examples;

FIG. 3 shows a schematic diagram of an illustrative Pulse Width Modulation (PWM) generator, according to various examples;

FIG. 4 shows a diagram of illustrative signal waveforms, according to various examples;

FIG. 5 shows a diagram of illustrative signal waveforms, according to various examples;

FIG. 6 shows a diagram of illustrative signal waveforms, according to various examples;

FIG. 7 shows a flow diagram of an illustrative method according to various examples; and is

FIG. 8 shows a table of illustrative pseudo-code, in accordance with various embodiments.

Detailed Description

In a Switched Mode Power Supply (SMPS), a power transistor is controlled (e.g., switched) to turn on and off at a particular frequency, referred to as the switching frequency. The nature of the switching behavior of the power transistor causes and/or generates electromagnetic energy (e.g., conducted and/or radiated) spectral frequency spurs at each of the switching frequency and its harmonic frequencies. These spectral frequency spurs are referred to as electromagnetic interference (EMI) with the greatest amount of energy at the switching frequency. The generation of such sound can sometimes be undesirable. In at least some instances, the maximum amount of EMI energy permitted in a particular system at a particular frequency is limited. For example, various standards or government regulations limit the maximum amount of EMI energy permitted at a particular frequency in a system, such as an automobile, audio equipment, or other application, in which excessive EMI at the particular frequency may be undesirable and/or inhibit normal or intended operation of the system.

There are some techniques for reducing the peak energy of EMI at the switching frequency. For example, various dithering techniques spread EMI energy across multiple frequencies (e.g., frequency bands). These dithering techniques are sometimes referred to as spread spectrum dithering. Spread spectrum dithering varies the switching frequency between a plurality of values over a predetermined bandwidth to spread the spectral energy of the EMI over the predetermined bandwidth. This prevents focusing of the spectral energy at the switching frequency and reduces the peak spectral energy at the switching frequency. Some dithering techniques are more suitable for a particular frequency range than others. For example, analog dithering techniques that generate triangular ramp signals may provide optimal performance for dithering at low frequencies. Digital dithering techniques, such as pseudo-random spread spectrum (PRSS) dithering, may provide optimal performance for dithering at high frequencies. However, dithering techniques that provide optimal performance for one frequency range (e.g., high or low) may not provide optimal performance for other frequency ranges, and may in some examples reduce system performance in other frequency ranges.

Aspects of the present disclosure provide for generating a dual random spread spectrum Dither (DRSS) signal using multiple dither profiles (e.g., dither signal shapes) or techniques simultaneously. For example, the first signal is generated to represent an analog signal or a digital signal, and is a first modulation signal for modulating the output of the oscillator and the output is a plurality of digital bits. Alternatively, in some examples, the first signal is output in an analog format. In some examples, the first signal represents an analog triangular ramp, as discussed above. The second signal is generated to represent an analog signal or a digital signal, and the first signal is modulated by the second signal to generate the DRSS signal. In some examples, the second signal is a PRSS signal. In some examples, the first signal is modulated by the second signal by adding the first signal to the second signal. In some examples, the DRSS signal output is a plurality of digital bits (e.g., data in a digital data format). In at least one example, generating the DRSS signal by modulating the first signal with the second signal is referred to as DRSS dithering. In another example, the result of modulating the first signal with the second signal is further modulated by another signal to generate a DRSS signal. In still other examples, any number of signals, each optimized for varying frequencies, are modulated together or otherwise combined to form a DRSS signal. When the DRSS signal is generated by combining more than two signals, the DRSS signal may be renamed to reflect the multiple combined signals. The oscillator is controlled in accordance with the DRSS signal to generate a Pulse Width Modulation (PWM) clock signal for controlling another component, e.g., as used to control the power converter, set a latch or other component that controls the power converter or yet another component, etc. For consistency and clarity of description, in the present disclosure, the first signal contains digital bits representing the form of a triangle wave, and the second signal is a PRSS signal. However, the teachings of the present disclosure are not limited to this single example, and the first signal and the second signal may each be any signal suitable for use in modulation and/or dithering. For example, in various implementations, the first signal is in a triangular waveform and the second signal is in a triangular waveform, the first signal is in a triangular waveform and the second signal is a PRSS signal, the first signal and the second signal are each a PRSS signal, the first signal is a PRSS signal and the second signal is a triangular waveform, either the first signal or the second signal is an adaptive random spread spectrum signal (ARSS), a periodic analog type waveform, and so forth. In at least some examples, the ARSS is defined as a triangular shaped modulation profile having a modulation period (e.g., a triangle width) that modulates over time. In some examples, the modulation period changes at the end of each ramp or at any other point in the cycle. Additionally, in some examples, the modulation period is a fixed value. In at least some examples, the periodic analog-type waveform is an analog or digital representation of an analog signal and can occur in a variety of shapes, including triangular, sinusoidal, exponential, and the like.

In some examples, the first signal is optimized for performing spread spectrum dithering in a low frequency band, such as a frequency band of about 150 kilohertz (kHz) to about 30 megahertz (MHz). Similarly, in some examples, the second signal is optimized for performing spread spectrum dithering in a high frequency band, such as a frequency band of about 30MHz to about 108 MHz. Thus, in at least some examples, modulating the first signal with the second signal to generate the DRSS signal allows the DRSS signal to be optimized for the low band and the high band. For example, generating the PWM signal according to the DRSS signal reduces peak energy of EMI in a low frequency band (e.g., generated by the first signal) and a high frequency band (e.g., generated by modulating the first signal with the second signal) when the devices are switched according to the PWM signal.

Turning now to fig. 1, a block diagram of an illustrative system 100 is shown. In at least some examples, system 100 is an electronic device that includes a power supply 102, an SMPS 104, and a load 106. In at least some examples, system 100 represents a consumer electronic device, such as a laptop computer, a smartphone, an audio device, a wearable device, and the like. In other examples, system 100 represents a system or subsystem in a transport vehicle, such as an automobile, aircraft, ship, or the like. In general, system 100 represents any system that desires and/or requires compliance with a particular control specification or standard that limits the peak energy of EMI at a particular frequency. One such standard is the International special Radio interference Committee (CISPR)25, which specifies peak energy limits for various vehicles at specific frequencies. Other such standards or peak energy limits may be specified in emission standards established and/or promulgated by the Federal Communications Commission (Federal Communications Commission) or other regulatory bodies in the united states.

In some examples, power source 102 is a rechargeable or non-rechargeable battery or a depletable power source that outputs VIN. In other examples, power supply 102 is in the form of a mains power supply, such as the output of a Direct Current (DC) transformer that receives an Alternating Current (AC) or other mains power supply and generates a DC output signal as VIN. In some examples, the load 106 is any one or more electrical and/or mechanical components that receive VOUT from the SMPS 104 and operate at least partially according to VOUT. In at least one example, SMPS 104 includes controller 108 and power converter 110. Power converter 110 is any suitable power converter, such as a buck power converter, a boost power converter, or a buck-boost power converter. The controller 108 generates a PWM that at least partially controls the operation of the power converter 110. In at least some examples, the controller 108 generates PWM based on the DRSS signal to limit EMI generated by the power converter 110 when generating VOUT, as described herein.

Turning now to fig. 2, a schematic diagram of an illustrative SMPS 104 is shown. Although described as a component of system 100, SMPS 104, in various examples, is suitable for implementation in other systems or devices that receive VIN and generate VOUT by switching one or more components. In at least some examples, SMPS 104 includes controller 108 and power converter 110. In at least some examples, power converter 110 includes a Field Effect Transistor (FET)202, a FET 204, and an inductor 206. As shown in fig. 2, the power converter 110 is a current-mode buck switching converter. However, the teachings of the present disclosure are equally applicable to boost switching converters and buck-boost switching converters, as well as voltage mode converters of buck, boost or buck-boost topologies or any other suitable power converter topology. In at least some examples, the controller 108 includes a resistor 208, a resistor 210, an amplifier 212, a comparator 214, a latch 216, a PWM generator 218, and an adder 220.

In an example architecture, FET 202 has a drain terminal coupled to node 224, a source terminal coupled to node 226, and a gate terminal. FET 204 has a drain terminal coupled to node 226, a source terminal coupled to ground node 230, and a gate terminal. Inductor 206 is coupled between node 226 and node 228. Resistor 208 is coupled between node 228 and node 232. Resistor 210 is coupled between node 232 and ground node 230. Amplifier 212 has a first input terminal (e.g., a negative or inverting input terminal) coupled to node 232, a second input terminal (e.g., a positive or non-inverting input terminal) coupled to node 234, and an output terminal. The comparator 214 has a first input terminal (e.g., a positive or non-inverting input terminal), a second input terminal (e.g., a negative or inverting input terminal) coupled to the output terminal of the amplifier 212, and an output terminal. Latch 216 has a reset input terminal, a set input terminal, and an output terminal coupled to the output terminal of comparator 214. PWM generator 218 has an input terminal coupled to node 238, a first output terminal coupled to the set input terminal of latch 216, and a second output terminal coupled to the input terminal of adder 220. The adder 220 further has another input terminal configured to receive a signal (IL) indicative of the current flowing through the power converter 110. An output terminal of the latch 216 is coupled to the gate terminal of the FET 202. The output terminal of latch 216 is further coupled to the gate terminal of FET 204 through inverter 222. In other examples, inverter 222 is omitted, and the inverting output terminal (not shown) of latch 216 is coupled to the gate terminal of FET 204.

In an example of operation, the controller 108 controls the power converter to generate an output Voltage (VOUT) at node 228 based at least in part on an input Voltage (VIN) received at node 224. Based on the PWM output signal (PWM2) of latch 216, FET 202 and FET 204 are controlled to be conductive or non-conductive, thereby generating VOUT from VIN. Resistor 208 and resistor 210 together form a voltage divider having an output at node 232. The signal present at node 232 is a feedback signal (FB) that is a scaled representation of VOUT that is scaled based on a ratio of the resistances of resistor 208 and resistor 210. Amplifier 212 is an ERROR amplifier that outputs a signal ERROR indicative of the difference between FB and a reference Voltage (VREF) received at node 234 indicative of a desired value of VOUT. Adder 220 receives IL and a slope compensation signal (COMP) and generates an output signal. The comparator 214 receives ERROR and the output signal of the adder 220 and compares the received signals. When the output signal of adder 220 exceeds ERROR, comparator 214 outputs a signal having a logic high value (COMP 2). When the output signal of adder 220 is less than ERROR, comparator 214 outputs COMP2 having a logic low value. Latch 216 receives COMP2 at the reset input terminal and the signal PWM1 at the set input terminal. When PWM1 is asserted, latch 216 outputs PWM2 with an asserted value. When COMP2 is asserted, latch 216 outputs PWM2 with a deasserted value. When PWM2 is asserted, FET 202 is controlled to be conductive and FET 204 is controlled to be non-conductive. Similarly, when PWM2 is de-asserted, FET 202 is controlled to be non-conductive and FET 204 is controlled to be conductive.

The PWM generator 218 is configured to receive a clock signal (CLK) at node 238 and generate PWM1 and COMP. For example, based on CLK, PWM generator 218 generates PWM1 as a modulation of at least two signals. CLK is generated according to any suitable circuitry and according to any suitable process, the scope of which is not limited herein. As illustrated in fig. 2, in at least some implementations, PWM1 is a jittered clock signal and COMP is a jitter compensation signal. In one example, PWM generator 218 receives CLK and divides the frequency of CLK to generate a divided clock signal. In at least one embodiment, the PWM generator 218 generates a triangular ramp signal or a signal having any other suitable profile based on the divided clock signal. In some examples, PWM generator 218 generates another triangular ramp signal or a signal having any other suitable profile based on CLK or based on the second divided clock signal. In other examples, PWM generator 218 generates a PRSS signal, for example, output by a register, such as a Linear Feedback Shift Register (LFSR). The PWM generator 218 then sums the generated signals (e.g., ramp signal + ramp signal, ramp signal + PRSS signal, etc.) to generate the DRSS signal. In some examples, the DRSS signal is output by PWM generator 218 as COMP. The PWM generator 218 further generates a PWM1 according to the DRSS signal, e.g., trimming an oscillator (not shown) that generates the PWM1 according to the DRSS signal.

Turning now to fig. 3, a schematic diagram of an illustrative PWM generator 300 is shown. In at least some examples, PWM generator 300 is suitable for implementation in any device or system that receives CLK and generates a dithered PWM signal. For example, the PWM generator 300 is suitable for implementation in some SMPS architectures, such as implemented as the PWM generator 218 in the SMPS 104 of the present disclosure. In other examples, the PWM generator 300 is suitable for implementation in other systems that generate PWM signals according to CLK, but not SMPS. For example, in a device comprising an input pin (such as a clock synchronization or sync pin or input) for providing a clock signal, the PWM generator 300 is adapted to be coupled at an output terminal to the input pin for providing a PWM signal. Additionally, at least some of the signals present in PWM generator 300 are illustrated in diagram 400 of fig. 4. Thus, an understanding of the operation of the PWM generator 300 illustrated in the schematic diagram of fig. 3 is further enhanced by looking at the signals illustrated in fig. 4. The signals illustrated in fig. 4 correspond in name to the signals described elsewhere herein with respect to generation and function.

In at least one example, PWM generator 300 includes a clock divider 302, a ramp generator 304, a register 306, an adder 308, and an oscillator 310. In at least some examples, register 306 is a linear feedback shift register clocked by CLK and having multiple output taps that each output one bit of digital data. In at least some examples, the register 306 is not included within the PWM generator 300, but rather the PWM generator 300 is implemented and the PWM generator 300 is configured as a component of a system coupled thereto. In at least one example, clock divider 302 is configured to receive CLK and generate CLK _ DIV. Clock divider 302 is further configured to receive one or more data bits output by register 306. In at least some examples, which particular data bits of output register 306 (e.g., which locations in register 306) are a matter of design choice. In at least some examples, clock divider 302 generates CLK DIV by dividing CLK according to at least some of the data bits received from registers 306. Because clock divider 302 generates CLK _ DIV from the data bits received from registers 306, the frequency of CLK _ DIV varies as the value of the data bits output by registers 306 changes. In this way, the frequency of CLK _ DIV varies with clock period.

Ramp generator 304 is coupled to clock divider 302 and is configured to receive CLK _ DIV. Based on CLK _ DIV, the RAMP generator 304 generates a RAMP signal and outputs a plurality of data BITs (e.g., RAMP _ BIT0, RAMP _ BIT1 … … RAMP _ BITX) representing the value of the RAMP signal for each clock cycle of CLK _ DIV. In at least some examples, the data bits output by the ramp generator 304 comprise a digital representation of an analog signal (e.g., a digital representation of a triangular waveform). However, in other examples, ramp generator 304 outputs the ramp signal in analog format. The adder 308 receives at least some of the data BITs output by the ramp generator 304 and the data BITs output by the register 306, adds the data BITs output by the register 306 and the data BITs output by the ramp generator 304 to generate a DRSS signal, and outputs the DRSS signal as a plurality of data BITs (DRSS _ BIT0, DRSS _ BIT1 … … DRSS _ BITX). In at least some examples, the data BITs (e.g., PR _ BIT0, PR _ BIT1, etc.) output by register 306 include the PRSS signal.

Oscillator 310 is configured to receive the plurality of data bits output by adder 308. In at least some examples, oscillator 310 generates the PWM signal by charging and discharging a capacitor (not shown). In this manner, in at least some examples, the output terminal of the oscillator 310 is coupled to an output node of the PWM generator 300, or an output node of the PWM generator 300. In at least some examples, oscillator 310 charges a capacitor by providing current to the capacitor via a programmable current source (not shown). The current output by the variable current source, and thus the charge rate of the capacitor, is determined from the plurality of data bits output by the adder 308. In this way, the PWM signal is generated according to the plurality of data bits output by the adder 308 such that it varies according to the ramp signal generated by the ramp generator 304 and the output bits of the register 306.

Turning briefly to fig. 5, an illustrative diagram 500 of signal waveforms is shown. Diagram 500 illustrates signal 505, signal 510, and signal 515. In at least one example, signal 505 is the ramp signal generated by ramp generator 304 of fig. 3, signal 510 is the PRSS signal output by register 306 of fig. 3, and signal 515 is the output of adder 308 of fig. 3. In at least some examples, signal 515 further indicates the output of oscillator 310, such that signal 515 indicates a switching frequency (f _ sw) that will control a power converter receiving the output of oscillator 310. The y-axis of graph 500 represents frequency and the x-axis of graph 500 represents time. During the time period shown as t1 in diagram 500, f _ sw remains substantially constant. During this time period, dithering according to the present disclosure is deactivated. During the time period shown as t2 in graph 500, dithering is enabled according to the present disclosure, and the value of the switching frequency f _ sw during t2 varies within about 0.156 times the bandwidth of f _ sw during t 1. Additionally, in at least some examples, signal 505 varies in frequency in a bandwidth of f _ h and signal 510 varies in frequency in a bandwidth of f _ l, where f _ l is less than f _ h.

Returning to fig. 3, in at least some examples, PWM generator 300 includes one or more components (not shown) configured to bypass adder 308. For example, in some cases, it may be preferable to bypass adder 308 to characterize, monitor, or otherwise observe the data bits output by ramp generator 304. In other examples, components configured to bypass the adder 308 enable the PWM generator 300 to be selectively configured to operate in either a DRSS mode or an ARSS mode. For example, in one implementation, a multiplexer is coupled between each output terminal of the register 306 and the adder 308. For example, each multiplexer receives a respective data bit output by register 306 at a first input terminal, a second input terminal of the multiplexer is coupled to a ground node, and an output terminal of the multiplexer is coupled to adder 308. Each multiplexer is configured to receive the same select signal so that the PWM generator 300 can be configured by selecting the second input of each of the multiplexers to bypass the generation of the DRSS signal and instead generate the periodic analog type waveform, as described above. In another example, a multiplexer is coupled between each output terminal of ramp generator 304 and oscillator 310. For example, each multiplexer receives a respective data bit output by the ramp generator 304 at a first input terminal, a second input terminal of the multiplexer is coupled to a corresponding output of the adder 308, and an output terminal of the multiplexer is coupled to the oscillator 310. Each multiplexer is configured to receive the same select signal so that the PWM generator 300 can be configured by selecting the second input of each of the multiplexers to bypass the generation of the DRSS signal and instead generate the periodic analog type waveform, as described above.

In some examples, such as a current mode power converter, the slope compensation signal is generated by a controller for compensating an error signal generated by the controller for controlling the power converter. In such examples, the slope compensation signal is fine-tuned based on the same input as received by oscillator 310 (e.g., DRSS _ BIT0, DRSS _ BIT1 … … DRSS _ BITX of fig. 3, collectively illustrated in fig. 2 as signal COMP). In at least some examples, trimming a signal includes modifying and/or generating a value of the signal at a particular point in time based on a value of the signal on which the trimming is based. Trimming the slope compensation signal according to the same input as received by the oscillator 310 minimizes ripple in the output voltage of the power converter. In other examples, such as a voltage mode power converter, the voltage ramp is instead trimmed according to the same input as received by the oscillator 310, again minimizing ripple in the output voltage of the power converter.

Additionally, in at least some examples, although not shown in fig. 3, PWM generator 300 includes a second ramp generator, and may further include a second clock divider. The second ramp generator and/or the second clock divider together generate a second ramp signal in a manner substantially similar to clock divider 302 and ramp generator 304. In some examples, the output of the second ramp generator has a higher frequency than the output of ramp generator 304. In such examples, the output of the second ramp generator is provided to adder 308 in place of the output of register 306 (e.g., in place of PR _ BIT0 and PR _ BIT 1).

Turning now to fig. 6, an illustrative diagram 600 of signal waveforms is shown. In at least some examples, diagram 600 illustrates a plurality of signals present in circuit 300 of fig. 3. Accordingly, at least some of the components and/or signals of fig. 3 may be referenced in describing diagram 600. Diagram 600 illustrates signal 605, signal 610, and signal 615. In at least one example, signal 605 is a ramp signal generated by ramp generator 304 of fig. 3, signal 610 is another ramp signal, and signal 615 is the output of adder 308 of fig. 3 (e.g., when adder 308 receives signal 605 and signal 610 as inputs, received signal 610 replaces the PRSS signal). In at least some examples, signal 615 is further indicative of an output of oscillator 310, such that signal 615 is indicative of an f _ sw of a power converter controlled at least in part according to the output of oscillator 310. The y-axis of graph 600 represents frequency and the x-axis of graph 600 represents time. As illustrated in diagram 600, in at least some examples, the bandwidth of signal 605 is greater than the bandwidth of signal 610, and the bandwidth of signal 615 is substantially equal to the bandwidth of signals 605 and 610 added together.

Turning now to fig. 7, a flow diagram of an illustrative method 700 is shown. In at least some examples, method 700 is a method of PWM signal generation. In some examples, the frequency of the PWM signal changes with each clock cycle. For example, in at least some implementations, the PWM signal is generated according to DRSS dithering that combines multiple spreading schemes or modulations in generating the PWM signal. In some examples, method 700 is implemented in a PWM generator, such as PWM generator 300 of fig. 3.

At operation 705, a clock signal is received. In at least some examples, the clock signal is CLK, as described above. In some examples, the clock signal is an output of an oscillator, a PWM generator, or another circuit capable of generating a clock signal. At operation 710, a clock signal is divided to form a divided clock signal. In at least some examples, the divided clock signal is CLK _ DIV, as described above. In at least some examples, the clock signal is divided according to the output of the linear feedback shift register. In other examples, the clock signal is divided by any other suitable value. In at least some examples, the value varies over clock cycles to prevent the divided clock signal from remaining at the same frequency for a plurality of consecutive clock cycles.

At operation 715, a first signal is generated according to a dithering scheme. The first signal is, for example, an analog ramp, or a plurality of data bits representing an analog ramp. In other examples, the first signal is an ARSS signal or a periodic analog type waveform, as described above. In yet other examples, the first signal is a PRSS signal. In at least one embodiment, the first signal is generated by a ramp generator. A first signal is generated from the divided clock signal generated at operation 710 such that the frequency of the first signal varies with clock period.

At operation 720, a second signal is generated according to a dithering scheme. The second signal is, for example, an analog ramp, or a plurality of data bits representing an analog ramp. In other examples, the second signal is an ARSS signal or a periodic analog type waveform, as described above. In yet other examples, the second signal is a PRSS signal. In some examples, the dithering scheme at operation 720 is the same as the dithering scheme at operation 715. In other examples, the dithering scheme at operation 720 is different than the dithering scheme at operation 715. In at least one implementation, the second signal is generated, for example, based on one or more bits output by a linear feedback shift register, such that the one or more bits form a PRSS signal.

At operation 725, the first signal is modulated by or with the second signal. In some examples, the first signal is modulated by the second signal by adding the second signal to the first signal. In some examples, the modulated first signal is a DRSS signal. In at least some examples, modulating the first signal with the second signal combines a dithering scheme of the first signal with a dithering scheme of the second signal. In some examples, combining the dithering scheme of the first signal with the dithering scheme of the second signal results in a greater variation in switching frequency between successive clock cycles than alternative methods using a single dithering scheme (e.g., ARSS, PRSS, or analog dithering).

At operation 730, the oscillator is trimmed to generate the PWM signal based on the DRSS signal generated at operation 725. In at least some examples, trimming the oscillator according to the DRSS signal causes the oscillator to generate a PWM signal having a frequency that changes as the value of the DRSS signal changes. The frequency is changed according to the first signal generated at operation 715 and the second signal generated at operation 720. Varying the frequency of the PWM signal according to the first signal and the second signal enables a switching assembly controlled according to the PWM signal to improve EMI performance in a frequency range in which the first signal is optimized and a frequency range in which the second signal is optimized. For example, when the first signal is an analog ramp signal, the first signal is optimized for improving EMI performance at low frequencies. Similarly, when the second signal is a PRSS signal, the second signal is optimized for improved EMI performance at high frequencies. Thus, by modulating the first signal with the second signal at operation 725 and generating a PWM signal from this modulated signal at operation 730, the PWM signal becomes optimized for improving EMI performance at low and high frequencies.

At operation 735, the power converter is controlled according to the PWM signal to generate an output voltage from the input voltage. For example, the PWM signal drives a gate terminal of at least one power transistor of the power converter (or drives a gate driver that in turn drives the gate terminal) to cause the power transistor to turn on and off, thereby enabling or disabling current flowing through the power transistor to generate VOUT.

Turning now to FIG. 8, a table 800 of illustrative pseudo-code is shown. In at least some examples, the present disclosure may be implemented, at least in part, via software. For example, at least some of the operations of method 700 of fig. 7 may be performed by programming a processor to perform particular tasks. Table 800 illustrates one example of pseudo code for performing such programming. However, the pseudo code of table 800 is but one method for programming a processor to perform the functions of the present disclosure, and other methods that achieve the same or similar results are also within the scope of the present disclosure.

As illustrated in table 800, variables clk _ frequency, clk _ differentiated _ frequency _2, and pseudo-random are defined. A random number (rand) is generated. Subsequently, a first ramp signal (ramp) is generated and a second ramp signal (ramp _2) is generated. DRSS is then generated by adding the ramp to the rand (e.g., to modulate the ramp according to the rand, which in some examples is a PRSS signal) or by adding the ramp to ramp _ 2. The frequency of the clock signal is modified based on the DRSS.

In the preceding discussion, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to. The term "coupled" is used throughout this specification. The terms may encompass a connection, communication, or signal path that achieves a functional relationship consistent with the description of the disclosure. For example, if device a generates a signal to control device B to perform an action, in a first example device a is coupled to device B, or in a second example device a is coupled to device B via intervening component C, if intervening component C does not substantially alter the functional relationship between device a and device B, such that device B is controlled by device a via the control signal generated by device a. A device that is "configured to" perform a task or function may be configured (e.g., programmed and/or hardwired) to perform the function when manufactured by a manufacturer, and/or may be configured (or reconfigurable) by a user to perform the function after manufacture, and/or other additional or alternative functions. The configuration may be through firmware and/or software programming of the device, through construction and/or layout of hardware components and interconnections of the device, or a combination thereof. Further, circuits or devices that are said to include certain components may alternatively be configured to be coupled to those components to form the described circuitry or devices. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and/or an Integrated Circuit (IC) package) and may be configured to be coupled to at least some of the passive elements and/or sources to form the described structure at manufacture or after manufacture, e.g., by an end user and/or a third party.

Although certain components are described herein as belonging to a particular processing technology (e.g., FET, Metal Oxide Semiconductor FET (MOSFET), n-type, p-type, etc.), these components may be swapped with components of other processing technologies (e.g., replacing the FET and/or MOSFET with a BJT, replacing the n-type with p-type, or vice versa, etc.) and the circuit including the replaced components reconfigured to provide the desired functionality at least partially similar to that available prior to component replacement. Unless otherwise stated, a component described as a resistor generally represents any element or elements coupled in series and/or parallel to provide the amount of impedance represented by the described resistor. Moreover, use of the phrase "ground voltage potential" in the foregoing discussion is intended to include base grounds, ground grounds, floating grounds, virtual grounds, digital grounds, general grounds, and/or any other form of ground connection suitable or appropriate for the teachings of the present disclosure. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means +/-10% of the stated value.

The above discussion is meant to be illustrative of the principles and various examples of the present disclosure. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the disclosure be construed as including all such variations and modifications.