阅读说明：本技术 维持稳定计时的装置和方法 (Apparatus and method for maintaining stable timing ) 是由 纳撒尼尔·奥古斯特 穆罕默德·埃尔古斯 本杰明·戈登 陈财源 于 2020-05-08 设计创作，主要内容包括：在意外时钟停止之前和之后,各种实施例的装置和方法利用电路组件的独特布置向存储器模块提供稳定而连续的时钟,这些电路组件包括时钟检测器电路、时钟平滑电路以及一个或多个PLL。在检测到已停止的主机时钟时,第一PLL从板载晶体振荡器无缝切换到备用参考时钟。时钟平滑电路允许第一PLL保持稳定的相位和频率,而不引起比锁定的PLL的自然抖动更大的短时脉冲波干扰或周期偏移；一个或多个可选的下游PLL可以驱动附加的时钟域。(Before and after an unexpected clock stop, the apparatus and methods of the various embodiments provide a stable and continuous clock to a memory module with a unique arrangement of circuit components, including a clock detector circuit, a clock smoothing circuit, and one or more PLLs. Upon detecting a stopped host clock, the first PLL seamlessly switches from the on-board crystal oscillator to the standby reference clock. The clock smoothing circuit allows the first PLL to maintain a stable phase and frequency without causing short-time pulse wave interference or period drift that is greater than the natural jitter of the locked PLL; one or more optional downstream PLLs may drive additional clock domains.)

1. An apparatus, comprising:

a first circuit for selecting one of a first clock or a second clock;

a Phase Locked Loop (PLL) to receive an output of the first circuit as a reference clock of the PLL; and

a second circuit coupled to the PLL, wherein the second circuit is to detect whether the first clock is present and provide a select signal to the first circuit to:

selecting the first clock as an output of the first circuit in the presence of the first clock; and

in the absence of the first clock, selecting the second clock as an output of the first circuit.

2. The apparatus of claim 1, comprising a third circuit to adjust an upper pulse and a lower pulse from a phase detector of the PLL when the first circuit selects the second clock.

3. The apparatus of claim 1, comprising a fourth circuit to divide a third clock to generate the first clock.

4. The apparatus of claim 3, wherein the third clock is generated by a host processor.

5. The apparatus of claim 1, wherein the second clock is generated by a crystal oscillator, wherein a frequency of the first clock is substantially the same as a frequency of the second clock.

6. The device of claim 1, wherein the first circuit comprises a multiplexer.

7. The apparatus of claim 1, wherein the second circuit comprises:

a first flip-flop having a clock input receiving the first clock and an output coupled to the input via an inverter;

a second flip-flop having a clock input receiving an output of the PLL, an input coupled to an output of the first flip-flop, and an output;

a third flip-flop having a clock input receiving an output of the PLL, an input coupled to an output of the second flip-flop, and an output; and

combinational logic to receive an output of the second flip-flop and an output of the third flip-flop, wherein an output of the combinational logic provides the select signal.

8. The apparatus of claim 2, wherein the third circuit comprises:

a first programmable delay line for receiving the top pulse;

a first inverter coupled to an output of the first programmable delay line;

a first combinational logic to receive the top pulse and an output of the first inverter, wherein an output of the first combinational logic provides an adjusted top pulse;

a second programmable delay line for receiving the lower pulse;

a second inverter coupled to an output of the first programmable delay line; and

second combinatorial logic to receive the lower pulse and an output of the second inverter, wherein an output of the second combinatorial logic provides an adjusted lower pulse.

9. The apparatus of any of claims 1 to 8, comprising a clock distribution network coupled to an output of the PLL.

10. The apparatus of claim 9, wherein the reference clock is a first reference clock, wherein the PLL is a first PLL, wherein the apparatus comprises:

a frequency divider for dividing the output of the first PLL and generating a second reference clock; and

a second PLL to receive the second reference clock.

11. The apparatus of claim 10, wherein the clock distribution network is a first clock distribution network, wherein the apparatus comprises a second clock distribution network coupled to an output of the second PLL, and wherein an output of the second clock distribution network is received by a memory.

12. The apparatus of claim 10, wherein the first PLL and the second PLL are one of analog PLLs or digital PLLs.

13. An apparatus, comprising:

a Phase Locked Loop (PLL) to receive a reference clock and generate an output clock, the output clock being used directly or indirectly to write data to a memory; and

circuitry to detect a valid first clock and to cause a multiplexer to provide a second clock as the reference clock when the first clock is invalid.

14. The apparatus of claim 13, wherein the circuit is a first circuit, and wherein the apparatus comprises a second circuit to adjust a top pulse and a bottom pulse from the PLL when the multiplexer provides the second clock as the reference clock.

15. The apparatus of claim 14, comprising a third circuit to divide the first clock to generate a third clock, wherein the third clock and the second clock are input to the multiplexer.

16. The apparatus of any of claims 13 to 15, wherein the first clock is generated by a host processor.

17. The apparatus of claim 15, wherein the second clock is generated by a crystal oscillator, and wherein a frequency of the third clock is substantially the same as a frequency of the second clock.

18. A system, comprising:

a processor;

a memory module coupled to the processor, wherein the processor sends a first clock to the memory module, wherein the memory module comprises the apparatus of any one of claims 1 to 12; and

a wireless interface to allow the processor to communicate with another device.

19. A system, comprising:

a processor;

a memory module coupled to the processor, wherein the processor sends a first clock to the memory module, wherein the memory module comprises the apparatus of any of claims 13-17; and

a wireless interface to allow the processor to communicate with another device.

20. A method, comprising:

selecting, by a first circuit, one of a first clock or a second clock;

receiving, by a Phase Locked Loop (PLL), an output of the first circuit as a reference clock of the PLL; and

detecting, by a second circuit coupled to the PLL, whether a first clock is present and providing a select signal to the first circuit to:

selecting the first clock as an output of the first circuit in the presence of the first clock; and

in the absence of the first clock, selecting the second clock as an output of the first circuit.

21. The method of claim 20, comprising: adjusting, by a third circuit, an upper pulse and a lower pulse from a phase detector of the PLL when the first circuit selects the second clock.

22. The method of claim 20, comprising dividing, by a fourth circuit, a third clock to generate the first clock.

23. The method of claim 22, wherein the third clock is generated by a host processor.

The method of any of claims 20 to 23, comprising generating the second clock by a crystal oscillator, wherein a frequency of the first clock is substantially the same as a frequency of the second clock.

Background

Several types of solid-state, high-density, non-volatile memory (NVM) provide persistent storage in commercial computer systems. Such techniques includeAotang toy^TM(Optane^TM) DC permanent memory, spin transfer torque-magnetic random access memory (STT-MRAM), resistive RAM (ReRAM), NAND, Conductive Bridge RAM (CBRAM), or Phase Change Memory (PCM). These memories may be implemented on memory modules, with a memory controller linking the non-volatile memory to a processor (e.g., a Central Processing Unit (CPU)) via one or more high speed interfaces such as PCIe (peripheral component interconnect express) or DDR (double data rate interface). These memories rely on a stable clock for read and write purposes. A sudden or unexpected stop or disappearance of the clock may corrupt or stop the ongoing write operation.

Drawings

Embodiments of the present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

FIG. 1 illustrates a high-level architecture of a memory module having a means to maintain stable timing according to some embodiments of the present disclosure.

Figure 2 illustrates a timing architecture of a memory module having a means to maintain stable timing according to some embodiments of the present disclosure.

FIG. 3 illustrates an apparatus and associated timing diagram of a clock detector circuit according to some embodiments.

Fig. 4 illustrates a Phase Locked Loop (PLL) coupled to a clock smoothing circuit to adjust the up pulse and the down pulse, according to some embodiments.

Fig. 5 illustrates an apparatus and associated timing diagram for clock smoothing according to some embodiments.

Fig. 6 illustrates a graph showing clock exchange performance of a PLL and a clock smoothing circuit according to some embodiments.

Fig. 7 illustrates a smart device or computer system or SoC (system on a chip) having an apparatus to maintain stable timing according to some embodiments of the present disclosure.

Detailed Description

For timing and synchronization on the memory interface, the memory module relies on a direct clock from the host processor (e.g., CPU) or a reference clock signal from the host processor for on-board clock regeneration in the memory module. Host or module power failures, module dislocations, thermal trips, or other failures can cause the host clock to be accidentally and suddenly lost, which the memory module treats as an "accidental clock stop".

One problem arises when an unexpected clock stall occurs, where the host processor (or simply host) and the memory module may have completely different views of the state of the transaction. The host considers that all writes received by the memory module before the unexpected clock stops are securely stored in its persistent memory. However, the memory module, upon receiving the data, uses hundreds or thousands of clock cycles to complete the complex task of writing to the medium (e.g., persistent memory). In addition, since power loss may result in an unexpected clock stall, it is desirable for the memory module to complete these writes within a limited window of time that the retention capacitor can safely maintain the power supply level of the module. When a clock stall occurs after the host transaction is completed but before the memory module completes writing all the data, many problems of data integrity and security are found, including circuit instability, data loss, illegal register access, FIFO (first in first out) underflow, and firmware state corruption. These problems can be avoided if the module maintains a continuous and stable clock after an unexpected clock stop event.

To address this issue, after an unexpected clock stall, a reset sequence may be initiated, including locking or re-locking a Phase Locked Loop (PLL) to a standby reference clock source, such as an on-module crystal oscillator. Then, after the PLL is locked to a steady state, the output of the PLL drives the clock distribution network.

However, the reset sequence may require thousands of clock cycles to lock the PLL and enable downstream timing circuits such as DLLs (delay locked loops) or clock-crossing queues. A better utilization of this valuable time would be to complete the in-flight operations at predetermined times to meet the latency constraints required for a given protocol or a given physical media type. In addition, a long reset sequence requires the power supply of the module to remain on for a longer period of time after power loss, which can result in additional expense and area for additional holding capacitors or more expensive materials (such as tantalum).

Another way to solve the problem of sudden clock stops is to switch to a new clock source that directly drives the clock distribution network. The new clock source may be an on-module crystal oscillator or an on-die ring oscillator.

However, when turned on, the new clock source may introduce short-time pulse wave interference (glitch) into the clock distribution network, whether as short pulses, extended periods, or shortened periods. Short pulses may intermittently disappear at different physical locations in the memory controller; extended cycles may cause downstream delay lines to fail; and the shortened period may result in timing failure. In addition, unstable clocks may cause synchronous clock crossing (crossing) failures. Furthermore, if the new clock comes from an on-die ring oscillator, the inherent device and power supply noise may over time produce increasingly longer or shorter periods that cannot be corrected as the noise accumulates, eventually leading to timing failures.

Another solution is for a memory controller that synthesizes a clock from a host clock to handle unexpected clock stops by freezing the state of the PLL oscillator control to the voltage on the capacitor (for analog PLLs) or to a digital control word (for digital PLLs). However, in the case of a stopped clock scenario, no correction is made to the oscillator phase or frequency since the PLL is currently operating in open loop mode with a static oscillator control value. Device and power supply noise may cause over time extended or shortened periods that are uncorrectable as noise accumulates, eventually leading to timing failures.

Some embodiments solve the problem of sudden clock stops by ensuring a stable and continuous clock to the memory module even after an unexpected clock stop event, thus ensuring timely completion of operations on all modules and maintaining data integrity and security. Before and after an unexpected clock stop, the apparatus of some embodiments provides a stable and continuous clock to a memory module having a unique arrangement of circuit components including a clock detector circuit, a clock smoothing circuit, and one or more Phase Locked Loops (PLLs). Upon detecting a stopped host clock, the first PLL seamlessly switches to a standby reference clock, for example, from a board-mounted crystal oscillator. The clock smoothing circuit allows the first PLL to maintain a stable phase and frequency without causing short-time pulse wave interference or period drift that is greater than the natural jitter of the locked PLL. In some embodiments, one or more downstream PLLs may drive additional clock domains from the first PLL.

The apparatus and schemes of various embodiments enable a memory controller to continuously drive a clock distribution network of memory modules with a clock that is less disturbed by glitches of short-duration pulses that are stable in both frequency and phase before and after an unexpected clock stall. There may be no need to relock any PLLs and no time is wasted on the reset sequence used to relock the PLLs or adjust downstream clocking circuits such as DLLs or clock crossings. The apparatus and schemes of various embodiments ensure that ongoing operations are completed at the same predetermined time as normal operations, thus meeting the latency constraints required for a given protocol or physical media type, maintaining data integrity, and reducing the cost and board area of the holding capacitor. Other technical effects will be apparent from the various embodiments and drawings.

In the following description, several details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

It should be noted that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more constituent signal paths and/or have arrows at one or more ends to indicate primary information flow direction. Such indication is not intended to be limiting. Rather, these lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or logic cell. Any representative signal specified by design needs or preferences may actually include one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

Throughout the specification and claims, the term "connected" means a direct connection without any intermediate device, such as an electrical, mechanical, or magnetic connection between the things that are connected.

The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices.

The term "adjacent" herein generally refers to a location of one thing next to (e.g., next to or near but with one or more things in between) or next to (e.g., next to) another thing.

The term "circuit" or "module" may refer to one or more passive and/or active components arranged to cooperate with each other to provide a desired function.

The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a", "an" and "the" includes plural references. The meaning of "in" includes "in … …" and "on … …".

The term "scaling" generally refers to converting a design (schematic and layout) from one processing technique to another, and may subsequently reduce the layout area. In some cases, scaling also refers to scaling a design from one processing technique to another, and may subsequently increase layout area. The term "scaling" also generally refers to reducing or enlarging layouts and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up-i.e., respectively scaling down or scaling up) the signal frequency relative to another parameter (e.g., power supply level). The terms "substantially", "close", "about", "near", and "about" generally mean within +/-10% of a target value.

Unless otherwise specified, the use of the ordinal adjectives "first", "second", "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

For the purposes of this disclosure, the phrases "a and/or B" and "a or B" mean (a), (B), or (a and B). For the purposes of this disclosure, the phrase "A, B and/or C" means (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C).

The terms "left", "right", "front", "back", "top", "bottom", "over", "under", and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

It should be noted that those elements of a figure having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not so limited.

For purposes of the embodiments, the transistors in the various circuits and logic blocks described herein are Metal Oxide Semiconductor (MOS) transistors or derivatives thereof, where MOS transistors include drain, source, gate, and bulk terminals. Transistors and/or MOS Transistor derivatives also include tri-Gate and FinFET transistors, All Around Gate transistors (Gate All Around Transistor transistors), Tunneling FETs (TFETs), square or rectangular strip transistors, ferroelectric FETs (fefets), or other devices that perform a Transistor function, such as carbon nanotubes or spintronic devices. The symmetrical source and drain terminals of the MOSFET are the same terminals herein and may be used interchangeably. TFET devices, on the other hand, have asymmetric source and drain terminals. Those skilled in the art will appreciate that other transistors may be used, such as bipolar junction transistors (BJTs PNP/NPN), BiCMOS, CMOS, etc., without departing from the scope of the present disclosure.

FIG. 1 illustrates a high-level architecture 100 of a memory module having a means to maintain stable timing according to some embodiments of the present disclosure. Architecture 100 includes a host processor 101, a memory module 102, and a host-memory interface 103 (e.g., DDR, PCIe, etc. interfaces). In various embodiments, the memory module 102 includes a memory controller 104, the memory controller 104 having a clock stabilizer device 105; and N memory banks (memory bank)106_1-NWherein N is an integer greater than 1. The memory bank (memory bank) may be a volatile memory or a non-volatile memory. Examples of memory for memory banks include: spin transfer torque-magnetic random access memory (STT-MRAM), resistive RAM (ReRAM), NAND, Conductive Bridging RAM (CBRAM), or Phase Change Memory (PCM). In various embodiments, the memory module 102 includes or is coupled to another timing source 107. In this example, the additional timing source is a crystal oscillator 107. The crystal oscillator 107 may be packaged in the same package as the memory module or outside the package. The interface 103 provides data, clock (strobe) and control signals. When the clock from host processor 101 stops, clock stabilizer device 105 ensures that memory controller 104 continues to operate as intended without concerns about data integrity and security issues, including circuit instability, data loss, illegal register access, FIFO underflow, and firmware state corruption.

In some embodiments, before and after an unexpected clock stall from host processor 101, clock stabilizer device 105 uses a clock detector circuit, a clock smoothing circuit, and one or more PLLs to memory controller 104 and memory bank 106_1-NProviding a stable and continuous clock. Upon detection of a stopped host clock, the first PLL seamlessly switches from the on-board crystal oscillator 107 to the standby reference clock through the clock stabilizer device 105. The clock smoothing circuit of the clock stabilizer device 105 allows the first PLL to maintain a stable phase and frequency without causing larger disturbances or period shifts than the natural jitter of the locked PLL. In some embodiments, one or more optional downstream PLLs may drive additional clock domains within the memory module 102.

Fig. 2 illustrates a timing architecture 200 of the memory module 102 with means to maintain stable timing according to some embodiments of the present disclosure. In some embodiments, the clock stabilizer device 105 of the clocking architecture 200 includes a frequency divider 201, a multiplexer 202, a clock detector circuit 203, a clock smoothing circuit 204 (e.g., 204)_1-M) And one or more PLLs 205_1-M. The clock detector circuit 203 enables the memory controller 1 to be relocked without the need to relock it04, the PLL 205 is switched on-the-fly in real time while maintaining a stable and continuous output clock₁Reference clock (RefClk) input. After an unexpected clock stop event from host processor 101, clock stabilizer device 105 ensures that ongoing transactions to non-volatile memory 106 are completed at a predetermined time_1-NThus maintaining normal delays, preserving data integrity, and reducing the cost of the hold capacitor. Under normal operation of the computer system, the frequency divider 201 of the memory controller 104 divides the high speed host clock frequency of the host clock (e.g., in the range of 500MHz to 10 GHz) to frequency toward the first PLL [0]]205₁A lower speed reference clock or host clock (e.g., in the 10MHz to 200MHz range) is transmitted. The low-speed reference frequency matches (e.g., within 10% or within 0.1%) the frequency of the crystal clock of the on-module crystal oscillator 107 that is not used in normal operation. In various embodiments, the controller 104, whether a host crystal oscillator or an on-board crystal oscillator, is designed to support a worst-case frequency accuracy specification in PPM (parts per million).

Then, the first PLL [0]]205₁Generating a high speed output clock (PLL [0]]Clock), the high speed output clock drives the clock distribution network 206₁And/or a frequency divider 207 for one or more additional downstream PLLs 205₂Providing a low speed reference clock, the additional downstream PLL 205₂Driving additional clock distribution network and clock domains 206₂And forward. Clock domains (e.g., endpoint 208)_1-N) Using distribution network 206₁Output clock of₀. Herein, a clock domain refers to a logic or a group of logics operating on a particular clock. clock₀Is also used by the frequency divider 207 for the downstream PLL 205₂Another reference clock is generated. Then PLL [1]]205₂By a clock distribution network 206₂Receive to generate clock₁. The downstream PLL has an associated clock smoothing circuit to reduce any large phase noise in the downstream PLL. For example, the clock smoothing circuit 204₂And PLL [1]]205₂Work together. Then, clock₁By another clock domain (e.g.Endpoint 209_1-N) The preparation is used. The clock (e.g. clock)₁) Or another downstream clock may be stored by the memory array or bank 106_1-NThe preparation is used. Examples of endpoints include sampling circuits, encoders, decoders, error correction logic, and so forth. In some embodiments, the bit line for PLL [1] may be removed]And a preceding clock smoothing circuit 204₂。

After an unexpected clock stop, the clock detector circuit 203 provides a continuous and stable clock to the memory module 102. In some embodiments, the clock detector 203 quickly detects a stopped host clock and initiates the exchange of the low-speed, host-derived reference clock to the low-speed, on-module crystal oscillator 107 clock. In some embodiments, the clock detector circuit 203 detects a stopped host clock using digital circuitry. For example, clock detector circuit 203 uses a first PLL [0]]205₁Output of (PLL [0]]Clock) samples a divided-by-2 version of the high-speed host clock, with matched path delays centered on PLL [0]]The clock is relative to the rising edge of the divide-by-2 host clock. When the current sample matches the previous sample, the clock detector circuit 203 asserts a clock select signal (e.g., a stop clock) indicating that the host clock has stopped. Albeit the first PLL [0]]205₁May drift and eventually become unstable without reference, but the clock detection operation is completed within a few high speed host clock cycles, which ensures that the first PLL 0]205₁For a sufficiently short time (e.g., less than a low speed reference clock period) before a stopped host clock is detected.

Upon detection of a stopped host clock, the clock stabilizer device 105 instantaneously swaps to the on-module crystal oscillator 107 via the multiplexer 202 as the first PLL [0]]205₁To the new reference clock source. In this example, because the clock smoothing circuit 204 remains from the PLL [0] even under such sudden changes in the reference clock]205₁So there is no need to re-lock any PLL. The clock smoothing circuit 204 allows the first PLL [0]]205₁Slowly and gradually tracking new reference clock while maintaining stable output frequency well within timing tolerancePhase.

Using a clock smoothing circuit 204, PLL 205₁Maintaining a stable output clock frequency without relocking under sudden phase changes, such as may occur during a reference clock swap. The clock smoothing circuit 204, as it is slowly aligned with the new reference clock, ensures a first PLL 205₁The frequency and phase deviations on the output are minimal. Due to the low pass filter characteristic, the downstream PLL (e.g., 205)_2-M) Even smaller frequency and phase deviations are experienced. In this example, PLL [0]]205₁For downstream PLL [1: M]205_2-MProviding a reference clock, PLL [1: M ]]205_2-MThe various domains on the module are clocked. The output clocks of all PLLs maintain a consistent period both before and after clock stopping, which is well within timing tolerance, with negligible inter-period frequency and phase offsets such as would be seen with spread spectrum clocking or natural crystal oscillator drift.

For embodiments without clock smoothing, the low-pass filtering characteristics of the downstream PLL slightly degrade PLL [1]]The frequency deviation at the output of (e.g., to about 5%), while a smaller frequency deviation (e.g., less than 0.3%) is seen with clock smoothing. The common reference clock keeps the PLLs synchronized across all modules and since there is no host clock, synchronization with the host is no longer required. In some embodiments, clock doubling facilitates high speed output; even at sudden maximum input phase error (e.g., T of 0.5 x RefClk_Period) The clock smoothing circuit 204 still limits phase and/or frequency variations in the high-speed oscillator output to less than a fraction of a high-speed clock cycle.

FIG. 3 illustrates an apparatus 300 and associated timing diagram of a clock detector circuit according to some embodiments. The apparatus 300 includes flip-flops 301, 303, and 304, an inverter 302, and combinational logic 305 (e.g., exclusive NOR (exclusive NOR) gates) coupled together as shown. The divided-by-2 version of the high-speed host clock is sampled using the PLL [0] clock, with matched path delays centered on the rising edge of the PLL [0] clock relative to the divided-by-2 host clock (host clock div 2). When the current sample (sample N) from flip-flop 303 matches the previous sample (sample N-1) from flip-flop 304, combinational logic 305 asserts a clock signal (stop clock) indicating that the host clock has stopped. Depending on the clock speed, embodiments may use an additional sampling depth (e.g., four samples) to further improve robustness against jitter. In one example, two additional flip-flops (not shown) are used to generate samples N-2 and N-3, and then samples N-2 and N-3 are compared to samples N and N-1 before asserting the clock select signal indicates that the host clock has indeed stopped. Although the PLL [0] clock may drift and eventually become unstable without reference, the clock detection operation is completed within a few high speed host clock cycles, which is a short enough time (indeed less than the low speed reference clock cycle) to ensure that the PLL [0] clock remains stable until a stopped host clock is detected. Some embodiments may not only increase the sampling depth, but may also increase the width. For example, sample N and sample N-1 in fig. 3 are shifted versions of the host clock div 2, which is also a 1-bit counter. The counter width may be increased to N bits. Also, the numerical scheme may be implemented in any fashion such as gray code or binary counting.

Fig. 4 illustrates a Phase Locked Loop (PLL) coupled to a clock smoothing circuit to adjust the up pulse and the down pulse, according to some embodiments. The PLL 400 includes a phase detector 401 or Phase Frequency Detector (PFD), a charge pump 402, a filter 403, a Voltage Controlled Oscillator (VCO)404, a frequency divider 405, and a clock smoothing circuit 204. Other components of the PLL, such as the lock detector, are not shown in order not to obscure the embodiments.

Phase detector 401 receives a reference clock (RefClk) and a feedback clock (FbClk) and generates an Up (Up) signal and a down (Dn) signal. The up and down signals are pulses representing the relative phase difference between RefClk and FbClk. Without the clock smoothing circuit 204, the charge pump 402 receives the up and down pulses and sources or sinks current on node V1. The signal at V1 is then filtered by filter 403, such as a Low Pass Filter (LPF), to generate a filtered control voltage Vctl. Then, Vctl is used to control the oscillation frequency of VCO 404. The output of VCO404 is VcoClk. Divider 405 divides the frequency of VcoClk by a divide ratio to generate FbClk. During PLL lock, the up signal and the down signal provide evidence of dynamic phase error. The division ratio may be programmable or fixed. The division ratio may be an integer value or a fractional value. The dynamic phase error is the phase error between RefClk and FbClk before the PLL is declared locked. The PLL is declared locked when the phase difference between RefClk and FbClk is below a predetermined threshold.

Some embodiments of phase detector 401 use analog circuit technology, while other embodiments use digital circuitry. The phase detector 401 may be designed to be sensitive to phase only or to frequency and phase. When the phase detector is sensitive only to the phase of RefClk and FbClk, an output is produced that is proportional to the phase difference between the two signals. Phase detector 401 produces a constant voltage when the phase difference between RefClk and FbClk is stable. Phase detector 401 produces a varying voltage when there is a frequency difference between the two signals (RefClk and FbCLk). Example embodiments of phase detector 401 include a diode-based circular phase detector, an "exclusive-or" phase detector, a JK flip-flop based comparator, and a dual D-type phase detector. Typically, when a digital phase detector is to implement phase detector 401, the logic gates of the digital phase detector create short up pulses and down pulses. The static phase error is the difference in pulse width between the top pulse and the bottom pulse, which is caused by the mismatch of the leakage current and the charge pump current.

When the PLL is in the normal operating mode, the PFD outputs a pulse whose duration is proportional to the phase error between the input RefClk of the PLL and the FBClk. These pulses enable the charge pump to source or sink an amount of charge proportional to the sign and magnitude of the phase error. Charge is pumped onto a capacitor (Cp) and filtered to provide a control voltage for the VCO404, which VCO404 accelerates or slows its output frequency in response to changes in the control voltage (Vctl). Eventually, the PLL reaches a stable "locked" state with nearly constant Vctl and minimal phase error. The divide-by-N divider 405 allows the PLL to output a frequency that is N times greater than the Refclk frequency.

Sudden changes in the source of RefClk may introduce large phase errors at the input of PFD 401. It can be seen that the amount of charge sourced from or sunk into the control VCO404 by the capacitor Cp is a function of the phase error. The amount of charge per unit time sampled on the capacitor is a function of the capacitor size (Cp) and the charge change or current per unit time (Ip ═ dQ/dT). For the moment, it is considered to limit this charge variation to less than what can be in the RefClk period (T)_Period) Internal sources or absorption maxima. Since the voltage of Vctl varies proportionally to the current, this currently limits the maximum variation of Vctl toThis implies that the gain of the PFD 401 and the charge pump system 402 may be saturated to stop the VCO404 from abruptly changing phase and/or frequency due to an abruptly large phase error. In various embodiments, the clock smoothing circuit 204 intercepts the PFD outputs (up and dn) and limits the pulse length to t0<(1％*T_Period). Thus, the modified upper and lower pulses (Up 'and Dn') are provided to the charge pump 402 to limit the amount of charge absorbed or sourced to node V1. Limiting the pulse width to t0 produces a similar ratio of variation (e.g., about 1%) in the output phase and frequency of the high-speed oscillator clock. It should be noted that t0 may be a value other than 1%, depending on system design considerations. Using the clock smoothing circuit 204, the PLL can maintain a stable output clock frequency without relocking under sudden phase changes greater than t0, such as may occur during a reference clock swap. The clock smoothing circuit, as it is slowly aligned with the new reference clock, ensures that the frequency and phase deviations on the first PLL output are minimal.

Although the PLL 400 is illustrated as an analog PLL, any type of PLL may be used to generate the clock. For example, a mixed signal PLL, an all-digital PLL, or the like may be used with the clock smoothing circuit 204. In some embodiments, the PFD 401 may be replaced with a time-to-digital converter (TDC). In one such embodiment, a digital clock smoothing circuit monitors the digital stream output of the TDC and digitally processes it to smooth sudden large changes in phase. Here, the output may be maintained in a digital format or converted to an analog output. In some embodiments, filter 403 may be replaced with an all-digital filter using well-known digital filter implementations, such as Finite Impulse Response (FIR) or Infinite Impulse Response (IIR). In one such embodiment, the digital filter receives a digital input from a clock smoothing circuit or from an analog-to-digital converter. In some embodiments, VCO404 may be replaced with a digitally controlled oscillator or DCO. In one such embodiment, the DCO receives a digital input from a digital filter or converts an analog input to a digital representation via an analog-to-digital converter.

Fig. 5 illustrates an apparatus 500 and associated timing diagram for clock smoothing according to some embodiments. Apparatus 500 includes delay line 501, inverter 502, and gate 503, delay line 504, inverter 505, and gate 506 coupled together as shown. Upon an unexpected clock stall, assertion of the "stalled clock" signal (or clock select signal) initiates PLL [0]]The exchange of the input reference clock from the low speed host clock to the low speed crystal oscillator clock. It should be noted that because the ultimate source of the host clock is also a crystal oscillator, the frequencies of the two low speed clocks are matched within a few Parts Per Million (PPM). However, there may be an arbitrary phase relationship between the two low speed clocks, so PLL [0]]The reference clock edge may suddenly have a large phase error with respect to the feedback clock. This phase error (also denoted as the up/down signal from the PFD 401 or the digital stream output from the TDC) may be a significant fraction of the reference clock period after the multiplexer 202 performs the clock swap, which in turn may result in PLL [0]]205₁Significantly slowed down or sped up without the clock smoothing circuit 204. However, the clock smoothing circuit 204 intercepts the raw PFD outputs (Up and Dn) and sends them through programmable inverting delay lines (501 and 504) which are anded with the raw PFD outputs (Up and Dn) (through 503 and 506). This logic limits PLL [0]]The experienced phase error (represented as the Up '/Dn' signal) and maintains a stable and continuous output clock for the clock distribution network.

In one example, a 1% limit for 100MHz Refclk, t0In the case of system N-32, a 5ns sudden input phase error results in 3.125ps (═ 0.01T) on the high speed 3200Mhz output clock_Period/N) maximum deviation. This is similar to the natural jitter of PLL noise inherent sources (e.g., thermal noise, power supply noise, and feed-through noise). In this context, a more precise definition of maintaining a "continuous and stable" clock under unexpected clock stops is also provided: this means that the output clock smoothing circuit limits the phase or frequency offset of the high speed clock to be lower in magnitude than those inherent noise from the normal operation of the locked PLL.

Fig. 6 illustrates a graph 600 showing clock exchange performance of a PLL and a clock smoothing circuit according to some embodiments. Graph 600 shows PLL [0]601 and PLL [1]601 output clocks; the additional PLL has similar performance. In graph 600, both PLL [0] and PLL [1] start and lock first; the unexpected clock then stops occurring near the 3.4 mus mark, as shown by the windowed portion of the waveform. The circuit simulation includes feed-through noise, which results in a natural frequency shift in the locked PLL [1] of about 20MHz (or less than 1%). After the unexpected clock stops and switches to the new reference clock, the clock smoothing circuit limits the additional noise introduced into the output clock of PLL [0] to less than 1MHz and limits the additional noise introduced into the output clock of PLL [1] to less than 20 MHz. Due to all inherent noise sources in normal lock operation, the frequency offset in the circuit simulation is much less than the expected total noise on the output of the PLL.

Although the embodiments are described with reference to an oscillator that provides a low speed clock to the multiplexer 202, the reverse process may also occur. For example, at power up of a memory module, where oscillator 107 may be the only clock available, and switches to the host clock when the host clock is stable. In some embodiments, the switching may also occur without a clock detection circuit, and the switching of the clock input may instead occur based on an explicit external control signal.

Fig. 7 illustrates a smart device or computer system or SoC (system on a chip) having an apparatus to maintain stable timing according to some embodiments of the present disclosure. It should be noted that those elements of fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not so limited.

In some embodiments, device 2400 represents a suitable computing device, such as a computing tablet, mobile or smart phone, laptop, desktop, internet of things (IOT) device, server, wearable device, set-top box, wireless enabled e-reader, or the like. It should be understood that certain components are shown generically and that not all components of such a device are shown in device 2400.

In an example, device 2400 includes a SoC (system on a chip) 2401. Example boundaries of SOC 2401 are illustrated using dashed lines in fig. 7, with some example components illustrated as being included within SOC 2401 — however, SOC 2401 may include any suitable components of device 2400.

In some embodiments, device 2400 includes a processor 2404. Processor 2404 may include one or more physical devices such as microprocessors, application processors, microcontrollers, programmable logic devices, processing cores, or other processing means. The processing operations performed by processor 2404 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to a human user or to I/O (input/output) of I/O devices of other devices, operations related to power management, operations related to connecting the computing device 2400 to another device, and so forth. The processing operations may also include operations related to audio I/O or display I/O.

In some embodiments, processor 2404 includes multiple processing cores (also referred to as cores) 2408a, 2408b, 2408 c. Although only three cores 2408a, 2408b, 2408c are illustrated in fig. 7, processor 2404 may include any other suitable number of processing cores, e.g., tens or even hundreds of processing cores. The processing cores 2408a, 2408b, 2408c may be implemented on a single Integrated Circuit (IC) chip. Further, a chip may include one or more shared and/or private caches, buses or interconnects, graphics and/or memory controllers, or other components.

In some embodiments, processor 2404 includes cache 2406. In an example, portions of the cache 2406 may be dedicated to respective cores 2408 (e.g., a first portion of the cache 2406 is dedicated to the core 2408a, a second portion of the cache 2406 is dedicated to the core 2408b, etc.). In an example, one or more portions of the cache 2406 may be shared between two or more cores 2408. The cache 2406 may be divided into different levels, such as a level 1 (L1) cache, a level 2 (L2) cache, a level 3 (L3) cache, and so on.

In some embodiments, processing core 2404 may include a fetch unit to fetch instructions (including instructions with conditional branches) executed by core 2404. The instructions may be fetched from any storage device, such as the memory 2403. Processor core 2404 may also include a decode unit to decode the fetched instructions. For example, the decode unit may decode the fetched instruction into a plurality of micro-operations. Processor core 2404 may include a scheduling unit to perform various operations associated with storing decoded instructions. For example, the dispatch unit may hold data from the decode unit until the instruction is ready for dispatch, e.g., until all original values of the decoded instruction become available. In one embodiment, the scheduling unit may schedule and/or issue (or dispatch) decoded instructions to the execution units for execution.

After an instruction is decoded (e.g., by a decode unit) and dispatched (e.g., by a dispatch unit), the execution unit may execute the dispatched instruction. In embodiments, the execution unit may include more than one execution unit (e.g., imaging computation unit, graphics computation unit, general purpose computation unit, etc.). The execution units may also perform various arithmetic operations such as addition, subtraction, multiplication, and/or division, and may include one or more Arithmetic Logic Units (ALUs). In an embodiment, a coprocessor (not shown) may perform various arithmetic operations in conjunction with an execution unit.

Furthermore, the execution units may execute instructions out-of-order. Thus, in one embodiment, processor core 2404 may be an out-of-order processor core. Processor core 2404 may also include a retirement unit (retirement unit). The retirement unit may retire executed instructions after the instructions are committed. In embodiments, executed instruction retirement may result from the state of the processor being committed by the instruction execution, the physical registers being used by the instruction being deallocated, and so forth. Processor core 2404 may also include a bus unit to enable communication between components of processor core 2404 and other components via one or more buses. The processor core 2404 may also include one or more registers to store data accessed by various components of the core 2404 (e.g., values associated with assigned application priorities and/or subsystem states (modes)).

In some embodiments, the device 2400 includes a connectivity circuit 2431. For example, circuitry 2431 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and/or software components (e.g., drivers, protocol stacks, etc.) to, for example, enable device 2400 to communicate with external devices. Device 2400 can be separate from external devices such as other computing devices, wireless access points, or base stations.

In an example, the connectivity circuitry 2431 may include a variety of different types of connectivity. Generally, the connectivity circuitry 2431 may include cellular connectivity circuitry, wireless connectivity circuitry, and so forth. The cellular connectivity circuitry of connectivity circuitry 2431 generally refers to cellular network connectivity provided by a wireless operator, such as via GSM (global system for mobile communications) or variants or derivatives, CDMA (code division multiple access) or variants or derivatives, TDM (time division multiplexing) or variants or derivatives, third generation partnership project (3GPP) Universal Mobile Telecommunications System (UMTS) system capable or variants or derivatives, 3GPP Long Term Evolution (LTE) system or variants or derivatives, 3GPP LTE-advanced (LTE-a) system or variants or derivatives, fifth generation (5G) wireless system or variants or derivatives, 5G mobile network system or variants or derivatives, 5G New Radio (NR) system or variants or derivatives, or other cellular service standards. The wireless connectivity circuitry (or wireless interface) of the connectivity circuitry 2431 refers to non-cellular wireless connectivity and may include a personal area network (e.g., bluetooth, near field, etc.), a local area network (e.g., Wi-Fi), and/or a wide area network (e.g., WiMax), and/or other wireless communications. In an example, the connectivity circuitry 2431 may include a network interface, such as a wired or wireless interface, for example, such that system embodiments may be incorporated into a wireless device, such as a cell phone or personal digital assistant.

In some embodiments, device 2400 includes a control center 2432 that represents hardware devices and/or software components related to interaction with one or more I/O devices. For example, the processor 2404 may communicate with one or more of a display 2422, one or more peripheral devices 2424, a storage device 2428, one or more other external devices 2429, and the like, via the control center 2432. The control center 2432 may be a chipset, a platform control center (PCH), or the like.

For example, control center 2432 illustrates one or more connection points for additional devices connected to device 2400, e.g., through which a user can interact with the system. For example, devices that can be attached to device 2400 (e.g., device 2429) include a microphone device, a speaker or stereo system, an audio device, a video system or other display device, a keyboard or keypad device, or other I/O devices for particular applications such as card readers or other devices.

As described above, the control center 2432 can interact with audio devices, the display 2422, and the like. For example, input or commands can be provided to one or more applications or functions of device 2400 through input from a microphone or other audio device. In addition, audio output may be provided instead of or in addition to display output. In another example, if the display 2422 comprises a touchscreen, the display 2422 also acts as an input device that may be at least partially managed by the control center 2432. Additional buttons or switches may also be present on the computing device 2400 to provide I/O functionality managed by the control center 2432. In one embodiment, the control center 2432 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware devices that may be included in the device 2400. The input may be part of direct user interaction, and environmental input may also be provided to the system to affect its operation (e.g., filter noise, adjust display for brightness detection, apply flash or other features for the camera).

In some embodiments, the control center 2432 may be coupled to the various devices using any suitable communication protocol, for example, PCIe (peripheral component interconnect express), USB (universal serial bus), Thunderbolt (Thunderbolt), High Definition Multimedia Interface (HDMI), Firewire (Firewire), and the like.

In some embodiments, display 2422 represents hardware (e.g., a display device) and software (e.g., a driver) components that provide a visual and/or tactile display for a user to interact with device 2400. The display 2422 may include a display interface, a display screen, and/or hardware devices for providing a display to a user. In some embodiments, the display 2422 comprises a touchscreen (or touchpad) device that provides output and input to a user. In an example, the display 2422 can communicate directly with the processor 2404. The display 2422 can be one or more internal display devices as within a mobile electronic device or laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, display 2422 may be a Head Mounted Display (HMD), such as a stereoscopic display device for Virtual Reality (VR) applications or Augmented Reality (AR) applications.

In some embodiments and although not illustrated in the figures, device 2400 can include, in addition to (or in place of) processor 2404, a Graphics Processing Unit (GPU) that includes one or more graphics processing cores that can control one or more aspects of the display content on display 2422.

The control center 2422 (or platform controller center) may include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections, for example, with peripheral devices 2424.

It is to be appreciated that device 2400 can be a peripheral device to other computing devices or have a peripheral device connected thereto. For purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on the device 2400, the device 2400 can have a "docking" connector for connecting to other computing devices. Additionally, a docking connector may allow device 2400 to connect to certain peripheral devices that allow computing device 2400 to control content output (e.g., to an audiovisual system or other system).

In addition to proprietary docking connectors or other proprietary connection hardware, the device 2400 may also be peripherally connected via a conventional connector or a standard-based connector. Common types may include Universal Serial Bus (USB) connectors, which may include any of a number of different hardware interfaces, displayports including MiniDisplayPort (MDP), high-definition multimedia interface (HDMI), firewire, or other types.

In some embodiments, the connectivity circuitry 2431 may be coupled to the control center 2432 in addition to or in place of being directly coupled to the processor 2404, for example. In some embodiments, for example, the display 2422 can be coupled to the control center 2432 in addition to or instead of being directly coupled to the processor 2404.

In some embodiments, device 2400 includes memory 2430 coupled to processor 2404 via memory interface 2434. Memory 2430 includes memory devices for storing information in device 2400.

In some embodiments, memory 2430 includes means for maintaining stable timing as described with reference to various embodiments. The memory may include non-volatile (state does not change if power to the storage device is interrupted) and/or volatile (state is indeterminate if power to the storage device is interrupted) memory devices. The memory device 2430 can be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance for use as a processing memory. In one embodiment, memory 2430 is operable as system memory for device 2400 to store data and instructions for use when one or more processors 2404 execute an application or process. Memory 2430 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of device 2400. In some embodiments, storage 2428 may include the apparatus.

Elements of the various embodiments and examples are also provided as a machine-readable medium (e.g., memory 2430) for storing computer-executable instructions (e.g., instructions for implementing any other processes discussed herein). The machine-readable medium (e.g., memory 2430) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, DVDs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, Phase Change Memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

In some embodiments, device 2400 includes a temperature measurement circuit 2440, e.g., for measuring the temperature of various components of device 2400. In an example, the temperature measurement circuit 2440 can be embedded in, coupled to, or attached to various components whose temperature is to be measured or monitored. For example, the temperature measurement circuit 2440 may measure the temperature of (or internal to) one or more of the cores 2408a, 2408b, 2408c, the voltage regulator 2414, the memory 2430, the motherboard of the SOC 2401, and/or any suitable components of the device 2400.

In some embodiments, device 2400 includes a power measurement circuit 2442, e.g., for measuring power consumed by one or more components of device 2400. In an example, the power measurement circuit 2442 can measure voltage and/or current in addition to, or instead of, measuring power. In an example, the power measurement circuit 2442 may be embedded in, coupled to, or attached to various components of the power, voltage, and/or current consumption to be measured or monitored. For example, the power measurement circuit 2442 can measure power, current, and/or voltage provided by one or more voltage regulators 2414, power provided to the SOC 2401, power provided to the device 2400, power consumed by the processor 2404 (or any other component) of the device 2400, and so forth.

In some embodiments, device 2400 includes one or more voltage regulator circuits, commonly referred to as Voltage Regulators (VRs) 2414. VR 2414 generates signals at appropriate voltage levels that may be provided to operate any appropriate components of device 2400. For example only, VR 2414 is illustrated as providing a signal to processor 2404 of device 2400. In some embodiments, VR 2414 receives one or more Voltage Identification (VID) signals and generates a voltage signal at an appropriate level based on the VID signals. Different types of VRs may be utilized for VR 2414. For example, VR 2414 may include a "buck" VR, a "boost" VR, a combination of buck and boost VRs, a Low Dropout (LDO) regulator, a switching DC-DC regulator, and so forth. Step-down VR is typically used in power transmission applications where the input voltage needs to be converted to an output voltage at a ratio of less than 1. In some embodiments, each processor core has its own VR controlled by PCU 2410a/b and/or PMIC 2412. In some embodiments, each core has a distributed LDO network to provide efficient control of power management. The LDO may be digital, analog, or a combination of digital or analog LDOs.

In some embodiments, device 2400 includes one or more clock generator circuits, commonly referred to as clock generators 2416. The clock generator 2416 generates a clock signal at an appropriate frequency level, which may be provided to any appropriate components of the operating device 2400. For example only, clock generator 2416 is illustrated as providing a clock signal to processor 2404 of device 2400. In some embodiments, clock generator 2416 receives one or more Frequency Identification (FID) signals and generates a clock signal at an appropriate frequency based on the FID signals.

In some embodiments, device 2400 includes a battery 2418 that provides power to various components of device 2400. For example only, a battery 2418 is shown as providing power to the processor 2404. Although not shown in the figures, device 2400 can include a charging circuit that recharges the battery, for example, based on an alternating current power source received from an Alternating Current (AC) adapter.

In some embodiments, device 2400 includes a Power Control Unit (PCU)2410 (also referred to as a Power Management Unit (PMU), power controller, etc.). In an example, some portions of PCU 2410 may be implemented by one or more processing cores 2408, and these portions of PCU 2410 are symbolically illustrated using dashed boxes and labeled PCU 2410 a. In an example, some other portions of PCU 2410 may be implemented external to processing core 2408, and these portions of PCU 2410 are symbolically illustrated using dashed boxes and labeled PCU 2410 b. PUC 2140 may implement various power management operations for device 2400. PCU 2410 may include hardware interfaces, hardware circuits, connectors, registers, and the like, as well as software components (e.g., drivers, protocol stacks) to implement various power management operations for device 2400.

In some embodiments, device 2400 includes a Power Management Integrated Circuit (PMIC)2412, e.g., to implement various power management operations for device 2400. In some embodiments, PMIC 2412 is a reconfigurable power management ic (rpmic) and/or IMVP: (rpvp)Moving voltage positioning). In an example, the PMIC is located within an IC chip separate from the processor 2404. The PMIC may implement various power management operations for device 2400. PMIC 2412 may include hardware interfaces, hardware circuits, connectors, registers, etc., and software components (e.g., drivers, protocol stacks) to implement various power management operations for device 2400.

In an example, the device 2400 includes one or both of the PCU 2410 or the PMIC 2412. In an example, either PCU 2410 or PMIC 2412 may not be present in device 2400, and therefore these components are illustrated using dashed lines.

Various power management operations of device 2400 may be performed by PCU 2410, PMIC 2412, or a combination of PCU 2410 and PMIC 2412. For example, PCU 2410 and/or PMIC 2412 may select power states (e.g., P-states) for various components of device 2400. For example, PCU 2410 and/or PMIC 2412 may select power states (e.g., according to ACPI (advanced configuration and power interface) specifications) for various components of device 2400. For example only, PCU 2410 and/or PMIC 2412 may transition various components of device 2400 to a sleep state, an active state, an appropriate C state (e.g., a C0 state according to the ACPI standard or another appropriate C state). In an example, the PCU 2410 and/or PMIC 2412 may control the voltage output by the VR 2414 and/or the frequency of the clock signal output by the clock generator, e.g., by outputting a VID signal and/or a FID signal, respectively. In an example, the PUC 2410 and/or PMIC 2412 may control battery power usage, charging of the battery 2418, and features related to power saving operation.

The clock generator 2416 may include a Phase Locked Loop (PLL), a Frequency Locked Loop (FLL), or any suitable clock source. In some embodiments, each core of processor 2404 has its own clock source. As such, each core may operate at a frequency that is independent of the operating frequencies of the other cores. In some embodiments, the PCU 2410 and/or the PMIC 2412 perform adaptive or dynamic frequency scaling or adjustment. For example, if a core is not operating below its maximum power consumption threshold or limit, the clock frequency of the processor core may be increased. In some embodiments, the PCU 2410 and/or PMIC 2412 determines operating conditions for each core of the processor and opportunistically adjusts the frequency and/or supply voltage of a core without losing lock of the core's clock source (e.g., the core's PLL) when the PCU 2410 and/or PMIC 2412 determines that the core is operating below a target performance level. For example, if a core draws less current from a power rail than the total current allocated to the core or processor 2404, the PCU 2410 and/or PMIC 2412 may temporarily increase the power draw of the core or processor 2404 (e.g., by increasing the clock frequency and/or power supply voltage level) so that the core or processor 2404 may operate at a higher performance level. As such, the voltage and/or frequency may be temporarily increased for the processor 2404 without violating product reliability.

In an example, PCU 2410 and/or PMIC 2412 may perform power management operations, for example, based at least in part on measurements received from power measurement circuit 2442, temperature measurement circuit 2440, a charge level of battery 2418, and/or any other suitable information that may be used for power management. To this end, the PMIC 2412 is communicatively coupled to one or more sensors to sense/detect various values/changes in one or more factors that have an impact on the power/thermal behavior of the system/platform. Examples of one or more factors include current, voltage drop, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, and the like. One or more of these sensors may be provided in physical proximity (and/or in thermal contact/coupling) with one or more components or logic/IP blocks of the computing system. Additionally, in at least one embodiment, the sensor(s) may be directly coupled to PCU 2410 and/or OMIC 2412 to allow PCU 2410 and/or PMIC 2412 to manage processor core energy based at least in part on values detected by the sensor(s).

An example software stack of device 2400 is also illustrated (although not all elements of the software stack are illustrated). By way of example only, the processor 2404 may execute an application 2450, an operating system 2452, one or more Power Management (PM) specific applications (e.g., commonly referred to as PM application 2458), and the like. The PM application 2458 may also be executed by the PCU 2410 and/or the PMIC 2412. The OS 2452 can also include one or more PM applications 2456a, 2456b, 2456 c. The OS 2452 can also include various drivers 2454a, 2454b, 2454c, etc., some of which can be dedicated for power management purposes. In some embodiments, device 2400 may also include a basic input/output system (BIOS) 2420. The BIOS 2420 can communicate with the OS 2452 (e.g., via one or more drivers 2454), with the processor 2404, and so forth.

For example, one or more of PM applications 2458, 2456, drivers 2454, BIOS 2420, etc. can be used to perform power management specific tasks, e.g., to control the voltage and/or frequency of various components of device 2400, to control the awake state, sleep state, and/or any other suitable power state of various components of device 2400, to control battery power usage, charging of battery 2418, features related to power saving operation, etc.

Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may", "might", "could", or "could", be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a or an" element, that does not mean there is only one of the element. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment wherever particular features, structures, functions, or characteristics associated with the first and second embodiments are not mutually exclusive.

While the present disclosure has been described in conjunction with specific embodiments, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the present disclosure are intended to embrace all such alternatives, modifications and variances that fall within the broad scope of the appended claims.

In addition, well known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Furthermore, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements is highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

The following examples are provided to illustrate various embodiments. These examples may be referenced to each other in any suitable manner.

Example 1: an apparatus, comprising: a first circuit for selecting one of a first clock or a second clock; a Phase Locked Loop (PLL) to receive an output of the first circuit as a reference clock of the PLL; and a second circuit coupled to the PLL, wherein the second circuit is to detect whether the first clock is present and provide a select signal to the first circuit to: selecting the first clock as an output of the first circuit in the presence of the first clock; and selecting the second clock as the output of the first circuit in the absence of the first clock.

Example 2: the apparatus of example 1, comprising a third circuit to adjust an up pulse and a down pulse from a phase detector of the PLL when the first circuit selects the second clock.

Example 3: the apparatus of example 1, comprising a fourth circuit to divide a third clock to generate the first clock.

Example 4: the apparatus of example 3, wherein the third clock is generated by a host processor.

Example 5: the apparatus of example 1, wherein the second clock is generated by a crystal oscillator, wherein a frequency of the first clock is substantially the same as a frequency of the second clock.

Example 6: the apparatus of example 1, wherein the first circuit comprises a multiplexer.

Example 7: the apparatus of example 1, wherein the second circuit comprises: a first flip-flop having a clock input receiving the first clock and an output coupled to the input via an inverter; a second flip-flop having a clock input receiving an output of the PLL, an input coupled to an output of the first flip-flop, and an output; a third flip-flop having a clock input receiving an output of the PLL, an input coupled to an output of the second flip-flop, and an output; and combinational logic to receive an output of the second flip-flop and an output of the third flip-flop, wherein an output of the combinational logic provides the select signal.

Example 8: the apparatus of example 2, wherein the third circuit comprises: a first programmable delay line for receiving the top pulse; a first inverter coupled to an output of the first programmable delay line; a first combinational logic to receive the top pulse and an output of the first inverter, wherein an output of the first combinational logic provides an adjusted top pulse; a second programmable delay line for receiving the lower pulse; a second inverter coupled to an output of the first programmable delay line; and second combinatorial logic to receive the lower pulse and an output of the second inverter, wherein an output of the second combinatorial logic provides an adjusted lower pulse.

Example 9: the apparatus of example 1, comprising a clock distribution network coupled to an output of the PLL.

Example 10: the apparatus of example 9, wherein the reference clock is a first reference clock, wherein the PLL is a first PLL, wherein the apparatus comprises: a frequency divider for dividing the output of the first PLL and generating a second reference clock; and a second PLL for receiving the second reference clock.

Example 11: the apparatus of example 10, wherein the clock distribution network is a first clock distribution network, wherein the apparatus includes a second clock distribution network coupled to an output of the second PLL, and wherein an output of the second clock distribution network is received by a memory.

Example 12: the apparatus of example 10, wherein the first PLL and the second PLL are one of analog PLLs or digital PLLs.

Example 13: an apparatus, comprising: a Phase Locked Loop (PLL) to receive a reference clock and generate an output clock, the output clock being used directly or indirectly to write data to a memory; and circuitry for detecting a valid first clock and causing the multiplexer to provide a second clock as the reference clock when the first clock is invalid.

Example 14: the apparatus of example 13, wherein the circuit is a first circuit, and wherein the apparatus comprises a second circuit to adjust a top pulse and a bottom pulse from the PLL when the multiplexer provides the second clock as the reference clock.

Example 15: the apparatus of example 14, comprising a third circuit to divide the first clock to generate a third clock, wherein the third clock and the second clock are input to the multiplexer.

Example 16: the apparatus of example 13, wherein the first clock is generated by a host processor.

Example 17: the apparatus of example 15, wherein the second clock is generated by a crystal oscillator, and wherein a frequency of the third clock is substantially the same as a frequency of the second clock.

Example 18: a system, comprising: a processor; a memory module coupled to the processor, wherein the processor sends a first clock to the memory module, wherein the processor module comprises: a first circuit for selecting one of a first clock or a second clock; a Phase Locked Loop (PLL) to receive an output of the first circuit as a reference clock of the PLL; and a second circuit coupled to the PLL, wherein the second circuit is to detect whether the first clock is present and provide a select signal to the first circuit to: selecting the first clock as an output of the first circuit in the presence of the first clock; and in the absence of the first clock, selecting the second clock as the output of the first circuit; and a wireless interface for allowing the processor to communicate with another device.

Example 19: the system of example 18, wherein the memory module comprises: a third circuit for adjusting an upper pulse and a lower pulse from a phase detector of the PLL when the first circuit selects the second clock; and a fourth circuit to divide the third clock to generate the first clock.

Example 20: the system of example 18, wherein the second clock is generated by a crystal oscillator, wherein a frequency of the first clock is substantially the same as a frequency of the second clock.

The abstract is provided to allow the reader to ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.