阅读说明：本技术 延迟不敏感异步电路单元、M×N-Join及其工作方法 (Delay insensitive asynchronous circuit unit, MXN-Join and working method thereof ) 是由 李佳 崔梓林 何春来 许文丽 宋伟 古平 于 2021-09-26 设计创作，主要内容包括：本发明公开了一种延迟不敏感异步电路单元、M×N-Join及其工作方法。所述异步电路单元,包括一个2×2-jion基础元件和一个Splitter组合元件；Splitter组合元件包括一个merge基础元件以及两个fork基础元件；第一fork基础元件的第一输出端与2×2-jion基础元件的第三输入端连接；第二fork基础元件的第一输出端与2×2-jion基础元件的第四输入端连接；2×2-jion基础元件的第三输入端与2×2-jion基础元件的第四输入端同轴向；第一fork基础元件的第二输出端与第二fork基础元件的第二输出端分别与merge基础元件的两个输入端连接。本申请提出了一个结构简单的延迟不敏感异步电路单元,由其扩展的M×N-jion设计,具有较好的扩展性和平面性。(The invention discloses a delay insensitive asynchronous circuit unit, an MXN-Join and a working method thereof. The asynchronous circuit unit comprises a 2 x 2-jon base element and a Splitter combination element; the Splitter combination unit comprises a merge base unit and two fork base units; the first output terminal of the first fork basis element is connected to the third input terminal of the 2 x 2-j ion basis element; the first output terminal of the second fork base element is connected to the fourth input terminal of the 2 x 2-j ion base element; the third input terminal of the 2 x 2-ion base unit is coaxial with the fourth input terminal of the 2 x 2-ion base unit; the second output terminal of the first fork basic element and the second output terminal of the second fork basic element are respectively connected to the two input terminals of the merge basic element. The application provides a delay insensitive asynchronous circuit unit with a simple structure, and the expanded MXN-jon design has better expansibility and planarity.)

1. A delay insensitive asynchronous circuit unit comprising a 2 x 2-jon base unit and a Splitter combination unit; the Splitter combination unit comprises a merge base unit and two fork base units; the first output terminal of the first fork basis element is connected to the third input terminal of the 2 x 2-j ion basis element; the first output terminal of the second fork base element is connected to the fourth input terminal of the 2 x 2-j ion base element; the third input terminal of the 2 x 2-ion base unit is coaxial with the fourth input terminal of the 2 x 2-ion base unit; the second output terminal of the first fork basic element and the second output terminal of the second fork basic element are respectively connected to the two input terminals of the merge basic element.

2. An mxn-Join comprising a plurality of delay insensitive asynchronous circuit cells as claimed in claim 1.

3. The mxn-Join of claim 2, wherein the delay-insensitive asynchronous circuit cells are spread in rows or columns by two or three connecting lines.

4. The mxn-Join according to claim 3, wherein the delay-insensitive asynchronous circuit cell comprises two output terminal groups and two input terminal groups; the first input end and the second input end of the 2 x 2-jion basic element are a first input end group; the input end of the first fork basic element and the input end of the second fork basic element are a second input end group; the output end of the 2 x 2-jion basic element is a first output end group; the output end of the merge basic element is a second output end group; the delay insensitive asynchronous circuit unit is divided into a head unit and a non-head unit, and the head unit is a delay insensitive asynchronous circuit unit of which the second input end group is provided with an input end connected with the outside.

5. The MXN-Join according to claim 4, wherein the head unit is expanded as follows:

one port of the second output end group of the head unit is connected with one port of the first input end group of the expansion unit; one port of the first input end group of the head unit is connected with one port of the first output end group of the expansion unit;

or, one port of the second output terminal group of the head unit is connected with one port of the second input terminal group of the extension unit; one port of the first input end group of the head unit is connected with one port of the first output end group of the expansion unit;

or, two ports of the first output end group of the head unit are respectively connected with two ports of the second input end group of the extension unit; one port of the second input terminal group of the head unit is connected to one port of the second output terminal group of the extension unit.

6. The MXN-Join as claimed in claim 4, wherein the non-header unit is extended as follows:

two ports of a first output end group of the non-head unit are respectively connected with two ports of a second input end group of the expansion unit;

or, two ports of the first output terminal group of the non-head unit are respectively connected with two ports of the first input terminal group of the extension unit; one port of the second input terminal group of the non-head unit is connected with one port of the second output terminal group of the extension unit.

7. The MXN-Join as claimed in claim 5 or 6 wherein after the unit is expanded, the resulting MXN-Join is further expanded as an expanded element.

8. The MXN-Join according to claim 4, wherein the MXN-Join is connected as follows:

between the head units, one port of the second output terminal group of one head unit is connected with one port of the second input terminal group of another head unit; one port of the first input end group of one head unit is connected with one port of the first output end group of the other head unit;

two ports of a first output end group of the head unit are connected with two ports of a first input end group of the non-head unit; one port of the first input terminal group of the head unit is connected with one port of the second output terminal group of the non-head unit;

among the non-head units, when the direction consistent with the extension direction of the head unit is extended, one port of the second input end group of one non-head unit is connected with one port of the first output end group of the other non-head unit; when the head unit expands in a direction different from the expansion direction of the head unit, two ports of the first output terminal group of one head unit are connected to two ports of the first input terminal group of another head unit, and one port of the second input terminal group of one head unit is connected to one port of the second output terminal group of another head unit.

9. An operation method of M x N-Join, comprising the steps of:

s1: selecting a unit input signal in each row and column, and recording the unit input signal as a row input signal and a column input signal; the row input signals conduct the row input ends of the column part of the units according to the operation mode of the units; the column input signals conduct the column input ends of the row part units according to the operation mode of the units;

s2: when the row and column input terminals of a cell are turned on in step S1, the cell outputs a signal to turn on the cell of the row having the column turn-on signal or the cell of the column having the row turn-on signal;

s3: after the signal transmission in step S2 is completed, one of the cells of the input row input signal or the input column input signal in step S1 is turned on, and a signal is output to a cell of the next row or the next column;

s4: repeating the steps S1-S3, a part of the M × N-Join cells will be turned on.

Technical Field

The invention relates to the field of asynchronous circuits, in particular to a delay insensitive asynchronous circuit unit, an MXN-Join and a working method thereof.

Background

With the continuous expansion of circuit scale, the conventional circuit using clock as the main synchronization mode encounters a series of problems, such as clock skew, low modularization degree, etc. The asynchronous circuit is designed without central clock signal coordination, information interaction among modules can be completed in a handshaking mode and the like, and meanwhile, rich coding schemes such as common double-track coding and the like are supported; the asynchronous circuit has the advantages of low power consumption, high running speed, good electromagnetic compatibility, strong reliability, capability of avoiding clock skew and the like.

Delay insensitive circuits (DI circuits) are asynchronous circuits in which any delay may occur in the interconnect lines and blocks without the delay affecting the accuracy of the circuit output. The DI circuit is event-driven, i.e., the circuit is triggered to operate once it receives a complete set of input signals. A circuit is delay insensitive if its external input and output behavior remains unchanged regardless of any (but finite) delay of any internal blocks or interconnect lines. Such circuits are robust, but few because of the many constraints. Among several kinds of theoretical models of asynchronous circuits, a delay insensitive circuit model is the one with the best theoretical prospect and the largest potential, but is also the one which is difficult to realize.

Keller has discussed in the language of the general Speed-Independent Modules that we can build arbitrary asynchronous circuits by combining a set of basic asynchronous components. According to the concept of keller, Priyadarsan Patra proposes the implementation of a series of asynchronous circuit elements in Building-blocks for Designing DI Circuits, and an mxn-jion circuit is one of them. The MXN-jon can be used as a core component of the DI circuit to form a model of the DI circuit as shown in FIG. 1, and the MXN-jon plays an important role in the circuit as a Mealy automaton. However, the circuit designed by Patra has some disadvantages, such as complex structure and poor realizability. As shown in FIG. 2, M N-j in the circuit proposed by patra can be understood as an indexing process of a quadtree. The basic idea of quadtree indexing can be summarized as dividing the spatial recursion into tree knots with different hierarchical depths, and then searching according to a certain method. It equally divides the space of the known range into four equal subspaces, and recurses in this way until the tree hierarchy reaches a certain depth or meets a certain requirement, and then stops the division. The MxN-Join circuit proposed by Patra can be constructed in a recursive manner, and through a continuous recursive process, we can finally obtain a basic joion realized by basic elements such as 2 x 2-Join, 2 x 1-Join and merge proposed by keller. In the M.times.N-Join proposed by Patra, the signal (R) is input_i,C_j) According to the value ranges of i and j, the signals finally enter the joons positioned at the four corners of the circuit, and the structures of the joons and the MXN-Join have no difference except that the values of M and N are different; the signal is then repeated until it can eventually be processed and output by the underlying 2 x 2-Join calculation. The M × N-jion search method proposed by patra is complex; and the design based on recursion makes expansion have more problems, for example, when M and N are odd or even, the self structure of the circuit can be changed greatly, and the circuit design can be affected badly; in addition, the circuit has poor planarity, and when the circuit with poor planarity is applied to the microelectronic field such as chip wiring, additional design work is required to prevent signal interference, which makes the application complicated.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provide a delay insensitive asynchronous circuit unit, an MXN-Join and a working method thereof.

In order to achieve the above purpose, the invention provides the following technical scheme:

a delay insensitive asynchronous circuit unit comprising a 2 x 2-jon base unit and a Splitter combination unit; the Splitter combination unit comprises a merge base unit and two fork base units; the first output terminal of the first fork basis element is connected to the third input terminal of the 2 x 2-j ion basis element; the first output terminal of the second fork base element is connected to the fourth input terminal of the 2 x 2-j ion base element; the third input terminal of the 2 x 2-ion base unit is coaxial with the fourth input terminal of the 2 x 2-ion base unit; the second output terminal of the first fork basic element and the second output terminal of the second fork basic element are respectively connected to the two input terminals of the merge basic element.

An mxn-Join comprising the delay insensitive asynchronous circuit cell described above.

Preferably, the extension of the row or column is implemented between the delay insensitive asynchronous circuit cells by two or three connection lines.

Preferably, the delay insensitive asynchronous circuit unit comprises two output terminal groups and two input terminal groups; the first input end and the second input end of the 2 x 2-jion basic element are a first input end group; the input end of the first fork basic element and the input end of the second fork basic element are a second input end group; the output end of the 2 x 2-jion basic element is a first output end group; the output end of the merge basic element is a second output end group; the unit is divided into a head unit and a non-head unit, and the head unit is a unit of which the second input end group is provided with an input end connected with the outside.

Preferably, the head unit is expanded as follows:

one port of the second output end group of the head unit is connected with one port of the first input end group of the expansion unit; one port of the first input end group of the head unit is connected with one port of the first output end group of the expansion unit;

or, one port of the second output terminal group of the head unit is connected with one port of the second input terminal group of the extension unit; one port of the first input end group of the head unit is connected with one port of the first output end group of the expansion unit;

or, two ports of the first output end group of the head unit are respectively connected with two ports of the second input end group of the extension unit; one port of the second input terminal group of the head unit is connected to one port of the second output terminal group of the extension unit.

Preferably, the non-head unit is expanded as follows:

two ports of a first output end group of the non-head unit are respectively connected with two ports of a second input end group of the expansion unit;

or, two ports of the first output terminal group of the non-head unit are respectively connected with two ports of the first input terminal group of the extension unit; one port of the second input terminal group of the non-head unit is connected with one port of the second output terminal group of the extension unit.

Preferably, after the unit is expanded, the resulting M × N-Join is further expanded as an expanded element.

Preferably, the M × N-Join connection mode is as follows:

between the head units, one port of the second output terminal group of one head unit is connected with one port of the second input terminal group of another head unit; one port of the first input end group of one head unit is connected with one port of the first output end group of the other head unit;

two ports of a first output end group of the head unit are connected with two ports of a first input end group of the non-head unit; one port of the first input terminal group of the head unit is connected with one port of the second output terminal group of the non-head unit;

among the non-head units, when the direction consistent with the extension direction of the head unit is extended, one port of the second input end group of one non-head unit is connected with one port of the first output end group of the other non-head unit; when the head unit expands in a direction different from the expansion direction of the head unit, two ports of the first output terminal group of one head unit are connected to two ports of the first input terminal group of another head unit, and one port of the second input terminal group of one head unit is connected to one port of the second output terminal group of another head unit.

An operation method of M x N-Join includes the following steps:

s1: selecting a unit input signal in each row and column, and recording the unit input signal as a row input signal and a column input signal; the row input signals conduct the row input ends of the column part of the units according to the operation mode of the units; the column input signals conduct the column input ends of the row part units according to the operation mode of the units;

s2: when the row and column input terminals of a cell are turned on in step S1, the cell outputs a signal to turn on the cell of the row having the column turn-on signal or the cell of the column having the row turn-on signal;

s3: after the signal transmission in step S2 is completed, one of the cells of the input row input signal or the input column input signal in step S1 is turned on, and a signal is output to a cell of the next row or the next column;

s4: repeating the steps S1-S3, a part of the M × N-Join cells will be turned on.

Compared with the prior art, the invention has the beneficial effects that: the application provides a brand-new MxN-jion design, accords with the limitation of Keller to basic elements, and has the advantages of better expansibility, planarity and the like compared with a circuit designed by patra.

Description of the drawings:

FIG. 1 is a schematic diagram of a DI circuit of the background of the invention;

FIG. 2 is a diagram of the indexing process of M × N-j proposed by patra in the background of the present invention;

FIG. 3 is a schematic diagram of a delay insensitive asynchronous circuit cell of an exemplary embodiment 1 of the present invention;

FIG. 4 is a schematic view of a 2X 2-Jion base unit according to exemplary embodiment 1 of the present invention;

FIG. 5 is a schematic diagram of a fork base element of exemplary embodiment 1 of the present invention;

FIG. 6 is a schematic view of a merge base unit according to exemplary embodiment 1 of the present invention;

FIG. 7 is a schematic diagram of a Splitter combination unit according to exemplary embodiment 1 of the present invention;

FIG. 8 is a functional diagram of M.times.N-Join according to exemplary embodiment 2 of the present invention;

FIG. 9 is a schematic diagram of cell classification in exemplary embodiment 2 of the present invention;

fig. 10 is a schematic diagram showing an expansion of the head unit according to exemplary embodiment 2 of the present invention;

fig. 11 is a schematic diagram showing an expansion of a non-header unit according to exemplary embodiment 1 of the present invention;

fig. 12 is a schematic diagram showing an expansion manner of an expansion circuit of exemplary embodiment 2 of the present invention;

fig. 13 is a schematic diagram of the signal transmission process of step S1 in exemplary embodiment 3 of the present invention;

fig. 14 is a schematic diagram of the signal transmission process of step S2 in exemplary embodiment 3 of the present invention;

fig. 15 is a schematic diagram of the signal transmission process of step S3 in exemplary embodiment 3 of the present invention;

fig. 16 is a first schematic diagram illustrating the signal transmission process of step S4 according to exemplary embodiment 3 of the present invention;

fig. 17 is a second schematic diagram of the signal transmission process of step S4 in exemplary embodiment 3 of the present invention;

fig. 18 is a third schematic diagram of the signal transmission process in step S4 in exemplary embodiment 3 of the present invention.

Detailed Description

The present invention will be described in further detail with reference to test examples and specific embodiments. It should be understood that the scope of the above-described subject matter is not limited to the following examples, and any techniques implemented based on the disclosure of the present invention are within the scope of the present invention.

Example 1

As shown in fig. 1, the present embodiment provides a delay insensitive asynchronous circuit unit, which includes a 2 x 2-jon base unit and a Splitter combination unit; the Splitter combination unit comprises a merge base unit and two fork base units; a first output of the first fork base element is connected to a first input of the 2 x 2-j ion base element; the first output terminal of the second fork base element is connected to the second input terminal of the 2 x 2-j ion base element; the first input terminal of the 2 x 2-jon base element is coaxial with the second input terminal of the 2 x 2-jon base element; the second output terminal of the first fork basic element and the second output terminal of the second fork basic element are respectively connected to the two input terminals of the merge basic element.

Briefly describe a 2 x 2-jion base element, a merge base element, and a fork base element.

As shown in FIG. 4, 2X 2-Jion is one of the basic elements, which has four input lines and four output lines, and generates output signals on the corresponding output lines by combining signals on different input lines; wherein the four input lines are respectively I₁、I₂、I₃And I₄，I₁And I₂Is a coaxial input line, I₃And I₄Is a coaxial input line; the four output lines are respectively O₁、O₂、O₃And O₄(ii) a The mathematical expression is as follows:

I_i，I_j；λ→{O_k}；λ

as shown in FIG. 5, fork is one of the base elements, arriving at input line A_fIs assimilated and copied into two signals, each at an output line B_fAnd C_fAnd carrying out transmission. The mathematical expression is as follows:

{A_f}；λ→{B_f，C_f}；λ

as shown in FIG. 6, merge is one of the base elements, arriving at input line A_MOr B_MIs transferred to the output line C_MMeanwhile, Merge is not a synchronous element in an asynchronous circuit, so that the 'waiting' of signals is not generated. The mathematical expression is as follows:

{A_M}；λ→{C_M}；λ

{B_M}；λ→{C_M}；λ

wherein, a merge base unit and two fork base units are combined to obtain the Splitter combination unit. Splitter, the signal arriving from a will be copied by fork into two branches, one output from c and the other through merge and output from port c ", as shown in FIG. 7; the same applies to the signal arriving from a ', one arriving at merge and the other arriving at port c'.

The delay insensitive asynchronous circuit unit described in this embodiment includes four input ports and five output ports; the four input ports are respectively a first input end of the 2 x 2-jon basic element, a second input end of the 2 x 2-jon basic element, an input end of the first fork basic element and an input end of the second fork basic element; the five output ports are four outputs of the 2 x 2-jion basis element and one output of the merge basis element. The function of the delay insensitive asynchronous circuit cell can be described as: from C₁Or C₂The signal transmitted through the fork base element will generate two signals, one of which will pass through D after merge₁Out of the element, the other via B₁Or B₂Enters 2 x 2-jon and waits when the external receives the generated input signal A₁Or A₂After reaching 2X 2-jon, the product is calculated, synthesized and output with A₁、A₂、B₁And B₂The four input lines input signals and output signals corresponding to the signals.

The delay insensitive asynchronous circuit unit described in this embodiment performs connection expansion to obtain an mxn-Join circuit.

Example 2

Keller sets forth a series of conditions to describe the class of DI circuits under which any circuit can be implemented by a fixed set of base elements. One of the circuits is { Merge, Fork, 2 × 2-Join, sequence }, and this embodiment adopts a new delay insensitive asynchronous circuit unit, and proposes a new M × N-Join circuit.

As shown in FIG. 8, the function of the MXN-Join is assimilation, i.e., two signals, one from input line A_i(1 ≦ i ≦ m), and the other from input line B_j(1. ltoreq. j. ltoreq.n) is assimilated inOutput line C_ijTo generate a signal. While a join is a synchronous element, when a signal arrives on one input line, but no signal arrives on the other input line, the signal will be retained until a signal arrives on the other line, producing a result. The mathematical formula can be expressed as:

A_i，B_j；λ→{C_ij}；λ

in an asynchronous circuit, mxn-Join needs to fulfill some functions as follows: (1) certainty (certainty), each set of inputs corresponding to a unique determinable output; (2) computability (computability), which is an automaton with computability; (3) the versatility (versatility) allows all logic and circuit bool type operations to be performed.

The mxn-Join described in this embodiment provides a new design of mxn-Join according to the construction of the delay insensitive asynchronous circuit unit described in embodiment 1, and while satisfying the above requirements, the mxn-Join also has: (1) extensibility (extensibility), a unitized extension to two dimensions; (2) planarity (Flatness): there is no crossover between the connecting lines.

In this embodiment, the delay insensitive asynchronous circuit unit can be extended in rows or columns by adding two or three connection lines.

As shown in fig. 3, the delay insensitive asynchronous circuit cell includes two output terminal groups and two input terminal groups; the first input end and the second input end of the 2 x 2-jion basic element are a first input end group; the input end of the first fork basic element and the input end of the second fork basic element are a second input end group; the output end of the 2 x 2-jion basic element is a first output end group; the output end of the merge basic element is a second output end group.

The first input and the second input of the 2 x 2-jon base element are the same axial inputs of the 2 x 2-jon base element to which the Splitter combination element is not connected.

As shown in fig. 9, the unit is divided into a head unit and a non-head unit, and the head unit is a unit in which the second input terminal group is left with an input terminal connected to the outside.

The head unit is expanded as follows:

the first method is as follows:

as shown in fig. 10(a), one port of the second output terminal group of the head unit is connected to one port of the first input terminal group of the extension unit; one port of the first input terminal group of the head unit is connected to one port of the first output terminal group of the extension unit.

The second method comprises the following steps:

as shown in fig. 10(b), one port of the second output terminal group of the head unit is connected to one port of the second input terminal group of the extension unit; one port of the first input terminal group of the head unit is connected to one port of the first output terminal group of the extension unit.

The third method comprises the following steps:

as shown in fig. 10(c), two ports of the first output terminal group of the head unit are connected to two ports of the second input terminal group of the extension unit, respectively; one port of the second input terminal group of the head unit is connected to one port of the second output terminal group of the extension unit.

The non-head unit is extended as follows:

the first method is as follows:

as shown in fig. 11(a), two ports of the first output terminal group of the non-head unit are connected to two ports of the second input terminal group of the extension unit, respectively.

The second method comprises the following steps:

as shown in fig. 11(b), two ports of the first output terminal group of the non-head unit are connected to two ports of the first input terminal group of the extension unit, respectively; one port of the second input terminal group of the non-head unit is connected with one port of the second output terminal group of the extension unit.

As shown in fig. 12, after the cell is expanded in the above-described manner, an expansion circuit is obtained, which can be further expanded as an expanded element.

Between the head units, one port of the second output terminal group of the upper head unit is connected with one port of the second input terminal group of the lower head unit; one port of the first input terminal group of the upper head unit is connected with one port of the first output terminal group of the lower head unit;

two ports of a first output end group of the head unit are connected with two ports of a first input end group of the non-head unit; one port of the first input terminal group of the head unit is connected with one port of the second output terminal group of the non-head unit;

among the non-head units, if the head unit expands in the column direction, one port of the second input end group of the previous non-head unit is connected with one port of the first output end group of the next non-head unit in the column direction; in the lateral direction, two ports of the first output terminal group of the upper head unit are connected to two ports of the first input terminal group of the lower head unit, and one port of the second input terminal group of the upper head unit is connected to one port of the second output terminal group of the lower head unit.

The expansion mode of the embodiment is various and convenient, and the expansion in any direction in a two-dimensional space can be realized.

Example 3

As shown in fig. 13, this embodiment illustrates the working method of M × N-Join by taking an extension method as an example, including the following steps:

s1, selecting a unit input signal in each row and column, and recording the unit input signal as a row input signal and a column input signal; the row input signals conduct the row input ends of the column part of the units according to the operation mode of the units; the column input signals conduct the column input ends of the row part units according to the operation mode of the units;

s2, when the row and column input terminals of a cell are turned on in step S1, the cell outputs a signal to turn on the cell of the row having the column turn-on signal or the cell of the column having the row turn-on signal;

s3, after the signal transmission in step S2 is completed, one of the cells of the input row signal or the input column signal in step S1 is turned on, and a signal is output to a cell of the next row or the next column;

s4, repeating the steps S1-S3, the partial unit of M × N-Join will be turned on.

Example 4

This embodiment will take an example of an mxn-Join to illustrate how a signal operates in a circuit. First, specific symbols and terms in which the present embodiment will appear are defined.

(1) Definition of terms

Line: a plurality of units are combined together horizontally, and the transmission of signals in one row can only be carried out in the horizontal direction;

the method comprises the following steps: a plurality of units are vertically combined together, and signal transmission among one column can be only carried out in the vertical direction;

ascending: the signals are transmitted to the upper part in the diagram in the circuit diagram, and are irrelevant to the actual signal transmission;

and (3) right row: the signals are transmitted to the right in the diagram in the circuit diagram, independently of the actual signal transmission.

(2) Definition of special symbols

H: a signal representing that the element is in a wait state.

The description of the transmission process will refer to the component ports, which are shown in fig. 4 for the sake of uniform naming.

The transmission process of the signal in the circuit comprises the following steps:

s1, Signal (A)_i，B_j) Inputting;

as shown in fig. 13, the input signal B of the upper row_jThrough unit J_mjBifurcating a fork basis element, duplicating and generating two signals, one of which is transmitted to J_mjOf 2X 2-Jion base element₃Port, while another signal passes through merge basic element to cell J in the same row_m(j+1)J in line m by the action of splitter combination elements_m(j+1)，J_m(j+2)，···，J_m(n-1)，J_mnI of each unit₄The ports all have input signal waiting;

input signal A of the right row_iThrough unit J_jnA fork element of (2) generating two signals, one of which is transmitted to J_jnOf 2X 2-Jion base element₂The other signal is input into the unit J in the same column through the Merge element_(i+1)nJ of column n by the action of splitter combination elements_(i+1)n，J_(i+2)n，···，J_(m-1)n，J_mnI of each unit₁The ports also have input signal latency.

S2, signal row transmission;

as shown in FIG. 14, when the whole circuit is observed, only the unit J can be found_mnThe 2 x 2-Jion basic element has effective input signals at the ports of two axial input lines and can be calculated and synthesized, so that the O of the basic element is₄The port outputs the newly synthesized right row signal into the row. Unit J_m(n-1)I of (A)₁The port receives the signal from the "left side" and performs new calculations and synthesis on the current cell, continuing to transmit the newly generated signal to the right. This process is repeated all the time.

S3, signal uplink transmission;

as shown in fig. 15, a signal up to the continuously updated is transmitted to the unit J of the m-th layer_mjI of (A)₁Port, Unit J_mjWill be I already in step S1₃The port receiving and waiting signal and the transmitted I₁Combining signals which are received by the port and are subjected to multiple calculation updates together to perform new calculation updates; and will be in cell J_mjO of (A) to (B)₁The port outputs a new signal, and the signal transmits the signal to the unit J of the (m-1) th layer_(m-1)jOf 2X 2-Jion base element₃A port;

s4, outputting a signal;

as shown in fig. 16 to 18, the input signal a in step S1 is repeated_iSimilar procedure, i.e. passing the combined signal through the split structure, so thatJ of (m-1) th layer_(m-1)(j+1)，J_(m-1)(j+2)，···，J_(m-1)(n-1)，J_(m-1)nI of each unit₄All have input signal waiting, and J_(m-1)jI of (A)₃The port of (2) will also receive the new combined signal;

repeating the steps S2 and S3 so that the combined signal of the (m-1) th layer can propagate upward; until the signal is transmitted to the i-th layer, and the composition information distribution of step S1 is completed, so that J_i(j+1)，J_i(j+2)，···，J_i(n-1)，J_inI of (A)₄Port and J_ijI of the component₃The ports have signals waiting; now only element J_inThere are two input signals, calculated at port O₃Generating an output signal;

the signal is transmitted right to element J_ijI of (A)₂Port of, current J_ijThe component has another composite signal I₃The port waits, thus passing the current J_ijFinal computational synthesis of elements, newly generated computation signal S_ijWill be from J_ijO of the element₂And (6) outputting the port.

Through the steps, the signal output of the unit of the partial area in the mxn-jion circuit is realized.

The m × n-j ion circuit described in this embodiment is compared with the patra circuit mentioned in the background art in terms of search principle, scalability, one-sidedness, and the like:

the search principle is as follows: the circuit idea of patra is close to quadtree search, while the jion principle proposed herein is a plane search;

and (3) expandability: the unit designed in the text can realize expansion in any direction in a two-dimensional space, and even M multiplied by N-Join itself can be used as a basic unit to realize expansion; the jion circuit proposed by patra is based on a recursive design, and has more problems in expansion, for example, when M and N are odd or even, the structure of the circuit can be greatly changed, and the circuit design can be adversely affected;

planarity: there are no crossovers between the connecting lines of the circuit design proposed herein, while there are comparable crossovers in the circuit design proposed by patra.

Therefore, the mxn-Join circuit composed of delay insensitive asynchronous circuit units described in this embodiment conforms to the limitations of Keller on the basic elements, the search method is simple, and the circuit has advantages of better expansibility, planarity and the like than the circuit designed by patra.

The foregoing is merely a detailed description of specific embodiments of the invention and is not intended to limit the invention. Various alterations, modifications and improvements will occur to those skilled in the art without departing from the spirit and scope of the invention.