阅读说明：本技术 基于数字逻辑硬件电路的主泵转速信号处理方法及系统 (Main pump rotating speed signal processing method and system based on digital logic hardware circuit ) 是由 朱加良 秦越 何正熙 杨洪润 青先国 何鹏 吴茜 徐涛 朱毖微 徐思捷 李小芬 于 2021-10-13 设计创作，主要内容包括：本发明公开了一种基于数字逻辑硬件电路的主泵转速信号处理方法及系统,其中,方法包括以下步骤：实时对传感器产生的类正弦脉冲信号进行预处理,得到标准的方波信号；获取所述方波信号的周期,并根据所述周期获取预先存储的转速信号数据；其中,所述对照表为各个所述周期与各个所述转速信号数据的对应关系；根据所述转速信号数据获取模拟量信号和开关量信号。本发明的目的在于提供一种基于数字逻辑硬件电路的主泵转速信号处理方法及系统,具有可靠性高、低功耗、高精度及无需开发软件程序等特点,可以很好的解决上述问题。(The invention discloses a method and a system for processing a main pump rotating speed signal based on a digital logic hardware circuit, wherein the method comprises the following steps: preprocessing a quasi-sinusoidal pulse signal generated by a sensor in real time to obtain a standard square wave signal; acquiring the period of the square wave signal, and acquiring prestored rotating speed signal data according to the period; wherein, the comparison table is the corresponding relation between each period and each rotating speed signal data; and acquiring an analog quantity signal and a switching value signal according to the rotating speed signal data. The invention aims to provide a method and a system for processing a main pump rotating speed signal based on a digital logic hardware circuit, which have the characteristics of high reliability, low power consumption, high precision, no need of developing a software program and the like and can well solve the problems.)

1. The method for processing the main pump rotating speed signal based on the digital logic hardware circuit is characterized by comprising the following steps of:

s1: preprocessing a quasi-sinusoidal pulse signal generated by a sensor in real time to obtain a standard square wave signal;

s2: acquiring the period of the square wave signal, and acquiring prestored rotating speed signal data according to the period and a comparison table; wherein, the comparison table is the corresponding relation between each period and each rotating speed signal data;

s3: and acquiring an analog quantity signal and a switching value signal according to the rotating speed signal data.

2. The digital logic hardware circuit-based main pump rotating speed signal processing method as claimed in claim 1, wherein the rotating speed signal data is binary data with 15 bits, and the 1 st bit to 11 th bit of the binary data represent rotating speed signals of a main pump, and the 12 th bit to 15 th bit of the binary data represent the switching value signals.

3. The digital logic hardware circuit-based main pump rotational speed signal processing method as claimed in claim 2, wherein said S3 comprises the sub-steps of:

s31: performing DA conversion on the 1 st bit to the 11 th bit of the binary data to obtain the analog quantity signal; comparing the period of the square wave signal at the current moment with the period of the square wave signal at the previous moment;

s32: when the period of the square wave signal at the current moment is smaller than that of the square wave signal at the previous moment, outputting numerical values corresponding to 13 th bit and 15 th bit of the binary data; otherwise, outputting the corresponding numerical values of the 12 th bit and the 14 th bit.

4. The digital logic hardware circuit-based main pump rotating speed signal processing method as claimed in claim 1, wherein the rotating speed signal data is binary data with 16 bits, and the 1 st bit to 11 th bit of the binary data represent rotating speed signals of a main pump, the 12 th bit represents a parity check signal, and the 13 th bit to 16 th bit represents a switching value signal.

5. The digital logic hardware circuit-based main pump rotational speed signal processing method according to claim 4, wherein the step S3 comprises the sub-steps of:

s31: judging whether the rotation speed signal data is valid or not by adopting a parity check method;

s32: when the rotating speed signal data is valid, DA conversion is carried out on the 1 st bit to the 11 th bit of the binary data to obtain the analog quantity signal; judging the size of the period of the square wave signal at the current moment and the size of the period of the square wave signal at the previous moment;

s33: when the period of the square wave signal at the current moment is smaller than that of the square wave signal at the previous moment, outputting numerical values corresponding to 13 th bit and 15 th bit of the binary data; otherwise, outputting the corresponding numerical values of the 12 th bit and the 14 th bit.

6. Main pump rotational speed signal processing system based on digital logic hardware circuit, its characterized in that includes:

the processing module is used for preprocessing the quasi-sinusoidal pulse signals generated by the sensor in real time to obtain standard square wave signals;

the searching module is used for acquiring the period of the square wave signal and acquiring prestored rotating speed signal data according to the period and a comparison table; wherein, the comparison table is the corresponding relation between each period and each rotating speed signal data;

and the processing module is used for acquiring an analog quantity signal and a switching value signal according to the rotating speed signal data.

7. The digital logic hardware circuit-based main pump rotating speed signal processing system as claimed in claim 6, wherein the rotating speed signal data is binary data with 15 bits, and the 1 st bit to 11 th bit of the binary data represent rotating speed signals of a main pump, and the 12 th bit to 15 th bit of the binary data represent the switching value signals.

8. The digital logic hardware circuit-based main pump rotational speed signal processing system of claim 7, wherein the processing module comprises:

the conversion unit is used for performing DA conversion on the 1 st bit to the 11 th bit of the binary data to obtain the analog quantity signal;

the comparison unit is used for comparing the period of the square wave signal at the current moment with the period of the square wave signal at the previous moment;

the output unit is used for outputting numerical values corresponding to 13 th bit and 15 th bit of the binary data when the period of the square wave signal at the current moment is smaller than the period of the square wave signal at the previous moment; otherwise, outputting the corresponding numerical values of the 12 th bit and the 14 th bit.

9. The digital logic hardware circuit-based main pump rotating speed signal processing system as claimed in claim 6, wherein the rotating speed signal data is binary data of 16 bits, and the 1 st bit to 11 th bit of the binary data represent rotating speed signals of the main pump, the 12 th bit represents parity check signals, and the 13 th bit to 16 th bit represents switching value signals.

10. The digital logic hardware circuit-based main pump rotational speed signal processing system of claim 9, wherein said processing module comprises:

the judging unit is used for judging whether the rotating speed signal data is valid by adopting a parity check method;

the conversion unit is used for performing DA conversion on the 1 st bit to the 11 th bit of the binary data to obtain the analog quantity signal when the rotating speed signal data is effective;

the comparison unit is used for comparing the period of the square wave signal at the current moment with the period of the square wave signal at the previous moment;

the output unit is used for outputting numerical values corresponding to 13 th bit and 15 th bit of the binary data when the period of the square wave signal at the current moment is smaller than the period of the square wave signal at the previous moment; otherwise, outputting the corresponding numerical values of the 12 th bit and the 14 th bit.

Technical Field

The invention relates to the technical field of nuclear power plant process measurement, in particular to a method and a system for processing a main pump rotating speed signal based on a digital logic hardware circuit.

Background

In a nuclear power device, a main pump rotating speed signal belongs to a safety level parameter and is an important signal for triggering a shutdown protection function, and measurement equipment is required to be safety level equipment and meet the requirements of high reliability and accurate and timely signal processing.

At present, a nuclear power device generally adopts a magnetic resistance type measuring principle to measure a main pump rotating speed signal, and measuring equipment comprises a sensor and a downstream signal processing circuit, wherein the sensor is arranged on a pump shaft. The sensor outputs a quasi-sinusoidal pulse signal with the same rotating frequency as the main pump, the signal processing circuit can obtain a rotating speed value by calculating the interval of the pulse signal, and outputs a 4 mA-20 mA analog quantity signal, a rotating speed low signal and a rotating speed low switching value signal according to the requirement.

The traditional signal processing method adopts a pulse signal processing method based on a CPU, the method has the problems of more internal components, higher power consumption and poor reliability caused by easy failure, and the phenomena of discontinuous output, large indication deviation, peak fluctuation, sudden indication drop to 0 and the like appear in a plurality of nuclear power plants at present, so that the safe and stable operation of a nuclear power device is seriously influenced. In addition, the processing software in the CPU needs to perform V & V, and the development difficulty is high.

Disclosure of Invention

The invention aims to provide a method and a system for processing a main pump rotating speed signal based on a digital logic hardware circuit, which have the characteristics of high reliability, low power consumption, high precision, no need of developing a software program and the like and can well solve the problems.

The invention is realized by the following technical scheme:

in one aspect of the present application, the present application provides a method for processing a main pump rotational speed signal based on a digital logic hardware circuit, comprising the following steps:

s1: preprocessing a quasi-sinusoidal pulse signal generated by a sensor in real time to obtain a standard square wave signal;

s2: acquiring the period of the square wave signal, and acquiring prestored rotating speed signal data according to the period and a comparison table; wherein, the comparison table is the corresponding relation between each period and each rotating speed signal data;

s3: and acquiring an analog quantity signal and a switching value signal according to the rotating speed signal data.

In the scheme, the quasi-sinusoidal pulse signals collected by the sensor for monitoring the rotating speed are converted into square wave signals, so that the signals have strong anti-interference capability in the transmission process; meanwhile, under the condition of achieving the function of monitoring the rotating speed of the main pump, the device also has the characteristic of low power consumption because a data processing mode of carrying out complex calculation through a single chip microcomputer is not needed; in addition, the condition that adopts pure hardware circuit satisfies the needs of main pump rotational speed monitoring in this application, so this device still has response time fast, measurement accuracy is high, the advantage of strong reliability.

Preferably, the rotating speed signal data is binary data with 15 bits, and the 1 st bit to the 11 th bit of the binary data represent the rotating speed signal of the main pump, and the 12 th bit to the 15 th bit of the binary data represent the switching value signal.

Preferably, the S3 includes the following substeps:

s31: performing DA conversion on the 1 st bit to the 11 th bit of the binary data to obtain the analog quantity signal; comparing the period of the square wave signal at the current moment with the period of the square wave signal at the previous moment;

s32: when the period of the square wave signal at the current moment is smaller than that of the square wave signal at the previous moment, outputting numerical values corresponding to 13 th bit and 15 th bit of the binary data; otherwise, outputting the corresponding numerical values of the 12 th bit and the 14 th bit.

Preferably, the rotation speed signal data is binary data of 16 bits, and the 1 st bit to the 11 th bit of the binary data represent the rotation speed signal of the main pump, the 12 th bit represents the parity check signal, and the 13 th bit to the 16 th bit represents the switching value signal.

Preferably, the S3 includes the following substeps:

s31: judging whether the rotation speed signal data is valid or not by adopting a parity check method;

s32: when the rotating speed signal data is valid, DA conversion is carried out on the 1 st bit to the 11 th bit of the binary data to obtain the analog quantity signal; judging the size of the period of the square wave signal at the current moment and the size of the period of the square wave signal at the previous moment;

s33: when the period of the square wave signal at the current moment is smaller than that of the square wave signal at the previous moment, outputting numerical values corresponding to 13 th bit and 15 th bit of the binary data; otherwise, outputting the corresponding numerical values of the 12 th bit and the 14 th bit.

In another aspect of the present application, the present application further provides a system for processing a main pump rotational speed signal based on a digital logic hardware circuit, comprising:

the processing module is used for preprocessing the quasi-sinusoidal pulse signals generated by the sensor in real time to obtain standard square wave signals;

the searching module is used for acquiring the period of the square wave signal and acquiring prestored rotating speed signal data according to the period and a comparison table; wherein, the comparison table is the corresponding relation between each period and each rotating speed signal data;

and the processing module is used for acquiring an analog quantity signal and a switching value signal according to the rotating speed signal data.

In the scheme, the quasi-sinusoidal pulse signals collected by the sensor for monitoring the rotating speed are converted into square wave signals, so that the signals have strong anti-interference capability in the transmission process; meanwhile, under the condition of achieving the function of monitoring the rotating speed of the main pump, the device also has the characteristic of low power consumption because a data processing mode of carrying out complex calculation through a single chip microcomputer is not needed; in addition, the condition that adopts pure hardware circuit satisfies the needs of main pump rotational speed monitoring in this application, so this device still has response time fast, measurement accuracy is high, the advantage of strong reliability.

Preferably, the rotating speed signal data is binary data with 15 bits, and the 1 st bit to the 11 th bit of the binary data represent the rotating speed signal of the main pump, and the 12 th bit to the 15 th bit of the binary data represent the switching value signal.

Preferably, the processing module comprises:

the conversion unit is used for performing DA conversion on the 1 st bit to the 11 th bit of the binary data to obtain the analog quantity signal;

the comparison unit is used for comparing the period of the square wave signal at the current moment with the period of the square wave signal at the previous moment;

the output unit is used for outputting numerical values corresponding to 13 th bit and 15 th bit of the binary data when the period of the square wave signal at the current moment is smaller than the period of the square wave signal at the previous moment; otherwise, outputting the corresponding numerical values of the 12 th bit and the 14 th bit.

Preferably, the rotation speed signal data is binary data of 16 bits, and the 1 st bit to the 11 th bit of the binary data represent the rotation speed signal of the main pump, the 12 th bit represents the parity check signal, and the 13 th bit to the 16 th bit represents the switching value signal.

Preferably, the processing module comprises:

the judging unit is used for judging whether the rotating speed signal data is valid by adopting a parity check method;

the conversion unit is used for performing DA conversion on the 1 st bit to the 11 th bit of the binary data to obtain the analog quantity signal when the rotating speed signal data is effective;

the comparison unit is used for comparing the period of the square wave signal at the current moment with the period of the square wave signal at the previous moment;

the output unit is used for outputting numerical values corresponding to 13 th bit and 15 th bit of the binary data when the period of the square wave signal at the current moment is smaller than the period of the square wave signal at the previous moment; otherwise, outputting the corresponding numerical values of the 12 th bit and the 14 th bit.

Compared with the prior art, the invention has the following advantages and beneficial effects:

1. the method is realized based on a hardware circuit, can quickly and accurately output rotating speed analog quantity and switching value signals according to the rotating state of the main pump through FLASH table lookup and a logic loop control technology, is simple and reliable in circuit, does not need software V & V, and is low in equipment power consumption;

2. and meanwhile, an odd check (or even check) design is carried out, and the circuit has self-checking capability on the basis of circuit simplification.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 is a schematic diagram of a sensor collecting a quasi-sinusoidal pulse signal;

FIG. 2 is a schematic diagram of a digital logic circuit configuration according to the present invention;

FIG. 3 is a diagram illustrating a Flash lookup table according to the present invention;

FIG. 4 is a schematic diagram of the logic loop control of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.

Example 1

The embodiment provides a method for processing a main pump rotating speed signal based on a digital logic hardware circuit, wherein the digital logic hardware circuit in the embodiment is shown in fig. 2 and comprises a processor, a counter, Flash, a digital-to-analog converter and an address change circuit, wherein the Flash stores a comparison table and a plurality of rotating speed signal data in advance. The scheme of the present application is explained based on the above-mentioned digital logic hardware circuit as follows:

s1: preprocessing a quasi-sinusoidal pulse signal generated by a sensor in real time to obtain a standard square wave signal;

the quasi-sinusoidal pulse signal is shown in fig. 1, and the processor filters and shapes the quasi-sinusoidal pulse main pump rotating speed signal collected by the sensor into a square wave signal of 10 ms. It should be noted that, during the conversion process, the rising edge of the square wave signal is selected at a suitable time point according to the characteristics of the main pump rotation speed signal, so that the frequency of the square wave signal is the same as that of the main pump rotation speed signal.

S2: acquiring the period of the square wave signal, and acquiring prestored rotating speed signal data according to the period and a comparison table; wherein, the comparison table is the corresponding relation between each period and each rotating speed signal data;

specifically, a clock of an addition counter is used for calculating a time interval between rising edges of square wave signals (namely a period of the square wave signals), the time interval is used as an address signal to be sent to Flash, a plurality of rotating speed signal data are stored in the Flash in advance, the 1 st bit to the 11 th bit of the rotating speed signal data represent rotating speed signals of a main pump, and the 12 th bit to the 15 th bit of the rotating speed signal data represent switching value signals; therefore, when the time interval is received in Flash, the uniquely corresponding rotation speed signal data can be obtained, as shown in fig. 3, for example, a binary value corresponding to 1500rpm exists in the comparison table when the pulse interval time of 40ms exists, that is, the binary value corresponding to 1500rpm of the first 11-bit stored rotation speed value can be found in Flash, so as to obtain the corresponding rotation speed signal data.

S3: acquiring an analog quantity signal and a switching value signal according to the rotating speed signal data;

specifically, since the 1 st to 11 th bits of the rotation speed signal data are rotation speed signals of the main pump, the 1 st to 11 th bits of the rotation speed signal data are subjected to DA conversion, so that a current signal (i.e., an analog signal) within a range of 4mA to 20mA can be obtained;

since the 12 th to 15 th bits of the rotation speed signal data are switching value signals, and there is a return difference (usually 1%) between the low and low switching values during normal use, the output of the switching value is realized by the logic loop control technology in this embodiment, specifically as follows:

as shown in fig. 4, the rotation speed signal may be represented by dividing the low and low (assuming that the low constant is 1393rpm, the low constant is 1365rpm, and the constant return difference is 18rpm) variation states into 6 sections by size, where L0 and LL0 represent low threshold trigger and low threshold trigger during rotation speed decrease, respectively, and L1 and LL1 represent low threshold release and low threshold release during rotation speed increase, respectively. Therefore, in the embodiment, according to the variation status, corresponding data is stored in the 12 th bit to the 15 th bit of Flash, for example, the pulse interval time of 43ms corresponds to 1395rpm, according to fig. 4, the values of L0, L1, LL0 and LL1 are 0, 1, 0 and 0, so that 0, 1, 0 and 0 correspond to the 12 th bit to the 15 th bit of Flash stored in the address of 43 ms; when the switching value signal needs to be output subsequently, the address change circuit judges whether the switching value at the moment outputs the value corresponding to L0 and LL0 or the value corresponding to L1 and LL 1. Namely, a corresponding switching value signal is output by judging whether the rotating speed of the main pump is in an ascending state or a descending state; when the rotation speed of the main pump is in a rising state, the corresponding values of L1 and LL1 are output, and when the rotation speed of the main pump is in a falling state, the corresponding values of L0 and LL0 are output, so that low-rotation and low-switching-value signals are obtained.

It should be noted that the address change circuit is a prior art, and the present application does not relate to an improvement thereof, and therefore, it is not described in an excessive way.

Example 2

In order to ensure the correctness of the output data and perform self-check on the circuit structure, the digital logic hardware circuit in this embodiment further includes a parity check chip for performing odd check or even check on the data in Flash. Specifically, the method comprises the following steps:

the revolution speed signal data in the present embodiment is binary data of 16 bits, wherein the 1 st to 11 th bits of the binary data represent the revolution speed signal of the main pump, the 12 th bit of the binary data represents the parity check signal, and the 13 th to 16 th bits of the binary data represent the switching value signal. The 12 th bit value assigns 1 or 0 to the 12 th bit according to the number of 1's in the 1 st bit to the 11 th bit and the 13 th to 16 th bits, so that the 16 th bit output result in Flash is maintained as odd number of 1's, when the output is detected as even number of 1's, the data output error is indicated, (even parity is even number of 1's, when the output is detected as odd number of 1's, the data output error is indicated), thereby judging whether the circuit structure has error or not

In specific implementation, the processing flow of step S1 and step S2 is the same as that of embodiment 1, and when going to step S3, unlike embodiment 1, step S3 of this embodiment first determines whether the rotation speed signal data is valid by using a parity check chip, and when the rotation speed signal data is valid, acquires an analog signal and a switching value signal; when the rotating speed signal data is invalid, an error is reported to prompt that the circuit has a fault and needs to be maintained.

Example 3

The embodiment provides a main pump rotating speed signal processing system based on a digital logic hardware circuit, which comprises:

the processing module is used for preprocessing the quasi-sinusoidal pulse signals generated by the sensor in real time to obtain standard square wave signals;

the searching module is used for acquiring the period of the square wave signal and acquiring prestored rotating speed signal data according to the period and the comparison table; wherein, the comparison table is the corresponding relation between each period and each rotating speed signal data;

and the processing module is used for acquiring the analog quantity signal and the switching value signal according to the rotating speed signal data.

Specifically, the rotational speed signal data in the present embodiment is binary data of 15 bits, and the 1 st bit to 11 th bit of the binary data represent the rotational speed signal of the main pump, and the 12 th bit to 15 th bit of the binary data represent the switching value signal.

Based on the rotational speed signal data, the processing module in this embodiment includes:

the conversion unit is used for carrying out DA conversion on the 1 st bit to the 11 th bit of the binary data to obtain an analog quantity signal;

the comparison unit is used for comparing the period of the square wave signal at the current moment with the period of the square wave signal at the previous moment;

the output unit is used for outputting numerical values corresponding to the 13 th bit and the 15 th bit of the binary data when the period of the square wave signal at the current moment is smaller than the period of the square wave signal at the previous moment; otherwise, outputting the corresponding numerical values of the 12 th bit and the 14 th bit.

Example 4

In order to ensure the correctness of output data and perform self-checking on the circuit structure, the present embodiment is different from embodiment 3 in that the rotation speed signal data in the present embodiment is binary data of 16 bits, and the 1 st bit to 11 th bit of the binary data represent the rotation speed signal of the main pump, the 12 th bit represents a parity check signal, and the 13 th bit to 16 th bit represents a switching value signal.

Based on this, the processing module in this embodiment includes:

the judging unit is used for judging whether the rotation speed signal data is valid by adopting a parity check method;

the conversion unit is used for performing DA conversion on the 1 st bit to the 11 th bit of the binary data to obtain an analog quantity signal when the rotating speed signal data is effective;

the comparison unit is used for comparing the period of the square wave signal at the current moment with the period of the square wave signal at the previous moment;

the output unit is used for outputting numerical values corresponding to the 13 th bit and the 15 th bit of the binary data when the period of the square wave signal at the current moment is smaller than the period of the square wave signal at the previous moment; otherwise, outputting the corresponding numerical values of the 12 th bit and the 14 th bit.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.