阅读说明：本技术 一种凹型电荷俘获层突触晶体管及其制备方法 (Concave type charge trapping layer synaptic transistor and preparation method thereof ) 是由 黎明 李小康 李海霞 陈珙 黄如 于 2021-09-02 设计创作，主要内容包括：本发明公开了一种凹型电荷俘获层突触晶体管及其制备方法,属于面向神经网络硬件化应用的突触器件领域。本发明采用的凹型电荷俘获层结构便于通过首次编程将电荷隧穿到俘获层,而后通过若编程的方式改变电荷俘获位置的方式来降低操作电压；另一方面,通过在栅源或者栅漏之间的电压脉冲控制电荷在俘获层中的横向位置实现多值存储,从而提高神经网络的精度。(The invention discloses a concave charge trapping layer synaptic transistor and a preparation method thereof, belonging to the field of synaptic devices for neural network hardware application. The concave charge trapping layer structure adopted by the invention is convenient for tunneling charges to the trapping layer through first programming, and then the operation voltage is reduced by changing the charge trapping position in a programming mode; on the other hand, multivalue storage is achieved by controlling the lateral position of charges in the trapping layer by voltage pulses between the gate source or the gate drain, thereby improving the accuracy of the neural network.)

1. A charge trapping type synapse transistor comprises a semiconductor substrate, a source region, a drain region and a channel region, wherein the source region and the drain region are formed on the semiconductor substrate, and a lightly doped channel region is connected with the source region and the drain region; the synapse transistor is characterized in that a charge trapping layer of the synapse transistor is of a concave structure, and a tunneling oxide layer, a concave charge trapping layer, a blocking layer and a metal gate are sequentially arranged from the surface of a channel region to the outside; and forming a device isolation region between the devices in an island isolation manner, wherein the isolation layer covers the whole device and is used as a metal leading-out layer of the source drain gate.

2. The charge-trapping synapse transistor of claim 1, wherein the semiconductor substrate is a bulk silicon substrate or a bulk germanium substrate.

3. The charge-trapping synapse transistor of claim 1, wherein the charge-trapping layer is selected from hafnium oxide, silicon nitride, and tantalum oxide, and has a maximum thickness of 5-8 nm, and the recessed region has a thickness of 1-2 nm.

4. The charge-trapping synapse transistor of claim 1, wherein the tunneling oxide layer is selected from silicon oxide, aluminum oxide, and has a thickness of 1-2 nm; the barrier layer is made of aluminum oxide or silicon oxide and is 7-10 nm thick.

5. The charge-trapping synapse transistor of claim 1, wherein the metal gate is made of titanium nitride or tantalum nitride and has a thickness of 50-80 nm.

6. A method for fabricating a charge-trapping synapse transistor as claimed in any of claims 1-5, comprising the steps of:

1) forming a well region in a semiconductor substrate and performing shallow trench isolation;

2) forming a tunneling oxide layer on the surface of the semiconductor substrate;

3) depositing a charge trapping layer on the tunneling oxide layer, defining a groove etching area through a photoetching technology, exposing to form a mask, etching the groove area of the charge trapping layer to a certain depth, wherein the etching depth is smaller than the thickness of the charge trapping layer, and thus forming the charge trapping layer with a concave structure;

4) depositing a barrier layer medium on the charge trapping layer with the concave structure, flattening the surface, and then sequentially depositing a metal gate electrode layer and a silicon oxide hard mask layer;

5) defining a metal gate region by using a photoetching technology, etching a silicon oxide hard mask, and etching a metal gate electrode layer, a barrier layer, a charge trapping layer and a tunneling oxide layer to a substrate by using the silicon oxide hard mask as a shield;

6) injecting source and drain doping impurities by taking the silicon oxide layer on the gate as a hard mask, and quickly annealing and activating the source and drain impurities;

7) depositing a silicon nitride layer and etching to form a silicon nitride side wall;

8) and depositing a silicon oxide isolation layer, flattening the surface, and then manufacturing metal extraction of a source drain gate.

7. The preparation method according to claim 6, wherein in step 8), after depositing the silicon oxide isolation layer and carrying out surface planarization, defining a via region by a photolithography technique, and etching to form a gate and a source-drain via, depositing metal and annealing to form a metal silicide in the source-drain via; and then depositing a metal adhesion layer and a metal interconnection layer in sequence, defining an interconnection line by a photoetching technology, and etching the metal layer to form the interconnection line.

8. The method of claim 7, wherein step 8) deposits Ni, Ti, or Co metal in the via hole, and then anneals to form a metal silicide.

9. The method according to claim 6, wherein the step 2) forms a tunnel oxide layer on the surface of the semiconductor substrate by oxidation; depositing a charge trapping layer by an atomic layer deposition method in the step 3); depositing a barrier layer by an atomic layer deposition method in the step 4); depositing silicon oxide by adopting a low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition method in the steps 4) and 8); and 4) depositing a metal layer in the steps 4) and 8) by adopting a magnetron sputtering or metal evaporation deposition mode.

10. The production method according to claim 6, wherein the surface planarization is performed by chemical mechanical polishing; the etching adopts reactive ion etching or inductively coupled plasma etching; the impurity activation means is one of rapid thermal annealing, laser annealing, spike annealing, and blaze annealing.

Technical Field

The invention belongs to the field of synapse devices for neural network hardware application, and relates to a low-voltage multivalued concave charge trapping layer synapse transistor and a preparation method thereof.

Background

Neuromorphic computing is a novel computing system aimed at simulating a highly parallel, highly fault-tolerant, low-power-consuming biological nervous system, which exhibits superior performance when dealing with recognition, classification, and decision-making tasks, as compared to the traditional von neumann-based computing system. The neuromorphic computing needs to be developed from multiple aspects such as devices, circuits and system architectures one by one, and the bottom-layer synapse devices and synapse networks provide a foundation for building a complex neuromorphic computing system.

The existing artificial synapse devices are mainly divided into two-end synapse devices and three-end synapse devices, and the two-end synapse devices such as Resistive Random Access Memories (RRAMs) have the advantages of simple structure and high-density integration, but have the problems of large fluctuation, poor reliability and the like; three-terminal synaptic devices such as ion-gated synaptic transistors and charge-trapping synaptic transistors, most of which are fabricated on the basis of organic materials or two-dimensional materials, have difficulty in integration with CMOS circuits and reliability problems of devices with small dimensions. On the other hand, when a Flash memory (Flash) device based on a traditional Very Large Scale Integration (VLSI) technology is used as a synapse, the problem of high operating voltage exists, and most Flash memory devices can only realize binary storage and cannot be used for simulating a neural network.

Therefore, a synapse device with low voltage polymorphism is urgently needed for a low-power consumption analog neural network in the future.

Disclosure of Invention

In view of the above problems, the present invention provides a concave type charge trapping layer synapse device, which can greatly reduce the operation voltage by first programming and then changing the charge trapping position, i.e. by weak programming. In addition, the charge trapping layer of the synapse device is of a concave structure, and multi-value storage is realized by applying a voltage pulse between a grid source and a grid drain to change the lateral position of trapped charges during operation.

The invention provides a charge trapping type synaptic transistor, which comprises a semiconductor substrate, a source region, a drain region and a channel region, wherein the source region and the drain region as well as a lightly doped channel region connecting the source region and the drain region are formed on the semiconductor substrate; the synapse transistor is characterized in that a charge trapping layer of the synapse transistor is of a concave structure, and a tunneling oxide layer, a concave charge trapping layer, a blocking layer and a metal gate are sequentially arranged from the surface of a channel region to the outside; and forming a device isolation region between the devices in an island isolation manner, wherein the isolation layer covers the whole device and is used as a metal leading-out layer of the source drain gate.

In the above charge trapping type synapse transistor, the semiconductor substrate may be a bulk silicon substrate or a bulk germanium substrate.

In the charge trapping type synaptic transistor, the charge trapping layer is of a concave structure, the size of the concave region is defined by a photoetching technology, and the depth of the concave region is determined by etching time. In order to ensure charge trapping efficiency and charge storage capacity, the maximum thickness of the charge trapping layer is about 5-8 nm, and the thickness of the concave region is 1-2 nm. The material of the charge trapping layer is preferably hafnium oxide (HfO)₂) Silicon nitride (Si)₃N₄) And tantalum oxide (Ta)₂O₅) And the like.

In the charge trapping type synapse transistor, the tunneling oxide layer is preferably made of silicon oxide, aluminum oxide or the like, and the thickness is preferably 1-2 nm.

In the synapse transistor, the dielectric material of the blocking layer is preferably aluminum oxide (Al)₂O₃) Silicon oxide (SiO)₂) And the thickness is preferably 7 to 10 nm.

In the charge trapping type synapse transistor, the gate electrode is a metal gate, preferably made of titanium nitride, tantalum nitride, or the like, and preferably has a thickness of 50 to 80 nm.

The invention also provides a preparation method of the charge trapping type synaptic transistor with the concave charge trapping layer, which comprises the following steps:

1) forming a well region in a semiconductor substrate and performing conventional Shallow trench isolation (SIT);

2) forming a tunneling oxide layer on the surface of the semiconductor substrate;

3) depositing a charge trapping layer on the tunneling oxide layer, defining a groove etching area through a photoetching technology, exposing to form a mask, etching the groove area of the charge trapping layer to a certain depth, wherein the etching depth is smaller than the thickness of the charge trapping layer, and thus forming the charge trapping layer with a concave structure;

4) depositing a barrier layer medium on the charge trapping layer with the concave structure, flattening the surface, and then sequentially depositing a metal gate electrode layer and a silicon oxide hard mask layer;

5) defining a metal gate region by using a photoetching technology, etching a silicon oxide hard mask, and etching a metal gate electrode layer, a barrier layer, a charge trapping layer and a tunneling oxide layer to a substrate by using the silicon oxide hard mask as a shield;

6) injecting source and drain doping impurities by taking the silicon oxide layer on the gate as a hard mask, and quickly annealing and activating the source and drain impurities;

7) depositing a silicon nitride layer and etching to form a silicon nitride side wall;

8) and depositing a silicon oxide isolation layer, flattening the surface, and then manufacturing metal extraction of a source drain gate.

Further, after depositing a silicon oxide isolation layer and carrying out surface planarization in the step 8), defining a through hole region through a photoetching technology, etching to form a gate and a source-drain through hole, depositing metal and annealing, and forming metal silicide in the source-drain through hole, so that the effect of reducing the contact resistivity of the source-drain is achieved; and then depositing a metal adhesion layer and a metal interconnection layer in sequence, defining an interconnection line by a photoetching technology, and etching the metal layer to form the interconnection line.

And finally, depositing a silicon oxide buffer layer, flattening the surface, and then depositing a silicon nitride passivation layer to finish the preparation of the device.

Further, in the step 2), a tunnel oxide layer is formed on the surface of the semiconductor substrate by an oxidation method, which may be dry oxygen oxidation or hydrogen-oxygen synthesis oxidation.

Further, the charge trapping Layer in step 3) is deposited by Atomic Layer Deposition (ALD), and the like.

Further, the photolithography technique used in the above-described manufacturing method is a photolithography technique capable of defining a nano-scale, such as 193nm ultraviolet lithography.

Further, the Etching technique used in the above preparation method may be Reactive Ion Etching (RIE), Inductively Coupled Plasma Etching (ICPE), and the like.

Further, the Deposition of the barrier Layer in step 4) may employ Atomic Layer Deposition (ALD) or the like.

Further, the planarization manner in steps 4) and 8) is preferably Chemical Mechanical Polishing (CMP).

Furthermore, in the above preparation method, the Metal layer may be deposited by Physical Vapor Deposition (PVD), such as Magnetron Sputtering (Magnetron Sputtering) and Metal Evaporation (Metal Evaporation).

Further, the silicon oxide layer in steps 4) and 8) may be deposited by Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD).

Further, the impurity activation in step 6) is one of Rapid Thermal Annealing (RTA), Laser Annealing (Laser Annealing), Spike Annealing (Spike Annealing), and Flash Annealing (Flash Annealing).

Further, in the step 8), the metal for forming the metal silicide in the source-drain via hole may be selected from Ni, Ti, Co, and the like.

The invention has the following advantages and positive effects:

1) according to the charge trapping type synaptic transistor with the concave charge trapping layer, the concave charge trapping layer structure is convenient for tunneling charges to the trapping layer through first programming, and then the operating voltage is reduced in a mode of changing charge trapping positions through weak programming;

2) the concave trap layer design is convenient for controlling the transverse position of charges in the trap layer through voltage pulses between a grid source and a grid drain, so that multi-value storage is realized, and the precision of the neural network is improved.

Drawings

FIGS. 1 to 13 are schematic diagrams of key process steps for fabricating a synaptic transistor with a concave charge-trapping layer; in each figure, (a) is a plan view, (B) is a sectional view taken along the direction A-A ', and (c) is a sectional view taken along the direction B-B'. Wherein:

FIG. 1 is a process of forming a P-well and STI isolation on a bulk silicon substrate;

FIG. 2 is a process of forming a tunneling oxide layer on the surface of a bulk silicon substrate by thermal oxidation;

FIG. 3 illustrates a hafnium oxide charge-trapping layer deposited on a surface of a tunneling oxide layer;

FIG. 4 is a schematic diagram of spin-coating a photoresist on the surface of the hafnium oxide charge-trapping layer, and exposing to form an etching mask;

FIG. 5 illustrates etching a hafnium oxide charge-trapping layer to form a concave structure, followed by photoresist stripping;

FIG. 6 is a sequential deposition of an alumina barrier layer, a titanium nitride metal gate layer, and a silicon oxide hard mask layer;

FIG. 7 is a schematic representation of a patterned silicon oxide layer with silicon oxide as a hard mask, with a titanium nitride metal gate, an aluminum oxide barrier layer, a hafnium oxide charge trapping layer, and a tunneling oxide layer etched to the bulk silicon surface;

FIG. 8 is a schematic diagram of a process for source-drain impurity implantation and annealing for activation using a patterned silicon oxide hard mask as an implantation blocking layer;

FIG. 9 is a silicon nitride layer deposited and anisotropically etched to form spacers;

FIG. 10 is a deposition of a silicon oxide isolation layer and surface planarization;

FIG. 11 is a schematic view showing that a via hole is defined above a source drain region and a gate region by photolithography, and is etched to form a source drain gate via hole;

FIG. 12 is a deposition of a metal conductive layer and etching to form metal interconnect lines;

fig. 13 is a sequence of depositing a silicon oxide buffer layer and a silicon nitride passivation layer.

Fig. 14 is an illustration of the materials used in fig. 1-13.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings by way of specific examples.

As shown in fig. 1 to 13, the steps of preparing the synapse transistor with concave charge trapping layer are as follows: forming a source region, a drain region and a lightly doped channel region connecting the source region and the drain region on a silicon substrate, and forming an isolation region between devices in a shallow trench isolation mode; growing silicon oxide on the surface of the channel region through thermal oxidation, depositing to form a hafnium oxide charge trapping layer, and etching to form a concave structure; then depositing an alumina barrier layer in sequence, flattening and depositing a titanium nitride metal gate electrode; and opening a window on the isolation layer until the upper surfaces of the source region, the drain region and the metal gate electrode are exposed, depositing metal to fill the through hole after forming metal silicide, and performing metal interconnection. The following description will be made by taking the preparation of an N-type synapse transistor as an example:

1) forming P-well and STI isolation on silicon substrate by implanting impurity P into P-type silicon substrate⁺Then annealing is carried out to carry out well advancing to form a P-type impurity well surrounded by an N-type impurity region, and then a silicon oxide isolation region is formed around the well according to a common shallow trench isolation step: depositing silicon nitride as a CMP stop layer, patterning the silicon nitride layer as an etching mask, etching the silicon substrate and depositing silicon oxide by CVD, patterning the surface of the substrate by CMP and removing the silicon nitride by hot phosphoric acid, as shown in FIG. 1;

2) forming a tunneling oxide layer of 2nm on the surface of the silicon substrate by thermal oxidation, as shown in fig. 2;

3) depositing 5nm hafnium oxide on the surface of the tunneling oxide layer by using an ALD (atomic layer deposition) technology to serve as a charge trapping layer, as shown in FIG. 3;

4) defining a charge trapping layer etching area by a photoetching technology (figure 4), etching the charge trapping layer into a concave structure by an RIE technology and removing photoresist, as shown in figure 5;

5) depositing an alumina barrier layer with the thickness of 8nm by ALD, performing surface CMP planarization, and then sequentially depositing a titanium nitride metal gate with the thickness of 60nm and a silicon oxide hard mask with the thickness of 100nm, as shown in FIG. 6;

6) patterning the metal gate by photolithography, etching to form a silicon oxide hard mask of the metal gate, and etching the titanium nitride metal gate, the aluminum oxide barrier layer, the hafnium oxide charge trapping layer and the tunneling oxide layer to the surface of the silicon, as shown in fig. 7;

7) using silicon oxide hard mask As barrier layer, injecting source-drain impurity As⁺The implantation dose is 5 × 10¹⁵cm^-2The implantation energy is 33 keV; then the operation is carried out rapidlyPerforming source-drain impurity activation by thermal annealing at 900 ℃ for 10s, as shown in FIG. 8;

8) depositing a silicon nitride layer with the thickness of 100nm by LPCVD (low pressure chemical vapor deposition), and performing anisotropic etching to form a silicon nitride side wall, as shown in FIG. 9;

9) a 300nm thick silicon oxide isolation layer was deposited by PECVD and the surface planarized as shown in fig. 10;

10) defining a source-drain gate through hole by using a photoetching technology, then selecting a program of etching selection ratio of silicon and titanium nitride, etching to form the source-drain gate through hole, sputtering metal nickel with the thickness of 3nm, forming nickel silicon in the source-drain through hole after annealing, and removing nickel residues on the surfaces of the metal gate and the side wall by wet etching, as shown in FIG. 11;

11) sputtering metal titanium with the thickness of 30nm and metal aluminum with the thickness of 1 mu m, then defining a metal interconnection line by a photoetching technology, and etching to form the metal interconnection line, as shown in figure 12;

12) a 30nm buffer layer of silicon oxide and a 100nm passivation layer of silicon nitride are deposited by PECVD as shown in figure 13.

For the preparation of a P-type synapse transistor, an N-type silicon substrate is adopted, and the light doping injection impurities of the step 1) are injected from P⁺Changed into BF₂ ⁺Implanting impurities from As into the source-drain doping of the step 7)⁺Changed into BF₂ ⁺The other conditions remain unchanged.

The embodiments of the present invention are not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present invention, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.