阅读说明：本技术 一种锁相环频率综合器 (Phase-locked loop frequency synthesizer ) 是由 韩怀宇 赵伟兵 邵要华 于 2021-09-29 设计创作，主要内容包括：本发明公开一种锁相环频率综合器,包括：前置分频器,用于接收外部电路输入的时钟信号,并对时钟信号进行分频；锁相环电路,用于接收所述前置分频器输出的分频后的时钟信号,并输出2N个相位依次变化的时钟信号；N倍频电路,包括或门、N级异或门和N级与门,用于接收所述锁相环电路输出的2N个相位依次变化的时钟信号,并将2N个相位依次变化的时钟信号进行倍频处理,以输出一个N倍频的最终时钟信号作为所述锁相环频率综合器输出的时钟信号。本发明在实现高频时钟信号输出的同时大幅度降低频率综合器的功耗,且本发明的N倍频电路不受时钟信号占空比的影响,无需采用占空比校正电路,简化频率综合器结构。(The invention discloses a phase-locked loop frequency synthesizer, comprising: the pre-frequency divider is used for receiving a clock signal input by an external circuit and dividing the frequency of the clock signal; the phase-locked loop circuit is used for receiving the frequency-divided clock signals output by the pre-frequency divider and outputting 2N clock signals with sequentially changed phases; and the N frequency multiplication circuit comprises an OR gate, an N-level XOR gate and an N-level AND gate and is used for receiving the 2N clock signals with sequentially changed phases output by the phase-locked loop circuit and carrying out frequency multiplication processing on the 2N clock signals with sequentially changed phases so as to output a final N-frequency-multiplied clock signal as the clock signal output by the phase-locked loop frequency synthesizer. The invention greatly reduces the power consumption of the frequency synthesizer while realizing the output of the high-frequency clock signal, and the N frequency multiplier circuit of the invention is not influenced by the duty ratio of the clock signal, does not need to adopt a duty ratio correction circuit, and simplifies the structure of the frequency synthesizer.)

1. A phase-locked loop frequency synthesizer is characterized by comprising a pre-frequency divider, a phase-locked loop circuit and an N frequency multiplication circuit;

the pre-frequency divider is used for receiving a clock signal input by an external circuit and dividing the frequency of the clock signal;

the phase-locked loop circuit is used for receiving the frequency-divided clock signals output by the pre-frequency divider and outputting 2N clock signals with sequentially changed phases;

the N frequency multiplication circuit comprises an OR gate, an N-level XOR gate and an N-level AND gate, and is used for receiving 2N clock signals with sequentially changed phases output by the phase-locked loop circuit and carrying out frequency multiplication processing on the 2N clock signals with sequentially changed phases so as to output a final N-frequency-multiplied clock signal as the clock signal output by the phase-locked loop frequency synthesizer;

wherein N is a positive integer multiple of 2.

2. The pll frequency synthesizer according to claim 1, wherein the prescaler comprises an input terminal and an output terminal, the input terminal of the prescaler is used as the input terminal of the pll frequency synthesizer for receiving a clock signal input from an external circuit; the pre-frequency divider divides the frequency of the clock signal input by the external circuit and transmits the divided clock signal to the phase-locked loop circuit through the output end of the pre-frequency divider.

3. The pll frequency synthesizer according to claim 2, wherein the pll circuit comprises an input terminal and 2N output terminals, the input terminal of the pll circuit being connected to the output terminal of the prescaler for enabling the pll circuit to receive the divided clock signal transmitted by the prescaler.

4. The pll frequency synthesizer of claim 3, wherein the pll circuit comprises: the phase frequency detector, the charge pump, the low-pass filter, the voltage-controlled oscillator and the loop frequency divider;

the phase frequency detector comprises a first input end, a second input end and an output end, wherein the first input end of the phase frequency detector is used as the input end of the phase-locked loop circuit, and the first input end of the phase frequency detector is connected with the output end of the pre-frequency divider and used for receiving the clock signal output by the pre-frequency divider after frequency division;

the charge pump comprises an input end and an output end, and the input end of the charge pump is connected with the output end of the phase frequency detector;

the low-pass filter comprises an input end and an output end, and the input end of the low-pass filter is connected with the output end of the charge pump;

the voltage-controlled oscillator comprises an input end, and the input end of the voltage-controlled oscillator is connected with the output end of the low-pass filter;

the loop frequency divider comprises an input end and an output end, and the output end of the loop frequency divider is connected with the second input end of the phase frequency detector and is used for dividing the frequency of the clock signal to generate a feedback clock signal and outputting the feedback clock signal.

5. The phase-locked loop frequency synthesizer of claim 4, wherein the voltage controlled oscillator is a ring oscillator of a differential architecture.

6. The PLL frequency synthesizer according to claim 4, wherein the voltage controlled oscillator comprises 2N outputs, and the 2N outputs of the voltage controlled oscillator serve as the 2N outputs of the PLL circuit for outputting 2N clock signals with sequentially changing phases to the N-multiplier circuit.

7. The PLL frequency synthesizer according to claim 6, wherein the Nmultiplying circuit comprises an output terminal and 2N input terminals, the 2N input terminals of the Nmultiplying are connected to the 2N output terminals of the PLL circuit for receiving the 2N clock signals with sequentially changing phase outputted from the PLL circuit, and the Nmultiplying output terminal is used as the output terminal of the PLL frequency synthesizer for outputting an Nmultiplying final output signal as the clock signal outputted from the PLL frequency synthesizer.

8. The phase-locked loop frequency synthesizer of claim 7, wherein there is one of the 2N outputs of the voltage-controlled oscillator that is connected to both an input of the frequency-N multiplier circuit and the input of the loop divider.

9. The pll frequency synthesizer according to claim 7, wherein each stage of the xor gate in the N-stage frequency multiplier circuit comprises two inputs and an output, and the 2N inputs of the xor gate in the N-stage frequency multiplier circuit are 2N inputs of the N-stage frequency multiplier circuit for receiving 2N clock signals with sequentially changing phases output by the pll circuit.

10. The pll frequency synthesizer of claim 9, wherein each and gate of the N-multiplier circuit comprises a first input terminal, a second input terminal and an output terminal, and the first input terminal of each and gate is connected to the output terminal of the corresponding xor gate for receiving the clock signal outputted from the xor gate.

11. The pll frequency synthesizer according to claim 10, wherein the second input of each and gate in the N-multiplier circuit is connected to the designated input of the designated xor gate; and the phase of the clock signal input by the appointed input end of the appointed stage of exclusive-OR gate is lagged by 3pi/2 compared with the phase of the clock signal input by the first input end of the stage of AND gate.

12. The pll frequency synthesizer according to claim 11, wherein the or gate of the N-multiplier circuit comprises N input terminals and an output terminal, the N input terminals of the or gate are respectively connected to the N output terminals of the N-level and gate for receiving N clock signals outputted from the N-level and gate, and the output terminal of the or gate serves as the output terminal of the N-multiplier circuit for outputting an N-multiplied final output signal as the clock signal outputted from the pll frequency synthesizer.

Technical Field

The invention relates to the field of circuit design, in particular to a phase-locked loop frequency synthesizer.

Background

The frequency synthesizer is a key device commonly used in modern communication systems, radars and test equipment, and can provide high-precision and stable frequency. However, the frequency synthesizer adopted in the prior art still has a problem of large power consumption, and it is difficult to reduce the power consumption of the frequency synthesizer generally by adopting a phase-locked loop structure, because a voltage-controlled oscillator module generating a clock signal in the phase-locked loop structure needs to consume more energy to generate the clock signal of a target frequency, when the target frequency is higher, the power consumption of the frequency synthesizer is higher. At present, in the prior art, frequency multiplication processing is performed on a clock signal output by a voltage-controlled oscillator to output a clock signal of a target frequency, but the requirement of the frequency multiplication processing on the duty ratio of the clock signal is high, and a corresponding duty ratio correction circuit needs to be designed.

Disclosure of Invention

In order to solve the above problems, the present invention provides a phase-locked loop frequency synthesizer, which can greatly reduce the power consumption of the frequency synthesizer while realizing the output of a high-frequency clock signal, and the frequency multiplication processing of the phase-locked loop frequency synthesizer of the present invention is not affected by the duty ratio of the clock signal, and does not need to adopt a duty ratio correction circuit, thereby simplifying the structure of the frequency synthesizer. The specific technical scheme of the invention is as follows:

a phase-locked loop frequency synthesizer comprises a pre-frequency divider, a phase-locked loop circuit and an N frequency multiplication circuit; the pre-frequency divider is used for receiving a clock signal input by an external circuit and dividing the frequency of the clock signal; the phase-locked loop circuit is used for receiving the frequency-divided clock signals output by the pre-frequency divider and outputting 2N clock signals with sequentially changed phases; the N frequency multiplication circuit comprises an OR gate, an N-level XOR gate and an N-level AND gate, and is used for receiving 2N clock signals with sequentially changed phases output by the phase-locked loop circuit, multiplying the 2N clock signals with sequentially changed phases, and outputting a final N-frequency-multiplied clock signal as the clock signal output by the phase-locked loop frequency synthesizer; wherein N is a positive integer multiple of 2.

Compared with the prior art, the technical scheme has the advantages that the N frequency doubling circuit is arranged in the phase-locked loop frequency synthesizer, the phase-locked loop circuit outputs the low-frequency clock signal and the frequency is doubled by the N frequency doubling circuit to achieve the target frequency, so that the overall power consumption of the frequency synthesizer is reduced, the special design of the N frequency doubling circuit in the technical scheme enables the frequency synthesizer to be free of specially designing a duty ratio correction circuit, the N frequency doubling circuit in the technical scheme has no requirement on the duty ratio of the input clock signal, the frequency doubling effect is not influenced by the duty ratio of the clock signal, the structure of the frequency synthesizer is simplified, and the flexibility of the frequency synthesizer is improved.

Furthermore, the prescaler comprises an input end and an output end, and the input end of the prescaler is used as the input end of the phase-locked loop frequency synthesizer and is used for receiving a clock signal input by an external circuit; the pre-frequency divider divides the frequency of the clock signal input by the external circuit and transmits the divided clock signal to the phase-locked loop circuit through the output end of the pre-frequency divider. Compared with the prior art, the pre-frequency divider arranged in the technical scheme regulates and controls the frequency dividing number of the pre-frequency divider according to the frequency multiplying factor of the N frequency multiplying circuit of the frequency synthesizer, the frequency of the clock signal input by the external circuit and the preset step length, so that the step length of the clock signal output by the frequency synthesizer is equal to the preset step length.

Furthermore, the phase-locked loop circuit comprises an input end and 2N output ends, wherein the input end of the phase-locked loop circuit is connected with the output end of the pre-frequency divider, and is used for receiving the frequency-divided clock signal transmitted by the pre-frequency divider. The phase-locked loop circuit of the technical scheme is connected with the pre-frequency divider, receives the clock signal after frequency division adjustment, and achieves step length pre-adjustment of the clock signal output by the frequency synthesizer.

Further, the phase-locked loop circuit specifically includes: the phase frequency detector, the charge pump, the low-pass filter, the voltage-controlled oscillator and the loop frequency divider; the phase frequency detector comprises a first input end, a second input end and an output end, wherein the first input end of the phase frequency detector is used as the input end of the phase-locked loop circuit, and the first input end of the phase frequency detector is connected with the output end of the pre-frequency divider and used for receiving the clock signal output by the pre-frequency divider after frequency division; the charge pump comprises an input end and an output end, and the input end of the charge pump is connected with the output end of the phase frequency detector; the low-pass filter comprises an input end and an output end, and the input end of the low-pass filter is connected with the output end of the charge pump; the voltage-controlled oscillator comprises an input end, and the input end of the voltage-controlled oscillator is connected with the output end of the low-pass filter; the loop frequency divider comprises an input end and an output end, and the output end of the loop frequency divider is connected with the second input end of the phase frequency detector and is used for dividing the frequency of the clock signal to generate a feedback clock signal and outputting the feedback clock signal. According to the technical scheme, the loop frequency divider is arranged in the phase-locked loop circuit, so that the loop frequency divider divides the frequency of the clock signal output by the voltage-controlled oscillator to obtain a feedback clock signal which is used for being compared with the clock signal input into the phase frequency detector by the pre-frequency divider, and whether the phase-locked loop circuit needs to perform feedback adjustment currently is determined according to the comparison result, so that the clock signal output by the phase-locked loop circuit can be output according to the target frequency.

Further, the voltage-controlled oscillator is a ring oscillator with a differential structure. In the technical scheme, the voltage-controlled oscillator in the phase-locked loop circuit is designed into the ring oscillator with the differential structure, so that the voltage-controlled oscillator can output multi-phase clock signals, and the multi-phase clock signals can be subjected to N frequency multiplication by combining with an N frequency multiplication circuit better.

Further, the voltage-controlled oscillator includes 2N output terminals, and the 2N output terminals of the voltage-controlled oscillator serve as the 2N output terminals of the phase-locked loop circuit, and are configured to output 2N clock signals with sequentially changing phases to the N-ary multiplier circuit. The voltage-controlled oscillator provided by the technical scheme respectively transmits 2N clock signals with sequentially changed phases to the N frequency doubling circuit so as to realize frequency doubling processing of the 2N clock signals with sequentially changed phases, so that the purpose that a phase-locked loop circuit in a frequency synthesizer outputs a low-frequency clock signal, the low-frequency clock signal is frequency-doubled by the N frequency doubling circuit and then outputs a clock signal with a target frequency is achieved, and therefore the power consumption of the frequency synthesizer is greatly reduced.

Further, the N-fold frequency circuit includes an output end and 2N input ends, where the 2N input ends of the N-fold frequency circuit are connected to the 2N output ends of the phase-locked loop circuit, and are configured to receive 2N clock signals output by the phase-locked loop circuit, where the output end of the N-fold frequency circuit is used as the output end of the phase-locked loop frequency synthesizer, and is configured to output a final output signal of the N-fold frequency as the clock signal output by the phase-locked loop frequency synthesizer. In the technical scheme, the N frequency multiplication circuit processes and outputs 2N clock signals with sequentially changed phases transmitted by the phase-locked loop circuit into an N frequency multiplication clock signal, so that the aims of outputting the low-frequency clock signal by the phase-locked loop circuit and outputting the clock signal by the frequency synthesizer at a target frequency are fulfilled.

Further, there is an output terminal in the 2N output terminals of the voltage-controlled oscillator, and the output terminal is connected to both an input terminal of the N frequency doubling circuit and an input terminal of the loop frequency divider. According to the technical scheme, one of 2N output ends of the voltage-controlled oscillator is selected to be connected with one input end of the N frequency doubling circuit and the input end of the loop frequency divider, so that frequency doubling of 2N clock signals with sequentially changed phases into one N frequency doubled clock signal can be realized, frequency division of one clock signal output by the voltage-controlled oscillator can be realized to serve as a feedback clock signal to perform feedback adjustment on the phase-locked loop circuit, and stability of the phase-locked loop circuit is guaranteed.

Furthermore, each stage of the xor gate in the N-stage frequency multiplier circuit includes two input terminals and an output terminal, and 2N input terminals included in the xor gate in the N-stage frequency multiplier circuit are used as 2N input terminals of the N-stage frequency multiplier circuit, and are configured to receive 2N clock signals output by the phase-locked loop circuit, where the 2N clock signals change in phase sequentially. In the technical scheme, N stages of exclusive-OR gates are arranged in an N frequency multiplier circuit to carry out exclusive-OR operation on 2N clock signals which are transmitted by a phase-locked loop circuit and change in phase in sequence, and N clock signals which are subjected to exclusive-OR operation are output.

Furthermore, each stage of the and gate in the N frequency multiplier circuit includes a first input terminal, a second input terminal, and an output terminal, and the first input terminal of each stage of the and gate is connected to the output terminal of the corresponding stage of the xor gate, and is configured to receive the clock signal output by the xor gate. In the technical scheme, N-level AND gates are arranged in an N-level frequency multiplier circuit to receive N clock signals which are output by N-level XOR gates and are subjected to XOR operation.

Furthermore, the second input end of each stage of AND gate in the N frequency multiplier circuit is connected with the specified input end of the specified stage of XOR gate; and the phase of the clock signal input by the appointed input end of the appointed stage of exclusive-OR gate is lagged by 3pi/2 compared with the phase of the clock signal input by the first input end of the stage of AND gate. In the technical scheme, the second input end of each stage of AND gate is connected with the specified input end of the specified stage of XOR gate, so that the phase difference of two clock signals input into the stage of AND gate is 3pi/2, the AND gate performs AND operation on the two input clock signals, one clock signal influenced by the duty ratio of the voltage-controlled oscillator signal is filtered out of the two clock signals output in one period of each stage of XOR gate, and the N frequency multiplier circuit is not influenced by the duty ratio of the clock signal output by the phase-locked loop circuit through the N stage of AND gate.

Further, the or gate in the N-ary frequency multiplier circuit includes N input terminals and an output terminal, the N input terminals of the or gate are respectively connected to the N output terminals of the N-ary and gate for receiving the clock signal output by the N-ary and gate, and the output terminal of the or gate serves as the output terminal of the N-ary frequency multiplier circuit for outputting an N-ary frequency multiplied final output signal as the clock signal output by the phase-locked loop frequency synthesizer. In the technical scheme, the OR gate is arranged in the N-stage frequency multiplier circuit to receive N AND-operated clock signals output by the N-stage AND gate and perform OR operation on the N AND-operated clock signals to output an N-stage frequency multiplied final output signal, so that the aim of low-power consumption and high-frequency output of the frequency synthesizer is fulfilled.

Drawings

Fig. 1 is a schematic structural diagram of a phase-locked loop frequency synthesizer according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a phase-locked loop frequency synthesizer according to another embodiment of the present invention.

Fig. 3 is a schematic structural diagram of an N-multiplier circuit according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clear, the present invention will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the following specific examples are illustrative only and are not intended to limit the invention. Moreover, it should be understood that the technical disclosure of the present invention may be modified by those skilled in the art by a conventional method, and it should not be understood that the technical disclosure of the present invention is not limited thereto.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. Reference to the words "a," "an," "the," and "the" in this application are not to be construed as limiting in number, and may mean singular or plural. The use of the terms "including," "comprising," "having," and any variations thereof herein, is intended to cover non-exclusive inclusions, such as: a process, method, system product or apparatus that comprises a list of steps or modules is not limited to the listed steps or elements but may include additional steps or elements not listed or inherent to such process, method, product or apparatus. Reference throughout this application to the terms "first," "second," "third," and the like are only used for distinguishing between similar references and not intended to imply a particular ordering for the objects.

In an embodiment of the present invention, a phase-locked loop frequency synthesizer is provided, as shown in fig. 1, the phase-locked loop frequency synthesizer includes: the frequency divider comprises a pre-frequency divider, a phase-locked loop circuit and an N frequency multiplier circuit; the pre-frequency divider is used for receiving a clock signal input by an external circuit, dividing the frequency of the clock signal and transmitting the divided frequency to the phase-locked loop circuit; the phase-locked loop circuit is used for receiving the clock signal after frequency division transmitted by the pre-frequency divider and outputting 2N clock signals with sequentially changed phases to the N frequency multiplier circuit; the N frequency multiplication circuit is used for receiving the 2N clock signals with sequentially changed phases output by the phase-locked loop circuit, and performing frequency multiplication processing on the 2N clock signals with sequentially changed phases to output a final N-frequency-multiplied clock signal as the clock signal output by the phase-locked loop frequency synthesizer. It should be noted that, the frequency of 2N clock signals output by the phase-locked loop circuit and sequentially changed in phase is output as a final output signal of N-fold frequency after being multiplied by the N-fold frequency circuit, and the frequency of the final output signal is equal to the target frequency of the phase-locked loop frequency synthesizer; where N is a positive integer multiple of 2, it is understood that the number N of frequency multiplication stages of the N frequency multiplication circuit may be, but is not limited to, a value of a positive integer multiple of 2, 4, 6, 8, 10, etc.

Specifically, the prescaler combines the N-times frequency multiplication of the N-times frequency multiplier circuit, so that the step length of the clock signal output by the phase-locked loop frequency synthesizer is equal to a preset step length. The frequency division number of the pre-frequency divider is adjustable, and is determined by the frequency of the clock signal input by the external circuit, the frequency multiplication number of the N frequency multiplication circuit and the preset step length. The preset step length is a step length preset according to a user in the practical application of the frequency synthesizer and is used for limiting the step length of the clock signal output by the phase-locked loop frequency synthesizer.

Based on the foregoing embodiment, the phase-locked loop frequency synthesizer provided in an embodiment of the present invention employs a pre-divider with an adjustable division number, where the division number of the pre-divider is adjusted according to an actual requirement of a user, so that the frequency synthesizer can output a clock signal with a preset step size, and a relationship between the division number of the pre-divider, the preset step size, a frequency of the clock signal input by the external circuit, and a number of frequency multiplication stages of an N frequency multiplication circuit of the frequency synthesizer satisfies: the ratio of the product of the frequency of the clock signal input by the external circuit and the frequency multiplication series of the N frequency multiplication circuit of the frequency synthesizer to the frequency division number of the pre-frequency divider is equal to the preset step length.

Based on the above embodiments, as a preferred embodiment of the present invention, a phase-locked loop frequency synthesizer is provided, in which a charge pump phase-locked loop circuit is adopted as a phase-locked loop circuit, and the charge pump phase-locked loop circuit is a typical representative of a digital-analog hybrid phase-locked loop circuit, and has irreplaceable advantages.

Specifically, as shown in fig. 2, the phase-locked loop circuit specifically includes: the phase frequency detector, the charge pump, the low pass filter, the voltage controlled oscillator and the loop frequency divider. The phase frequency detector comprises a first input end I, a second input end II and an output end, the first input end I of the phase frequency detector is used as the input end of the phase-locked loop circuit and is connected with the output end of the pre-frequency divider, the charge pump comprises an input end and an output end, the output end of the phase frequency detector is connected with the input end of the charge pump, the low-pass filter comprises an input end and an output end, the output end of the charge pump is connected with the input end of the low-pass filter, the voltage-controlled oscillator comprises an input end and 2N output ends, the output end of the low-pass filter is connected with the input end of the voltage-controlled oscillator, the 2N output ends of the voltage-controlled oscillator are used as the output ends of the phase-locked loop circuit, and the clock signal is used for transmitting the 2N clock signals with sequentially changed phases output by the phase-locked loop circuit to the N frequency multiplier circuit. It should be noted that, the 2N clock signals with sequentially changed phases output by the 2N output terminals of the voltage-controlled oscillator have the same frequency and different phases, specifically, the phase difference between two adjacent clock signals in the 2N clock signals with sequentially changed phases output by the voltage-controlled oscillator is pi/N, and the 2N clock signals with sequentially changed phases output by the voltage-controlled oscillator constitute one complete clock cycle of the voltage-controlled oscillator.

The loop frequency divider comprises an input end and an output end, the output end of the loop frequency divider is connected with the second input end of the phase frequency detector, the input end of the loop frequency divider is connected with one of 2N output ends of the voltage-controlled oscillator, and understandably, one output end of the 2N output ends of the voltage-controlled oscillator is connected with the input end of the loop frequency divider and is also connected with one input end of the N frequency doubling circuit, so that a clock signal output by the one output end of the voltage-controlled oscillator is transmitted to the loop frequency divider and is also transmitted to the N frequency doubling circuit.

Specifically, the loop frequency divider is configured to receive a clock signal transmitted by the voltage-controlled oscillator, divide the clock signal, transmit the divided clock signal to the second input end of the phase frequency detector as a feedback clock signal, compare the divided clock signal with a frequency-divided clock signal transmitted by a pre-divider and received by the first input end of the phase frequency detector, and perform feedback adjustment on the phase-locked loop circuit according to a comparison result until the output frequency of the voltage-controlled oscillator is stabilized as the clock signal of the target frequency, and determine that the phase-locked loop circuit is stable when the feedback clock signal and the frequency-divided clock signal transmitted by the pre-divider to the phase frequency detector are stable in the same frequency and phase. It should be noted that, when the phase-locked loop circuit is stabilized, the frequency of the clock signal output by the voltage-controlled oscillator of the phase-locked loop circuit is equal to the product of the frequency of the clock signal input by the prescaler after frequency division and the frequency division number of the loop frequency divider, so that the frequency of the clock signal output by the frequency synthesizer is equal to the product of the frequency of the clock signal input by the external circuit divided by the frequency division number of the prescaler and multiplied by the frequency division number of the loop frequency divider, and multiplied by the multiple of the frequency multiplication number of the frequency multiplication circuit, that is: the frequency of the clock signal output by the frequency synthesizer = (frequency of the clock signal input by the external circuit/frequency division number of the prescaler) × (frequency division number of the loop frequency divider) × (multiple times of the N-fold circuit).

Based on the above embodiments, the voltage-controlled oscillator in the phase-locked loop circuit in the phase-locked loop frequency synthesizer provided in a preferred embodiment of the present invention adopts a ring oscillator with a differential structure, the number of stages of a differential inverter of the ring oscillator is set to be N stages which is the same as the number of stages of the N frequency multiplier circuits, each stage adopts a dual-input dual-output structure, and the phase difference between two adjacent clock signals in 2N clock signals whose phases sequentially change and which are output by the ring oscillator with the differential structure is pi/N.

Preferably, the voltage-controlled oscillator may also be, but is not limited to, a ring oscillator adopting a differential structure, a ring oscillator adopting a non-differential structure, or the like. In the present invention, the voltage-controlled oscillator may be an oscillator capable of outputting 2N clock signals having the same frequency and sequentially changing phases.

As a preferred embodiment of the present invention, a voltage-controlled oscillator module of a phase-locked loop circuit in a frequency synthesizer is designed as a ring oscillator with a differential structure, and the number of stages of a differential inverter of the ring oscillator is set to be one of positive integer multiples of 2, such as 2, 4, 6, 8, 10, or 12, and the like, and the ring oscillator outputs a general clock signal in which phases of all output signals are sequentially and continuously changed, such as: 4. 8, 12, 16 or 24 clock signals, and the phase difference of two adjacent clock signals is pi/2, pi/4, pi/6, pi/8, pi/10 or pi/12, etc. Meanwhile, in the frequency synthesizer provided in this embodiment, the number of frequency multiplication stages of the N frequency multiplication circuit is set to a value equal to the number of stages of the differential inverters of the ring oscillator, and the number of clock signals output by the ring oscillator is twice as large as the number of stages of the differential inverters of the ring oscillator.

Based on the foregoing embodiments, a preferred embodiment of the present invention provides a pll frequency synthesizer, as shown in fig. 3, in which an N-multiplier circuit in the pll frequency synthesizer is composed of an N-stage xor gate, an N-stage and gate, and a one-stage or gate.

Specifically, each stage of the N stages of xor gates includes two input ends and an output end, the N stages of xor gates include 2N input ends, and the 2N input ends included in the N stages of xor gates are used as the 2N input ends of the N frequency doubling circuit, and are configured to sequentially receive the 2N clock signals output by the phase-locked loop circuit, where the phase of the clock signals sequentially changes.

Each stage of the N-stage and gate includes a first input terminal, a second input terminal, and an output terminal, the first input terminal of each stage of the and gate is correspondingly connected to the output terminal of the same stage of the xor gate to receive the clock signal output by the xor gate, understandably, the first input terminal of the first stage of the and gate is connected to the output terminal of the first stage of the xor gate to receive the clock signal output by the first stage of the xor gate after the xor operation, the first input terminal of the second stage of the and gate is connected to the output terminal of the second stage of the xor gate to receive the clock signal output by the second stage of the xor gate after the xor operation, and so on, the first input terminal of the N-th stage of the and gate is connected to the output terminal of the N-th stage of the xor gate to receive the clock signal output by the N-th stage of the xor gate after the xor operation.

The second input end of each stage of AND gates in the N stages of AND gates is connected with the appointed input end of the appointed stage of XOR gate, so that the phase of the clock signal input by the second input end of each stage of AND gates is lagged by 3pi/2 compared with the phase of the clock signal input by the first input end of the stage of AND gates, namely: the phase of the clock signal input by the appointed input end of the appointed first-stage exclusive-OR gate lags behind 3pi/2 compared with the phase of the clock signal input by the first input end of the appointed first-stage exclusive-OR gate, if the phase of the clock signal input by the first input end of the appointed first-stage exclusive-OR gate is pi/12, the second input end of the appointed first-stage exclusive-OR gate is connected with the second input end of the appointed first-stage exclusive-OR gate, so that the phase of the clock signal input by the second input end of the appointed first-stage exclusive-OR gate is 19pi/12, namely the phase of the clock signal input by the second input end of the appointed first-stage exclusive-OR gate lags behind 3pi/2 compared with the phase of the clock signal input by the first input end of the appointed first-stage exclusive-OR gate. It should be noted that the second input terminal of each stage of and gate has a designated input terminal of the xor gate in a one-to-one correspondence with the designated input terminal of the xor gate in the designated stage.

The first-stage OR gate comprises N input ends and an output end, wherein the N input ends of the first-stage OR gate are connected with the N output ends of the N-stage AND gate in a one-to-one correspondence mode, and the first-stage OR gate is used for receiving N clock signals output by the N-stage AND gate after AND operation, taking the output end of the first-stage OR gate as the output end of the N frequency doubling circuit and the output end of the phase-locked loop frequency synthesizer as well as the output end of the phase-locked loop frequency synthesizer and outputting a final clock signal of N frequency doubling as the clock signal output by the phase-locked loop frequency synthesizer.

For the current phase-locked loop circuit, when the frequency of the clock signal output by the voltage-controlled oscillator is 100MHz, the overall power consumption of the phase-locked loop circuit is only about 100 μ a to 200 μ a, but when the frequency of the clock signal output by the voltage-controlled oscillator reaches 1.6GHz, the overall power consumption of the phase-locked loop circuit can reach 1mA to 2 mA. The frequency synthesizer of the invention can realize that the whole power consumption of the phase-locked loop circuit is kept between 100 muA and 200 muA when the frequency of the clock signal output by the frequency synthesizer reaches N x 100MHz by combining the N frequency doubling circuit arranged outside the phase-locked loop circuit, and when the N of the N frequency doubling circuit is equal to 16, the power consumption of the N frequency doubling circuit is only less than 50 muA, thereby realizing that the frequency synthesizer outputs high-frequency clock signals with low power consumption, greatly reducing the whole power consumption of the frequency synthesizer.

Preferably, the N-multiplier circuit is disposed outside the loop of the phase-locked loop circuit, because if the N-multiplier circuit is disposed between the voltage-controlled oscillator and the loop divider of the phase-locked loop circuit, a larger division number needs to be configured for the loop divider of the phase-locked loop circuit, which increases the complexity of the loop divider, and if the frequency of the feedback clock signal to be divided is increased, the power consumption of the loop divider of the phase-locked loop circuit is correspondingly increased, which increases the overall power consumption of the phase-locked loop circuit, thereby affecting the purpose of the frequency synthesizer to output the high-frequency clock signal with low power consumption. Meanwhile, in the phase of starting the phase-locked loop circuit, 2N clock signals with sequentially changed phases output by the voltage-controlled oscillator are different, so that the clock signals output by the N frequency doubling circuit have large instability, and the output of the feedback clock signals of the loop frequency divider may be influenced, thereby causing the problem that the loop of the phase-locked loop circuit is difficult to start or lock, and influencing the overall working efficiency of the frequency synthesizer.

Obviously, the above-mentioned embodiments are only a part of embodiments of the present invention, not all embodiments, and the technical solutions of the embodiments may be combined with each other. In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. In the embodiments provided in the present invention, it should be understood that the disclosed technical contents can be implemented in other manners. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the circuit may be a logical division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or may be integrated into another system, or modules with different functions are integrated into the same module to implement multiple functions, or some features may be omitted, or not executed.

It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.