阅读说明：本技术 用于高带宽和高裸片计数存储器堆叠的印刷电路板补偿结构 (Printed circuit board compensation structure for high bandwidth and high die count memory stacks ) 是由 J·T·孔特拉斯 S·莫宾 D·奥赫 R·A·扎凯 于 2021-03-08 设计创作，主要内容包括：本发明公开了一种用于高带宽和高裸片计数存储器堆叠的电路互连件。所述电路互连件可包含第一接地迹线、第一信号迹线、第二接地迹线和第二信号迹线。所述第一接地迹线可驻留在多层印刷电路板的第一层中。所述第一信号迹线可在所述第一层内定位成邻近于所述第一接地迹线。所述第二接地迹线可驻留在所述多层印刷电路板的第二层内。所述第二信号迹线可在所述第二层内定位成邻近于所述第二接地迹线。(A circuit interconnect for high bandwidth and high die count memory stacks is disclosed. The circuit interconnect can include a first ground trace, a first signal trace, a second ground trace, and a second signal trace. The first ground trace may reside in a first layer of a multilayer printed circuit board. The first signal trace may be positioned adjacent to the first ground trace within the first layer. The second ground trace may reside within a second layer of the multilayer printed circuit board. The second signal trace may be positioned adjacent to the second ground trace within the second layer.)

1. A circuit interconnect, comprising:

a first ground trace within a first layer of the multilayer printed circuit board;

a first signal trace positioned adjacent to the first ground trace within the first layer;

a second ground trace within a second layer of the multilayer printed circuit board; and

a second signal trace within the second layer adjacent to the second ground trace.

2. The circuit interconnect of claim 1, further comprising:

a first source via within the multilayer printed circuit board connected to the first and second signal traces and to a first signal source; and

a first ground via within the multilayer printed circuit board connected to the first ground trace and the second ground trace and to a ground source.

3. The circuit interconnect of claim 2, further comprising:

a third ground trace connected to a second ground via and positioned within the second layer and adjacent to the second signal trace;

a third signal trace connected to a second source via and positioned within the first layer and adjacent to the first ground trace;

a fourth ground trace connected to a third ground via and positioned within the first layer and adjacent to the third signal trace; and

a fourth signal trace connected to the second source via and positioned within the second layer and adjacent to the third ground trace, the second source via connected to a second signal source.

4. The circuit interconnect of claim 2, further comprising a third signal trace connected to the first source via and bond pads for pins of a memory controller, and a third ground trace connected to one of the ground source and the first ground via.

5. The circuit interconnect of claim 2, wherein the first signal trace, the second signal trace, the first ground trace, and the second ground trace each comprise an angled connector; and wherein each angled connector is configured to route traces horizontally within a layer of the multilayer printed circuit board so as to connect the traces to vias.

6. The circuit interconnect of claim 2, wherein the first and second signal traces are connected to a T-branch connected with upper and lower bond pads, the upper bond pad configured to be connected to an upper die stack by way of a first wire bond, and the lower bond pad configured to be connected to a lower die stack by way of a second wire bond.

7. The circuit interconnect of claim 2, wherein a component of a first signal has a signal frequency wavelength within about ten times a physical length of a transmission path including the circuit interconnect, and the circuit interconnect has a characteristic impedance of about 20 ohms.

8. The circuit interconnect of claim 2, wherein the multi-layer printed circuit board comprises a ground plane layer connected to the first ground via and an insulating layer separating the first layer from the second layer.

9. A system, comprising:

a multilayer printed circuit board;

a signal compensation structure integrated with the multilayer printed circuit board, the signal compensation structure comprising a first signal trace coupled to a first signal source and two ground traces coupled to a ground source;

a memory controller coupled to the multi-layer printed circuit board and configured to read data from and write data to a set of memory dies;

a die stack coupled to the multilayer printed circuit board, the die stack including the set of memory dies, the memory dies connected to each other by wire bonds; and

a communication bus configured to connect the set of memory dies to the memory controller by way of the signal compensation structure.

10. The system of claim 9, wherein a first ground trace of the two ground traces is positioned within a first layer of the multilayer printed circuit board and the first signal trace is positioned adjacent to the first ground trace within the first layer and a second ground trace of the two ground traces is positioned within a second layer and directly above the first signal trace; and is

The signal compensation structure further includes a second signal trace positioned within the second layer and directly above the first ground trace.

11. The system of claim 10, wherein the signal compensation structure comprises:

a third signal trace positioned within the first layer and adjacent to the first ground trace;

a third ground trace positioned within the second layer and adjacent to the second signal trace, the third ground trace positioned directly above the third signal trace;

a fourth ground trace positioned within the first layer and adjacent to the third signal trace;

a fourth signal trace positioned within the second layer and adjacent to the third ground trace, the fourth signal trace positioned directly above the fourth ground trace; and is

Wherein the first and second signal traces are connected to the first signal source and the third and fourth signal traces are connected to a second signal source separate and distinct from the first signal source.

12. The system of claim 9, wherein a first ground trace of the two ground traces is positioned within a first layer of the multilayer printed circuit board and the first signal trace is positioned directly above the first ground trace in a second layer of the multilayer printed circuit board, the second layer being adjacent to the first layer; and is

Wherein the second ground trace of the two ground traces is positioned directly above the first signal trace within a third layer of the multilayer printed circuit board, the third layer being adjacent to the second layer.

13. The system of claim 9, wherein the first signal trace is positioned between the two ground traces within a first layer of the multilayer printed circuit board, and the signal compensation structure further comprises a first ground trace positioned directly above the first signal trace and within a second layer that is above the first layer and adjacent to the first layer, and the signal compensation structure comprises a second ground trace positioned directly below the first signal trace and within a third layer that is below the first layer and adjacent to the first layer.

14. The system of claim 9, wherein a first ground trace of the two ground traces is positioned within a first layer of the multilayer printed circuit board and the first signal trace is positioned directly above the first ground trace in a second layer of the multilayer printed circuit board, the second layer being adjacent to the first layer; and is

The signal compensation structure further comprises a second signal trace positioned directly above the first signal trace and within a third layer, the third layer being above and adjacent to the second layer;

wherein the second of the two ground traces is positioned directly above the second signal trace within a fourth layer of the multilayer printed circuit board adjacent to the third layer; and is

Wherein the first signal trace and the second signal trace are connected to a source via connected to a common signal source.

15. The system of claim 9, wherein the communication bus comprises a parallel bus comprising a set of transmission lines, each transmission line comprising a signal compensation structure.

16. A signal compensation structure, comprising:

a first ground trace coupled to a lower ground plane of a multi-layer printed circuit board by a first ground via, the multi-layer printed circuit board comprising a substrate, a first layer, a second layer, the lower ground plane, and an upper ground plane, the multi-layer printed circuit board further comprising an insulating layer between each of: the lower ground plane and the first layer, the first layer and the second layer, and the second layer and the upper ground plane;

a first signal trace within the first layer adjacent to the first ground trace and coupled to a signal source;

a second ground trace coupled to the upper ground plane by a second ground via;

a second signal trace within the second layer adjacent to the second ground trace and coupled to the signal source through a source via connected to the first signal trace; and is

Wherein the second layer is positioned above the first layer.

17. The signal compensation structure of claim 16, wherein the first and second signal traces are connected to a T-branch connected with upper and lower bond pads, the upper bond pad configured to be connected to an upper die stack by means of a first wire bond and the lower bond pad configured to be connected to a lower die stack by means of a second wire bond; and is

Wherein the upper die stack includes more than four memory dies and the lower die stack includes more than four memory dies.

18. The signal compensation structure of claim 16, wherein the signal compensation structure is part of a transmission path and the signal compensation structure is configured to connect to a third signal trace connected to the source via and a bond pad for a pin of a memory controller and a third ground trace connected to one of the upper ground plane, the lower ground plane, and one of the first ground via and the second ground via; and is

Wherein the third ground trace is positioned within the first layer of the multilayer printed circuit board and responsive to a component of the signal source having a signal frequency wavelength within about ten times a physical length of the transmission path, the third signal trace includes a characteristic impedance of about 50 ohms.

19. The signal compensation structure of claim 16 wherein, in response to a component of the signal source having a signal frequency wavelength within about ten times a physical length of the transmission path, the signal compensation structure comprises a characteristic impedance of less than 40 ohms.

20. The signal compensation structure of claim 19 wherein the signal compensation structure comprises a characteristic impedance of 20 ohms.