阅读说明：本技术 印刷电路板 (Printed circuit board ) 是由 郑注奂 李承恩 金容勳 于 2021-06-22 设计创作，主要内容包括：本公开提供一种印刷电路板,所述印刷电路板包括：第一布线结构,包括第一绝缘层和第一布线层；第二布线结构,设置在所述第一布线结构上,并且包括第二绝缘层和第二布线层；以及第三布线结构,设置在所述第二布线结构上,并且包括第三绝缘层和设置在所述第三绝缘层上的第三布线层。所述第二布线层中的至少一个第二布线层的至少一部分具有比所述第一布线层的间距和所述第三布线层的间距更精细的间距,其中,所述第一布线层中的一个第一布线层的至少一部分通过第一布线过孔连接到所述第三布线层的至少一部分,并且其中,所述第一布线过孔穿透所述第一绝缘层、所述第二绝缘层和所述第三绝缘层。(The present disclosure provides a printed circuit board, the printed circuit board including: a first wiring structure including a first insulating layer and a first wiring layer; a second wiring structure provided on the first wiring structure and including a second insulating layer and a second wiring layer; and a third wiring structure provided on the second wiring structure and including a third insulating layer and a third wiring layer provided on the third insulating layer. At least a portion of at least one of the second wiring layers has a finer pitch than a pitch of the first wiring layers and a pitch of the third wiring layers, wherein at least a portion of one of the first wiring layers is connected to at least a portion of the third wiring layers by a first wiring via, and wherein the first wiring via penetrates the first insulating layer, the second insulating layer, and the third insulating layer.)

1. A printed circuit board comprising:

a first wiring structure including a plurality of first insulating layers and a plurality of first wiring layers;

a second wiring structure provided on the first wiring structure and including a plurality of second insulating layers and a plurality of second wiring layers; and

a third wiring structure provided on the second wiring structure and including a third insulating layer and a third wiring layer provided on the third insulating layer,

wherein at least a portion of at least one of the plurality of second wiring layers has a finer pitch than a pitch of the plurality of first wiring layers and a pitch of the third wiring layer,

wherein at least a portion of one of the plurality of first wiring layers is connected to at least a portion of the third wiring layer through a first wiring via, and

wherein the first wire via penetrates at least one of the plurality of first insulating layers, the plurality of second insulating layers, and the third insulating layer.

2. The printed circuit board as set forth in claim 1,

wherein at least a portion of one of the plurality of second wiring layers is connected to at least a portion of the third wiring layer through a second wiring via, and

wherein the second wire via penetrates the third insulating layer and at least one of the plurality of second insulating layers.

3. Printed circuit board according to claim 1 or 2,

wherein at least a portion of another one of the plurality of second wiring layers is connected to at least a portion of the third wiring layer through a third wiring via, and

wherein the third wire via penetrates the third insulating layer.

4. The printed circuit board as set forth in claim 3,

wherein at least a portion of one of the plurality of second wiring layers is connected to at least a portion of another one of the plurality of second wiring layers through a fourth wiring via,

wherein the fourth wiring via penetrates at least one of the plurality of second insulating layers, and

wherein a side surface of the third wire via and a side surface of the fourth wire via taper in opposite directions.

5. The printed circuit board as set forth in claim 1,

wherein a thickness of the first wiring structure is larger than a thickness of the second wiring structure, and

wherein a thickness of the second wiring structure is greater than a thickness of the third wiring structure.

6. The printed circuit board as set forth in claim 5,

wherein the first wiring structure has a core substrate structure, and

wherein the second wiring structure has a coreless substrate structure.

7. A printed circuit board comprising:

a first wiring structure including a plurality of first insulating layers and a plurality of first wiring layers;

a second wiring structure disposed over the first wiring structure and including one or more second insulating layers and one or more second wiring layers; and

a third wiring structure disposed over the second wiring structure and including a third insulating layer and a third wiring layer disposed on the third insulating layer,

wherein an uppermost second wiring layer of the one or more second wiring layers is buried in an uppermost second insulating layer of the one or more second insulating layers,

wherein an upper surface of the uppermost second wiring layer is in contact with the third insulating layer, and

wherein the number of conductive patterns included in the uppermost second wiring layer is greater than the number of conductive patterns included in the third wiring layer.

8. The printed circuit board as set forth in claim 7,

wherein the second wiring structure includes a plurality of second insulating layers and a plurality of second wiring layers, and

wherein the number of conductive patterns included in the uppermost second wiring layer is greater than the number of conductive patterns included in another second wiring layer among the plurality of second wiring layers.

9. The printed circuit board of claim 7, wherein the uppermost second routing layer comprises a single conductive layer.

10. The printed circuit board of any of claims 7-9, wherein there is a step between an upper surface of the uppermost second wiring layer and an upper surface of the uppermost second insulating layer.

11. The printed circuit board of claim 10, wherein the step provides a recessed area that is above the uppermost second insulating layer, at least a portion of the recessed area being filled with the third insulating layer.

12. The printed circuit board of any of claims 7-9, wherein an uppermost first insulating layer of the plurality of first insulating layers is in contact with a lowermost second insulating layer of the one or more second insulating layers.

13. The printed circuit board of claim 12, wherein a boundary between the uppermost first insulating layer and the lowermost second insulating layer is spaced apart from each routing layer.

14. The printed circuit board of any of claims 7-9, further comprising:

a first passivation layer disposed under the first wiring structure and covering at least a portion of a lowermost first wiring layer of the plurality of first wiring layers; and

a second passivation layer disposed over the third wiring structure and covering at least a portion of the third wiring layer.

15. The printed circuit board of claim 14, further comprising:

a plurality of electronic components disposed on the second passivation layer,

wherein each of the plurality of electronic components is connected to at least a portion of the third wiring layer, and the plurality of electronic components are connected to each other through the plurality of second wiring layers.

16. The printed circuit board of claim 15, wherein the plurality of electronic components comprise logic chips and/or memory chips.

17. A printed circuit board comprising:

a core layer;

a plurality of upper insulating layers disposed on an upper side of the core layer;

a plurality of upper wiring layers respectively provided on and/or in the plurality of upper insulating layers;

a plurality of lower insulating layers disposed on a lower side of the core layer opposite to the upper side; and

a plurality of lower wiring layers respectively disposed on or in the plurality of lower insulating layers,

wherein a portion of one of the plurality of upper wiring layers has a finer pitch than the pitches of the other of the plurality of upper wiring layers and has a finer pitch than the pitches of the plurality of lower wiring layers, and

wherein the portion of the plurality of upper wiring layers having the fine pitch and another one of the plurality of upper wiring layers are respectively located on opposite sides of one of the plurality of upper insulating layers.

18. The printed circuit board as set forth in claim 17,

wherein the portion of the plurality of upper wiring layers having the fine pitch is disposed between the core layer and the one of the plurality of upper insulating layers.

19. The printed circuit board as set forth in claim 17,

wherein the number of the upper wiring layers is greater than the number of the lower wiring layers.

20. The printed circuit board as claimed in any one of claims 17-19, further comprising:

two or more vias extending from the other one of the plurality of upper wiring layers to be connected to two of the plurality of upper wiring layers, respectively,

wherein the two or more vias penetrate different numbers of the plurality of upper insulating layers.

21. A printed circuit board comprising:

a first wiring structure including a first insulating layer and a first wiring layer;

a second wiring structure disposed over the first wiring structure and including a second insulating layer and a second wiring layer; and

a third wiring structure disposed over the second wiring structure and including a third insulating layer and a third wiring layer,

wherein a routing pitch of at least a portion of an uppermost one of the second routing layers is smaller than routing pitches of other ones of the second routing layers.

22. The printed circuit board of claim 21, wherein the at least a portion of the uppermost second wiring layer is embedded in an uppermost second insulating layer of the second insulating layers, a portion of a lowermost third insulating layer of the third insulating layers is embedded in the uppermost second insulating layer, and contacts the at least a portion of the uppermost second wiring layer.

Technical Field

The present disclosure relates to a printed circuit board, and more particularly, to a printed circuit board for mounting a package board of an electronic component.

Background

The mediator market has been growing due to the high size of the devices (sets) and the use of High Bandwidth Memory (HBM). In most cases, silicon has been used as the material of the interposer. For example, in the case of a semiconductor package using an interposer, the die may be surface mounted on a silicon interposer and molded with a molding material.

Since the interposer has also been designed to have high performance due to the increase in the number of HBMs for high-specification equipment, process difficulty may increase and a problem of yield reduction has occurred.

Disclosure of Invention

An aspect of the present disclosure is to provide a printed circuit board that can easily implement a microcircuit pattern.

Another aspect of the present disclosure is to provide a printed circuit board that can ensure sufficient adhesion between a microcircuit pattern and an insulating material.

Another aspect of the present disclosure is to provide a printed circuit board that can replace a silicon interposer.

According to an aspect of the present disclosure, a printed circuit board includes a microcircuit pattern, which can be provided by: a microcircuit board manufactured by a separate microcircuit process is attached to one side of the multilayer wiring substrate.

For example, according to an aspect of the present disclosure, a printed circuit board may include: a first wiring structure including a plurality of first insulating layers and a plurality of first wiring layers; a second wiring structure provided on the first wiring structure and including a plurality of second insulating layers and a plurality of second wiring layers; and a third wiring structure provided on the second wiring structure and including a third insulating layer and a third wiring layer provided on the third insulating layer. At least a portion of at least one of the plurality of second wiring layers may have a finer pitch than a pitch of the plurality of first wiring layers and a pitch of the third wiring layer. At least a portion of one of the plurality of first routing layers may be connected to at least a portion of the third routing layer by a first routing via. The first wire via may penetrate the plurality of second insulating layers, the third insulating layers, and at least one of the plurality of first insulating layers.

For example, according to an aspect of the present disclosure, a printed circuit board may include: a first wiring structure including a plurality of first insulating layers and a plurality of first wiring layers; a second wiring structure disposed over the first wiring structure and including one or more second insulating layers and one or more second wiring layers; and a third wiring structure disposed over the second wiring structure and including a third insulating layer and a third wiring layer disposed on the third insulating layer. An uppermost second wiring layer of the one or more second wiring layers may be buried in an uppermost second insulating layer of the one or more second insulating layers. An upper surface of the uppermost second wiring layer may be in contact with the third insulating layer. The number of conductive patterns included in the uppermost second wiring layer may be greater than the number of conductive patterns included in the third wiring layer.

For example, according to an aspect of the present disclosure, a printed circuit board may include: a core layer; a plurality of upper insulating layers disposed on an upper side of the core layer; a plurality of upper wiring layers respectively provided on or in the plurality of upper insulating layers; a plurality of lower insulating layers disposed on a lower side of the core layer opposite to the upper side; and a plurality of lower wiring layers respectively disposed on or in the plurality of lower insulating layers. A portion of one of the plurality of upper wiring layers may have a finer pitch than the pitches of the other of the plurality of upper wiring layers, and may have a finer pitch than the pitches of the plurality of lower wiring layers. The portion of the plurality of upper wiring layers having the fine pitch and another one of the plurality of upper wiring layers may be respectively located at opposite sides of one of the plurality of upper insulating layers.

For example, according to another aspect of the present disclosure, a printed circuit board may include: a first wiring structure including a first insulating layer and a first wiring layer; a second wiring structure disposed over the first wiring structure and including a second insulating layer and a second wiring layer; and a third wiring structure disposed above the second wiring structure and including a third insulating layer and a third wiring layer, wherein a wiring pitch of at least a part of an uppermost second wiring layer among the second wiring layers is smaller than wiring pitches of other second wiring layers among the second wiring layers.

Drawings

The above and other aspects, features and advantages of the present disclosure will be more clearly understood by reference to the following detailed description when taken in conjunction with the accompanying drawings, in which:

fig. 1 is a block diagram illustrating an example of an electronic device system;

fig. 2 is a perspective view showing an example of an electronic apparatus;

fig. 3 is a sectional view showing an example of a printed circuit board;

fig. 4 to 6 are sectional views illustrating a process for manufacturing the printed circuit board shown in fig. 3; and

fig. 7 is a sectional view showing another example of the printed circuit board.

Detailed Description

Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. In the drawings, the shape, size, and the like of elements may be exaggerated or schematically illustrated for clarity of description.

Fig. 1 is a block diagram illustrating an example of an electronic device system.

Referring to fig. 1, an electronic device 1000 may house a motherboard 1010 therein. Chip-related components 1020, network-related components 1030, other components 1040, etc. may be physically and/or electrically connected to motherboard 1010. These components may be connected to other components described below by various signal lines 1090.

The chip related component 1020 may include: a memory chip such as a volatile memory (e.g., a Dynamic Random Access Memory (DRAM)), a nonvolatile memory (e.g., a Read Only Memory (ROM)), a flash memory, or the like; an application processor chip such as a central processing unit (e.g., Central Processing Unit (CPU)), a graphics processor (e.g., Graphics Processing Unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and logic chips such as analog-to-digital converters (ADCs), Application Specific Integrated Circuits (ASICs), and the like. However, the chip-related component 1020 is not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip related assembly 1020 may have a package form including the chip described above.

Network-related components 1030 may include components compatible with or operating using protocols such as: wireless fidelity (Wi-Fi) (institute of electrical and electronics engineers (IEEE)802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), evolution data only (Ev-DO), high speed packet access + (HSPA +), high speed downlink packet access + (HSDPA +), high speed uplink packet access + (HSUPA +), Enhanced Data GSM Environment (EDGE), global system for mobile communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless and wired protocols specified after the above protocols. However, network-related component 1030 is not so limited, but may also include components that are compatible with or operate using various other wireless or wired standards or protocols. In addition, the network-related component 1030 and the above-described chip-related component 1020 may be combined with each other.

Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), and so forth. However, the other components 1040 are not limited thereto, and may also include passive components and the like for various other purposes. In addition, other components 1040 may be combined with one another with the chip-related components 1020 and/or the network-related components 1030 described above.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that are physically or electrically connected to the motherboard 1010 or that are not physically or electrically connected to the motherboard 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard drive), a Compact Disc (CD) drive, a Digital Versatile Disc (DVD) drive, and so forth. However, these other components are not limited thereto, but may also include other components for various purposes according to the type of the electronic device 1000 and the like.

The electronic device 1000 may be a smart phone, a Personal Digital Assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game, a smart watch, an automotive component, and so forth. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.

Fig. 2 is a perspective view showing an example of the electronic apparatus.

Referring to fig. 2, the electronic device may be implemented by a smart phone 1100. Motherboard 1110 may be housed in smartphone 1100, and various electronic components 1120 may be physically or electrically connected to motherboard 1110. The camera module 1130 and/or the speaker 1140 may be housed in the smartphone 1100. Some of the electronic components 1120 may be chip-related components such as the component packages 1121, but exemplary embodiments thereof are not limited thereto. In the component package 1121, a plurality of electronic components may be disposed in a surface-mounted form on a multi-layered printed circuit board, but exemplary embodiments thereof are not limited thereto. The electronic device need not be limited to the smartphone 1100, but may be other electronic devices as described above.

Fig. 3 is a sectional view showing an example of the printed circuit board.

Referring to fig. 3, the printed circuit board 500A in the exemplary embodiment may include a first wiring structure 100, a second wiring structure 200, and a third wiring structure 300, the first wiring structure 100 including a plurality of first insulating layers 111, 112, 113, and 114 and a plurality of first wiring layers 121, 122, and 123, the second wiring structure 200 including a plurality of second insulating layers 211 and 212 and a plurality of second wiring layers 221 and 222, and the third wiring structure 300 including a third insulating layer 311 and a third wiring layer 321. The first, second and third wiring structures 100, 200 and 300 may be sequentially stacked. If necessary, the first passivation layer 410 and the second passivation layer 420 may be disposed above and below the stacked body including the first, second and third wiring structures 100, 200 and 300, respectively.

As described above, recently, due to the high specification of the equipment, the number of HBMs has increased compared to before, and thus the silicon interposer has also been constructed to have high performance, and thus, the process difficulty may increase and the yield may decrease, and the price may also increase. In order to solve the above problems, as a method of replacing a silicon interposer, it may be considered to form a microcircuit in a Flip Chip Ball Grid Array (FCBGA) substrate and use the substrate as a package substrate. However, microcircuit technology in FCBGA substrates should use semi-additive process (SAP) methods. In this case, when the seed layer under the pattern is etched, undercut (undercut) may occur, and the undercut may reduce the adhesive force between the pattern and the insulating material. Therefore, there may be a limitation in forming a microcircuit pattern having a desired level of fine pitch.

The printed circuit board 500A in the exemplary embodiment may be a micro circuit board including a micro circuit pattern, in which the second wiring structure 200 may be separately manufactured using an Embedded Trace Substrate (ETS) method in a process described below, and may be inversely attached to the first wiring structure 100. For example, the uppermost second wiring layer 221 of the plurality of second wiring layers 221 and 222 may include a microcircuit pattern (or referred to as a conductive pattern) having a relatively finer pitch than the pitch of the plurality of first wiring layers 121, 122, and 123 and the third wiring layer 321. The configuration including the relatively fine pitch may mean that the intervals between the wiring patterns included in the respective wiring layers may be relatively finer than the intervals between the wiring patterns included in the wiring layers to be compared, so that the wiring density may be relatively higher. For example, the number of conductive patterns in the uppermost second wiring layer 221 may be greater than the number of conductive patterns in the second wiring layer 222, and may be greater than the number of conductive patterns in the third wiring layer 321. Thus, the plate can replace a silicon interposer. Further, since the above-described undercut problem does not occur when forming the microcircuit pattern, the microcircuit pattern having a desired level of fine pitch can be formed without the problem of reduced adhesion.

Accordingly, the uppermost second wiring layer 221 of the plurality of second wiring layers 221 and 222 may be buried in the uppermost second insulating layer 211 of the plurality of second insulating layers 211 and 212, so that the upper surface of the uppermost second wiring layer 221 may be in contact with the third insulating layer 311. Further, the number of the conductive layers P1 included in the uppermost second wiring layer 221 may be greater than the number of the conductive layers S2 and P2 included in another second wiring layer (or referred to as a lowermost second wiring layer) 222 among the plurality of second wiring layers 221 and 222 and the number of the conductive layers S3 and P3 included in the third wiring layer 321. For example, the uppermost second wiring layer 221 may include the single conductive layer P1 without including a seed layer. Further, the upper surface of the uppermost second wiring layer 221 and the upper surface of the uppermost second insulating layer 211 may have a height difference (step) therebetween. Due to the step, the recessed area r may be disposed at an upper portion of the uppermost second insulating layer 211, and at least a portion of the recessed area r may be filled with the third insulating layer 311.

Further, accordingly, at least a portion of the uppermost first wiring layer 123 and at least a portion of the third wiring layer 321 in the plurality of first wiring layers 121, 122, and 123 may be connected to each other by the first wiring via V1 that penetrates entirely through at least a portion of the uppermost first insulating layer 114 in the plurality of first insulating layers 111, 112, 113, and 114, the plurality of second insulating layers 211 and 212, and the third insulating layer 311. Further, at least a portion of the lowermost second wiring layer 222 and at least a portion of the third wiring layer 321 of the plurality of second wiring layers 221 and 222 may be connected to each other through a second wiring via V2 penetrating entirely through the uppermost second insulating layer 211 and the third insulating layer 311 of the plurality of second insulating layers 211 and 212. Accordingly, upward and downward electrical connection paths may be provided through the wiring vias V1 and V2 penetrating the plurality of insulating layers.

Further, accordingly, at least a part of the uppermost second wiring layer 221 and at least a part of the third wiring layer 321 in the plurality of second wiring layers 221 and 222 may be connected to each other through the third wiring via V3 penetrating the third insulating layer 311. Further, at least a portion of the plurality of second wiring layers 221 and at least a portion of the plurality of second wiring layers 222 may be connected to each other through a fourth wiring via V4 penetrating an uppermost second insulating layer 211 of the plurality of second insulating layers 211 and 212. In this case, the side surface of the third wire via V3 and the side surface of the fourth wire via V4 may be tapered in opposite directions. Accordingly, the second wiring structure 200 may be disposed upside down, so that the second wiring layer 221, which is a buried pattern having a fine pitch, may be disposed on the first wiring structure 100, and thus, the fourth wiring via V4 formed in the second wiring structure 200 may have a tapered shape tapered in a direction opposite to the direction in which the third wiring via V3 is tapered, and the third wiring via V3 may be formed after the second wiring structure 200 is disposed, that is, for example, the fourth wiring via V4 may have a tapered shape tapered in a direction opposite to the direction in which the first, second, and third wiring vias V1, V2, and V3 are tapered.

In the following description, each element included in the printed circuit board 500A according to an example will be described in more detail with reference to the drawings.

The first wiring structure 100 may include a plurality of first insulating layers 111, 112, 113, and 114 and a plurality of first wiring layers 121, 122, and 123. The first wiring structure 100 may have a core substrate structure. Accordingly, the thickness of the first wiring structure 100 may be greater than the thickness of each of the second and third wiring structures 200 and 300. For example, the first wiring structure 100 may include: a core layer 111; a plurality of first stacked insulating layers 112 disposed under the core layer 111; and a plurality of second insulation buildup layers 113 and 114 disposed over the core layer 111, the plurality of first insulation layers 111, 112, 113, and 114 each having a relatively large thickness. The number of layers of the plurality of first stacked insulating layers 112 may be the same as the number of layers of the plurality of second stacked insulating layers 113 and 114, and thus, the first wiring structure 100 may have a symmetrical structure. Further, the first wiring structure 100 may include a core wiring layer 121 disposed on both surfaces of the core layer 111, a plurality of first build-up wiring layers 122 disposed on the plurality of first build-up insulating layers 112 and/or in the plurality of first build-up insulating layers 112, and a plurality of second build-up wiring layers 123 disposed on the plurality of second build-up insulating layers 113 and 114 and/or in the plurality of second build-up insulating layers 113 and 114. The number of layers of the plurality of first stacked insulating layers 112 and the plurality of second stacked insulating layers 113 and 114 and the number of layers of the plurality of first stacked wiring layers 122 and the plurality of second stacked wiring layers 123 are not limited to any particular example, and may be larger or smaller than the example shown in the drawings.

An insulating material may be used as the material of the core layer 111 and the plurality of first stacked insulating layers 112 and the plurality of second stacked insulating layers 113 and 114, and a thermosetting resin (such as an epoxy resin) or a thermoplastic resin (such as polyimide), or a resin including an inorganic filler (such as silica) and/or a reinforcing material such as glass fiber may be used as the insulating material. For example, an insulating material of a Copper Clad Laminate (CCL) may be used as the material of the core layer 111. In addition, a prepreg may be used as a material of the plurality of first stacked insulating layers 112 and the plurality of second stacked insulating layers 113 and 114. An uppermost second stacked insulating layer 114 of the plurality of second stacked insulating layers 113 and 114 (i.e., an uppermost first insulating layer 114 of the plurality of first insulating layers 111, 112, 113, and 114) may be in contact with a lowermost second insulating layer 212 of the plurality of second insulating layers 211 and 212. In order to secure the adhesive force, an ajinomoto stacked film (ABF) may be used as a material for the uppermost second stacked insulating layer 114 of the plurality of second stacked insulating layers 113 and 114. Further, the wiring layer may not be provided on the boundary between the uppermost second stacked insulating layer 114 (i.e., the uppermost first insulating layer 114) and the lowermost second insulating layer 212.

A metal material may be used as a material for the core wiring layer 121 and the plurality of first and second build-up wiring layers 122 and 123, and copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used as the metal material. Each of the core wiring layer 121 and the plurality of first and second stacked wiring layers 122 and 123 may perform various functions according to design. For example, the core wiring layer 121 and the plurality of first and second buildup wiring layers 122 and 123 may include a ground pattern, a power pattern, a signal pattern, and the like. Here, the signal pattern may include various signal patterns, such as a data signal pattern, in addition to a ground pattern and a power pattern. Each of these patterns may have a line shape, a face shape, or a pad shape. The core wiring layer 121 and the plurality of first and second buildup wiring layers 122 and 123 may be formed by a plating process such as an Addition Process (AP), a half AP (sap) process, a modified sap (msap) process, a sealing (TT) process, etc., and thus may include a seed layer (electroless plating layer) and an electrolytic plating layer formed based on the seed layer. The particular layer may also include copper foil.

The second wiring structure 200 may include a plurality of second insulating layers 211 and 212 and a plurality of second wiring layers 221 and 222. The second wiring structure 200 may have a coreless substrate structure. Accordingly, the thickness of the second wiring structure 200 may be less than that of the first wiring structure 100 and greater than that of the third wiring structure 300. For example, the second wiring structure 200 may be a build-up layer in which the plurality of second insulating layers 211 and 212 may have substantially the same thickness. Further, the second wiring structure 200 may be a buried pattern having a fine pitch in which the uppermost second wiring layer 221 of the plurality of second wiring layers 221 and 222 may be buried in the uppermost second insulating layer 211 of the plurality of second insulating layers 211 and 212, and may be in contact with the third insulating layer 311. The number of layers of the plurality of second insulating layers 211 and 212 and the number of layers of the plurality of second wiring layers 221 and 222 may not be limited to any particular number and may be larger than the example in the drawing, and each may have only a single layer.

An insulating material may be used as a material of the plurality of second insulating layers 211 and 212, and a thermosetting resin (such as an epoxy resin) or a thermoplastic resin (such as polyimide), or a resin including an inorganic filler (such as silicon oxide) and/or a reinforcing material (such as glass fiber) may be used as the insulating material. For example, a prepreg, ABF, or the like may be used as a material for the plurality of second insulating layers 211 and 212. As described above, the printed circuit board 500A in the exemplary embodiment may have the following advantages: the microcircuit pattern can be formed without using new materials such as photosensitive dielectric (PID), photosensitive material.

A metal material may be used as a material of the plurality of second wiring layers 221 and 222, and copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used as the metal material. Each of the plurality of second wiring layers 221 and 222 may perform various functions according to design. For example, the plurality of second wiring layers 221 and 222 may include a ground pattern, a power pattern, a signal pattern, and the like. Each of these patterns may have a line shape, a face shape, or a pad shape. The uppermost second wiring layer 221 may be formed through a plating process according to the ETS method as described above, and thus may include only the single conductive layer P1 without including a seed layer as described above. The other second wiring layer 222 may be formed by a plating process such as AP, SAP, MSAP, or TT, and thus may include a seed layer S2 (electroless plating layer) and a metal layer P2 (electrolytic plating layer formed based on the seed layer S2). In other words, the other second wiring layer 222 may include a plurality of conductive layers S2 and P2 (including the seed layer S2). The second wiring layer 222 may further include a primer copper foil (primer copper foil), if necessary.

The third wiring structure 300 may include a third insulating layer 311 and a third wiring layer 321. The third wiring structure 300 may be formed to provide an outermost layer for mounting electronic components on the upper side of the printed circuit board 500A after attaching the second wiring structure 200 to the first wiring structure 100. In the third wiring structure 300, each of the third insulating layer 311 and the third wiring layer 321 may include a plurality of layers, if necessary.

As the material of the third insulating layer 311, a thermosetting resin (such as an epoxy resin) or a thermoplastic resin (such as polyimide) or a resin including an inorganic filler (such as silica) and/or a reinforcing material (such as glass fiber) can be used. For example, a prepreg, ABF, or the like may be used as the material of the third insulating layer 311.

As a material of the third wiring layer 321, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. The third wiring layer 321 may also perform various functions according to design. For example, the third wiring layer 321 may include a ground pattern, a power pattern, a signal pattern, and the like. Each of these patterns may have a line shape, a face shape, or a pad shape. The third wiring layer 321 may be formed by a plating process such as AP, SAP, MSAP, or TT, and thus may include a seed layer S3 (electroless plating layer) and a metal layer P3 (electrolytic plating layer formed based on the seed layer S3). In other words, the third wiring layer 321 may include a plurality of conductive layers S3 and P3 (including the seed layer S3). The third wiring layer 321 may further include a primer copper foil, if necessary.

First routing via V1 may connect at least a portion of uppermost first routing layer 123 to at least a portion of third routing layer 321. The first wire via hole V1 may entirely penetrate the uppermost first insulating layer 114, the plurality of second insulating layers 211 and 212, and the third insulating layer 311. As a material of the first wire via V1, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. The number of the first routing vias V1 may be two or more according to design, and may include signal connection vias, ground connection vias, power connection vias, and the like. The first wiring via V1 may be a filled via in which the via hole is completely filled with a metal material, or may be a conformal via in which a metal material may be formed along a wall surface of the via hole. The first wiring via V1 may have a tapered shape in which the width of the upper surface is wider than the width of the lower surface. For example, the first wiring via V1 may be formed by a plating process (such as AP, SAP, MSAP, or TT), and thus may include a seed layer (electroless plating layer) and an electrolytic plating layer formed based on the seed layer. The first routing via V1 may also include a primed copper foil, if desired.

Second routing via V2 may connect at least a portion of lowermost second routing layer 222 to third routing layer 321. The second wiring via V2 may entirely penetrate the second insulating layer 211 and the third insulating layer 311 disposed on the uppermost side. As a material for the second wire via V2, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. The number of the second routing vias V2 may be two or more according to design, and may include signal connection vias, ground connection vias, power connection vias, and the like. The second wiring via V2 may be a filled via in which the via hole is completely filled with a metal material, or may be a conformal via in which a metal material may be formed along a wall surface of the via hole. The second wiring via V2 may have a tapered shape in which the width of the upper surface is wider than the width of the lower surface. For example, the second wiring via V2 may be formed by a plating process (such as AP, SAP, MSAP, or TT), and thus may include a seed layer (electroless plating layer) and an electrolytic plating layer formed based on the seed layer. The second routing via V2 may also include a primed copper foil, if desired.

Third wire via V3 may connect at least a portion of uppermost second wire layer 221 to third wire layer 321. The third wiring via V3 may penetrate the third insulating layer 311. As a material for the third wire via V3, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. The number of the third routing vias V3 may be two or more according to design, and may include signal connection vias, ground connection vias, power connection vias, and the like. The third wiring via V3 may be a filled via in which the via hole is completely filled with a metal material, or may be a conformal via in which a metal material may be formed along a wall surface of the via hole. The third wiring via V3 may have a tapered shape in which the width of the upper surface is wider than the width of the lower surface. For example, the third wiring via V3 may be formed by a plating process (such as AP, SAP, MSAP, TT), and thus may include a seed layer (electroless plating layer) and a plating layer formed based on the seed layer. The third wire via V3 may also include a primer copper foil, if desired.

The fourth wiring via V4 may connect at least a part of the plurality of second wiring layers 221 and at least a part of the plurality of second wiring layers 222 disposed on different layers to each other. The fourth wiring via V4 may penetrate the uppermost second insulating layer 211. As a material for the fourth wire via V4, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. The number of the fourth routing vias V4 may be two or more according to design, and may include signal connection vias, ground connection vias, power connection vias, and the like. The fourth wiring via V4 may be a filled via in which the via hole is completely filled with a metal material, or may be a conformal via in which a metal material may be formed along a wall surface of the via hole. The fourth wiring via V4 may have a tapered shape in which the width of the lower surface is wider than the width of the upper surface. For example, the fourth wiring via V4 may be formed by a plating process (such as AP, SAP, MSAP, TT), and thus may include a seed layer (electroless plating layer) and an electrolytic plating layer formed based on the seed layer. The fourth routing via V4 may also include a primed copper foil, if desired.

The fifth wire via V5 may penetrate the core layer 111 and may connect at least a portion of the plurality of core wire layers 121 disposed on different layers to each other. The fifth wire via V5 may have a relatively large height and may have a Plated Through Hole (PTH) shape. Accordingly, the fifth routing via V5 may include a plating layer V5a plated on the wall surface of the through-hole and a filler V5b filling the space between the plating layers V5 a. The plating layer V5a may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, and the filler V5b may include a capping ink. A plurality of fifth routing vias V5 may be provided according to design, and may include signal connection vias, ground connection vias, power connection vias, and the like. The plating layer V5a may be formed by a plating process (such as AP, SAP, MSAP, TT, etc.), and thus may include a seed layer (electroless plating layer) and an electrolytic plating layer formed based on the seed layer. The fifth routing via V5 may also include a primed copper foil, if desired.

The sixth wiring via V6 may penetrate at least a portion of each of the plurality of first buildup insulation layers 112 and may connect at least a portion of the plurality of first buildup wiring layers 122 disposed on different layers to each other. The sixth wiring via V6 may also connect at least a portion of the core wiring layer 121 disposed at the lower side of the core layer 111 to at least a portion of the uppermost first buildup wiring layer 122. The sixth wiring via V6 may be disposed in multiple layers in the plurality of first stacked insulating layers 112. Further, a plurality of sixth wiring vias V6 may be provided in each layer. As a material for the sixth routing via V6, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. The sixth routing via V6 may include a signal connection via, a ground connection via, and a power connection via, depending on the design. The sixth wiring via V6 may be a filled via in which the via hole is completely filled with a metal material, or may be a conformal via in which a metal material may be formed along a wall surface of the via hole. The sixth routing via V6 may have a tapered shape in which the width of the lower surface is wider than the width of the upper surface. For example, the sixth wiring via V6 may be formed through a plating process (AP, SAP, MSAP, or TT), and thus may include a seed layer (electroless plating layer) and an electrolytic plating layer formed based on the seed layer. The sixth routing via V6 may also include a primed copper foil, if desired.

The seventh wiring via V7 may penetrate a portion of each of the plurality of second stacked insulating layers 113 and 114 and may connect at least a portion of the plurality of second stacked wiring layers 123 disposed on different layers to each other. Further, the seventh wiring via V7 may connect at least a portion of the core wiring layer 121 disposed on the upper side of the core layer 111 to at least a portion of the lowermost second build-up wiring layer 123. The seventh routing via V7 may be disposed in a plurality of layers among the plurality of second stacked insulating layers 113 and 114. Further, a plurality of seventh wiring vias V7 may be provided in each layer. As a material of the seventh routing via V7, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof may be used. The seventh routing via V7 may include a signal connection via, a ground connection via, and a power connection via, depending on the design. The seventh routing via V7 may be a filled via in which the via hole is completely filled with the metal material, or may be a conformal via in which the metal material may be formed along a wall surface of the via hole. The seventh routing via V7 may have a tapered shape in which the width of the upper surface is wider than the width of the lower surface. For example, the seventh routing via V7 may be formed through a plating process (AP, SAP, MSAP, or TT), and thus may include a seed layer (electroless plating layer) and a plating layer formed based on the seed layer. The seventh routing via V7 may also include a primed copper foil, if desired.

The first passivation layer 410 may be disposed under the first wiring structure 100 and may cover at least a portion of the lowermost first wiring layer 122. The second passivation layer 420 may be disposed over the third wiring structure 300 and may cover at least a portion of the third wiring layer 321. Thus, the element can be protected from external physical and chemical damage. An insulating material may be used as the material of the first and second passivation layers 410 and 420, and a thermosetting resin (such as an epoxy resin) or a thermoplastic resin (such as polyimide) or a resin formed by mixing the above-described resin with an inorganic filler (such as ABF) may be used as the insulating material, but exemplary embodiments thereof are not limited thereto. A Solder Resist (SR) including a photosensitive material may be used. The first and second passivation layers 410 and 420 may have openings for exposing at least a portion of each of the lowermost first and third wiring layers 122 and 321, if necessary.

Fig. 4 to 6 are sectional views illustrating a process for manufacturing the printed circuit board shown in fig. 3.

Referring to fig. 4, a Copper Clad Laminate (CCL) or the like, which may be used as the core layer 111, may be prepared. Further, a through hole may be processed in the core layer 111 using a mechanical drill or the like, and the through hole may be filled by a plugging process, thereby forming the fifth wiring via V5. In addition, the core wiring layer 121 may be formed on both surfaces of the core layer 111 through a plating process. Thereafter, a plurality of first stacked insulating layers 112 and a plurality of second stacked insulating layers 113 and 114 may be stacked on both sides of the core layer 111. In the process of stacking each layer, via holes may be formed by laser processing or the like, and the via holes may be filled with a plating process to form the sixth wiring via V6 and the seventh wiring via V7, and the plurality of first build-up wiring layers 122 and the plurality of second build-up wiring layers 123 may be formed by the plating process. Through this process, the first wiring structure 100 in which the fifth, sixth, and seventh wiring vias V5, V6, and V7 are formed may be prepared.

Referring to fig. 5, a carrier 700 may be prepared, and a plurality of metal foils M1 and M2 may be formed on both sides of the carrier 700. Thereafter, the second wiring layer 221 (buried pattern) on the lower side may be formed by a plating process using the outermost metal foil M2 as a seed layer, and may be covered by the second insulating layer 211. Thereafter, a via hole may be formed by laser processing or the like, and the via hole may be filled by a plating process to form the fourth wiring via V4, and the second wiring layer 222 located on the upper side may be formed by the plating process, and the second wiring layer 222 may be covered by the second insulating layer 212. Therefore, since a seed layer for the second wiring layer 221 (buried pattern) located on the lower side may not need to be separately formed, problems caused by undercut or the like may be prevented. Thereafter, the stacked body manufactured from the carrier 700 may be separated by a method of separating the plurality of metal foils M1 and M2. Since the peeling layer may be provided between the plurality of metal foils M1 and M2, separation may be facilitated. Thereafter, the metal foil M2 remaining in the stack may be removed by etching or the like. Therefore, even in the final structure, the second wiring layer 221 (buried pattern) located on the lower side may not have a seed layer. In this process, the above-described recessed region r may be formed. Through this process, the second wiring structure 200 in which the fourth wiring via V4 is formed may be prepared.

Referring to fig. 6, the second wiring structure 200 may be attached to the first wiring structure 100. Specifically, the second wiring structure 200 may be inverted and may be stacked on the upper side of the first wiring structure 100, so that the second wiring layer 221 (buried pattern) disposed on the lower side may be disposed on the upper side of the first wiring structure 100. Thereafter, the third insulating layer 311 may be deposited on the second wiring structure 200, a via hole may be formed by laser processing or the like, and the via hole may be filled using a plating process to form the first wiring via V1, the second wiring via V2, and the third wiring via V3, and the third wiring layer 321 may be formed by the plating process. Through this process, the first wiring structure 100 in which the first, second, and third wiring vias V1, V2, and V3 may be formed may be additionally formed.

The printed circuit board 500A of the above-described exemplary embodiment may be manufactured through a series of processes, and a detailed description thereof will not be repeated since other descriptions may be the same as those described above.

Fig. 7 is a sectional view showing another example of the printed circuit board.

Referring to fig. 7, the printed circuit board 500B in the exemplary embodiment may further include first and second electrical connection metal pieces 415 and 425 disposed on the openings of the first and second passivation layers 410 and 420, respectively. In addition, the printed circuit board 500B in the exemplary embodiment may further include a plurality of electronic components 441 and 442 surface-mounted on the second passivation layer 420 through the second electrical connection metal member 425. The plurality of electronic components 441 and 442 may be connected to at least a portion of the third wiring layer 321 through the second electric-connection metal member 425 and may be electrically connected to each other through the plurality of second wiring layers 221 and 222 having the microcircuit pattern.

For example, the first and second electrical connection metals 415 and 425 may be formed using a low melting point metal having a melting point lower than that of copper (Cu), and may be formed using tin (Sn) or an alloy containing tin (Sn). For example, each of the first and second electrical connection metals 415 and 425 may be formed using solder, but exemplary embodiments thereof are not limited thereto. Each of the first and second electrical connection metals 415 and 425 may be a pad, a ball, a pin, etc., and may be formed in multiple layers or a single layer. When formed as a multi-layer, a copper pillar and solder may be included, and when formed as a single layer, a tin-silver solder may be included, but exemplary embodiments thereof are not limited thereto.

The plurality of electronic components 441 and 442 may include active devices and/or passive devices. The active devices may be semiconductor chips in the form of Integrated Circuits (ICs), with hundreds to millions of devices integrated in a single chip. The semiconductor chip may be implemented by a logic chip or a memory chip. The logic chip may be implemented by a CPU, a GPU, or the like (an AP (application processor) including at least one of the CPU and the GPU), an analog-to-digital converter, an ASIC, or the like, or a chipset including a combination thereof. The memory chips may be constructed as stacked memory, such as HBM. The passive device may be constructed as a chip-type passive component and may be implemented by, for example, a high frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, an LTCC, an EMI filter, an MLCC, or the like.

Descriptions of other elements are the same as the above description, and a detailed description thereof will not be provided.

According to the foregoing exemplary embodiments, a printed circuit board that can easily implement a microcircuit pattern may be provided.

Further, a printed circuit board that can ensure sufficient adhesion between the microcircuit pattern and the insulating material can be provided.

Additionally, a printed circuit board may be provided that may replace the silicon interposer.

In an exemplary embodiment, for convenience of description, the terms "side portion", "side surface", and the like may be used to refer to a surface formed in a right/left direction with respect to a cross section in the drawings, for convenience of description, the terms "upper side", "upper portion", "upper surface", and the like may be used to refer to a surface formed in an upward direction with respect to a cross section in the drawings, and the terms "lower side", "lower portion", "lower surface", and the like may be used to refer to a surface formed in a downward direction. The concept that an element is provided on a side, an upper side, a lower side, or a lower side may include a configuration in which the element is in direct contact with an element configured as a reference in various directions, and a configuration in which the element is not in direct contact with a reference element. However, for convenience of description, these terms may be defined as above, and the scope of rights of the exemplary embodiments is not particularly limited by the terms described above.

In exemplary embodiments, the term "connected" may refer not only to "directly connected," but also to "indirectly connected" through an adhesive layer or the like. Further, the term "electrically connected" may include the case where elements are "physically connected" and the case where elements are "not physically connected". Furthermore, the terms "first," "second," and the like may be used to distinguish one element from another, and may not limit the order and/or importance, etc., associated with the elements. In some instances, a first element may be termed a second element, and, similarly, a second element may be termed a first element, without departing from the scope of exemplary embodiments.

In exemplary embodiments, the term "exemplary embodiment" may not refer to one and the same exemplary embodiment, but may be provided to describe and emphasize the different unique features of each exemplary embodiment. The above suggested exemplary embodiments may be implemented without excluding the possibility of combinations with features of other exemplary embodiments. For example, even if a feature described in one exemplary embodiment is not described in another exemplary embodiment, the description may be understood as relating to another exemplary embodiment, unless otherwise specified.

While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the invention defined by the appended claims.