阅读说明：本技术 用于具有电容增益输入级的Delta-Sigma ADC的比率增益误差校准方案 (Ratiometric gain error calibration scheme for Delta-Sigma ADC with capacitive gain input stage ) 是由 V·奎凯姆波伊克斯 Z·S·特克 于 2020-05-22 设计创作，主要内容包括：本发明公开了一种模数转换器(ADC)电路,该ADC电路包括电压输入端子、参考输入端子、采样电路和控制逻辑部件。该采样电路包括输入端子、输出端子和设置在输入端子和输出端子之间的并联的电容器。该控制逻辑部件被配置为在校准操作阶段：使多路复用器将ADC参考输入端子路由到采样电压输入端子；确定给定增益值；确定要用于实现给定增益值的多个电容器的集合；连续地启用电容器子集以对参考输入端子的电压进行采样,同时禁用剩余电容器,直到所有电容器已被启用；确定产生的输出代码；以及根据该输出代码,确定ADC电路的给定增益值的增益误差。(An analog-to-digital converter (ADC) circuit includes a voltage input terminal, a reference input terminal, a sampling circuit, and a control logic. The sampling circuit includes an input terminal, an output terminal, and a parallel capacitor disposed between the input terminal and the output terminal. The control logic is configured to, during a calibration operation phase: causing a multiplexer to route an ADC reference input terminal to a sampled voltage input terminal; determining a given gain value; determining a set of a plurality of capacitors to be used to achieve a given gain value; successively enabling a subset of the capacitors to sample the voltage of the reference input terminal while disabling the remaining capacitors until all capacitors have been enabled; determining a generated output code; and determining a gain error for a given gain value of the ADC circuit based on the output code.)

1. An analog-to-digital converter (ADC) circuit, the ADC circuit comprising:

an ADC voltage input terminal;

an ADC reference input terminal;

a sampling circuit, the sampling circuit comprising:

a sampling voltage input terminal;

a sampling voltage output terminal; and

a plurality of capacitors connected in parallel and configured to be selectively enabled or disabled, the plurality of capacitors disposed between the sampled voltage input terminal and the sampled voltage output terminal;

a multiplexer connected between the ADC voltage input terminal and the sampled voltage input terminal and between the ADC reference input terminal and the sampled voltage input terminal; and

control logic configured to, during a calibration operation phase:

causing the multiplexer to route the ADC reference input terminal to the sampling voltage input terminal;

determining a given gain value of the ADC circuitry to be calibrated for gain error;

determining a set of the plurality of capacitors in the sampling circuit to be used to achieve the given gain value;

sequentially enabling a subset of capacitors of the set of the plurality of capacitors,

to sample a voltage of the ADC reference input terminal at the sampling voltage input terminal while disabling remaining capacitors of the set of the plurality of capacitors until all capacitors of the set of the plurality of capacitors have been enabled;

determining an output code generated after enabling all capacitors in the set of the plurality of capacitors; and

determining a gain error for the given gain value of the ADC circuit from the output code;

wherein the control logic is further configured to take corrective action based on the gain error for the given gain value of the ADC circuitry.

2. The ADC circuit of claim 1, wherein enabling each subset of the set of the plurality of capacitors is configured to set the ADC circuit to perform gain 1.

3. The ADC circuit of any one of claims 1 to 2, wherein each subset of the set of the plurality of capacitors is enabled for a same number of samples.

4. The ADC circuit of any of claims 1 to 3, wherein the control logic is further configured to, during the calibration operation phase:

determining another gain value of the ADC circuitry to calibrate for a gain error;

determining another set of the plurality of capacitors in the sampling circuit to be used to achieve another gain value;

continuously enabling a subset of capacitors of the other set of the plurality of capacitors to sample a voltage of the ADC reference input terminal at the sampled voltage input terminal while disabling remaining capacitors of the other set of the plurality of capacitors until all capacitors of the other set of the plurality of capacitors have been enabled;

determining another output code generated after enabling all capacitors in the another set of the plurality of capacitors; and

determining a gain error for the other gain value of the ADC circuit from the other output code.

5. The ADC circuit of any of claims 1 to 4, wherein the control logic is further configured to:

sampling a voltage of the ADC reference input terminal at the sampling voltage input terminal to obtain a given number of samples; and

sampling each subset of the set of the plurality of capacitors to obtain a subset of the given number of samples, the subset of the given number of samples being equal to the given number of samples divided by the given gain value.

6. The ADC circuit of claim 5, wherein a result of the division of the given number of samples by the given gain value has no remainder.

7. A system, the system comprising:

an ADC circuit, the ADC circuit being any one of the ADC circuits of claims 1-6;

an input voltage connected to the ADC voltage input terminal of the ADC circuit, the ADC circuit configured to convert the input voltage to the output code; and

a reference voltage source connected to the ADC reference input terminal of the ADC circuit, the ADC circuit configured to convert the input voltage according to a range defined by the reference voltage source.

8. A method comprising operation of a system or ADC circuit configured according to any of claims 1 to 7.

Technical Field

The present disclosure relates to analog-to-digital converters (ADCs), and more particularly, to a rate gain error calibration scheme for Delta Sigma (Delta-Sigma) ADCs having capacitive gain input stages.

Background

Analog-to-digital converters are used in electronic devices for consumer, industrial applications, and the like. Typically, an analog-to-digital converter includes circuitry for receiving an analog input signal and outputting a digital value proportional to the analog input signal. The digital output value is typically in the form of a parallel word or a serial digital bit string. There are many types of analog-to-digital conversion schemes such as voltage-to-frequency conversion, charge redistribution, integral modulation, and others. Generally, each of these conversion schemes has its advantages and disadvantages. An increasingly used type of analog-to-digital converter is the switched capacitor delta-sigma converter.

The input stage of the ADC may be implemented using a switched capacitor sampling circuit for both the input voltage and the reference voltage. The gain of the input stage can then be determined by the ratio between the input sampling capacitor and the reference sampling capacitor or the ratio between a pair of capacitors for a fully differential structure. The gain of the input stage of the ADC may be used to more closely match the input of the ADC to a range within which the ADC is configured to convert an analog signal to a digital signal. For example, if the voltage range of the ADC is 0 to 2 volts, but the expected ADC input would only be in the range of 0 to 1 volt, the ADC may apply a gain of 2 to its input, such that the possible values of the ADC input match the range of the ADC.

The use of gain in the input stage of the ADC may introduce gain errors. The gain error may be tested using a known, accurate reference voltage or source voltage. The accurate reference voltage or source voltage may be equal to the voltage of the ADC divided by the gain of the ADC. However, when ADCs are deployed in various electronic devices, such electronic devices may not include or have access to an accurate reference or source voltage. Thus, self-testing of such ADCs may not be possible or practical. Also, testing an ADC may require testing each gain permutation or combination of capacitive gains in the input stage. Therefore, testing such ADCs can be very slow, as each gain setting must be tested and its setup time can be long. The inventors of embodiments of the present disclosure have discovered systems and methods for testing ADCs that address one or more of these challenges.

Disclosure of Invention

Embodiments of the present disclosure may include an analog-to-digital converter (ADC) circuit. The ADC circuit may include an ADC voltage input terminal, an ADC reference input terminal, and a sampling circuit. The sampling circuit may include a sampled voltage input terminal, a sampled voltage output terminal, and a capacitor connected in parallel and configured to be selectively enabled or disabled. The capacitor may be disposed between the sampling voltage input terminal and the sampling voltage output terminal. The ADC may include a multiplexer connected between the ADC voltage input terminal and the sampled voltage input terminal and between the ADC reference input terminal and the sampled voltage input terminal. The ADC may comprise control logic configured to, during a calibration operation phase: causing a multiplexer to route an ADC reference input terminal to a sampled voltage input terminal; determining a given gain value of the ADC circuit to be calibrated for the gain error; determining a set of capacitors to be used to achieve a given gain value; continuously enabling a subset of capacitors of the set of multiple capacitors to sample a voltage of an ADC reference input terminal at a sampling voltage input terminal while disabling remaining capacitors of the set of capacitors until all capacitors of the set of multiple capacitors have been enabled; determining an output code generated after enabling all capacitors in the set of the plurality of capacitors; determining a gain error for a given gain value of the ADC circuit from the output code; and taking corrective action based on the gain error for the given gain value of the ADC circuit.

Embodiments of the present disclosure may include a system. The system may comprise a reference voltage source connected to an ADC reference input terminal of the ADC circuit and the ADC circuit of any of the above embodiments.

Embodiments of the present disclosure may include methods performed by any of the systems or ADCs of the above embodiments.

Drawings

Fig. 1 is an illustration of an example system for ADC gain error calibration, according to some implementations.

Fig. 2 is a diagram of an example system for ADC ratio gain error calibration, according to an embodiment of the present disclosure.

Fig. 3 illustrates an example implementation of an analog input multiplexer according to an embodiment of the present disclosure.

Fig. 4 is an illustration of an example implementation of a delta-sigma modulator circuit, according to an embodiment of the present disclosure.

Fig. 5 illustrates an example implementation of a sampling circuit according to an embodiment of the present disclosure.

Fig. 6 shows a timing diagram generated by the control circuit and applied to the sampling circuit, according to an embodiment of the present disclosure.

Fig. 7 depicts another timing diagram to be applied to a sampling circuit according to an embodiment of the present disclosure.

Fig. 8 is an illustration of an example method for determining a ratiometric gain error of an ADC having a capacitive gain input stage, in accordance with an embodiment of the disclosure.

Detailed Description

Embodiments of the present disclosure include ADC circuits. The ADC circuit may be included in any larger electronic device. The ADC circuit may include an ADC voltage input terminal. With this ADC voltage input terminal, the ADC circuit may be configured to receive a voltage for which analog-to-digital conversion is to be performed during normal operation. The ADC circuit may include an ADC reference input terminal. With the ADC reference input terminal, the ADC circuit may be configured to receive a reference voltage defining a range of voltages to be analog-to-digital converted. The ADC circuit may include a sampling circuit. The sampling circuit may be configured to sample an input routed thereto. The sampling circuit may include a sampling voltage input terminal and a sampling voltage output terminal. Further, the sampling circuit may include capacitors connected in parallel and configured to be selectively enabled or disabled. The number of capacitors enabled may define the gain of the sampling circuit, and thus the gain of the ADC. The capacitor may be disposed between the sampling voltage input terminal and the sampling voltage output terminal. The ADC circuit may include a multiplexer connected between the ADC voltage input terminal and the sampled voltage input terminal and between the ADC reference input terminal and the sampled voltage input terminal. The ADC circuit may include an integrating circuit, such as a delta-sigma analog loop circuit, to accumulate values sampled by the sampling circuit and generate an output code. The ADC circuit may include control logic. The control logic may be configured to cause the multiplexer to route the ADC reference input terminal to the sample voltage input terminal during a calibration operation phase and to determine a given gain value of the ADC circuit for which the gain error is to be calibrated. The control logic is configured to, during a calibration operation phase: determining a set of a plurality of capacitors in a sampling circuit to be used to achieve a given gain value; and successively enabling a subset of capacitors of the set of capacitors to sample a voltage of the ADC reference input terminal at the sampling voltage input terminal while disabling remaining capacitors of the set of capacitors until all capacitors of the set of capacitors have been enabled. The control logic may be configured to determine, during a calibration operation phase, an output code generated after all capacitors in the set of capacitors are enabled. The control logic may be configured to determine a gain error for a given gain value of the ADC circuit from the output code during a calibration operation phase. The control logic may be further configured to take corrective action based on a gain error for a given gain value of the ADC circuit. The corrective action may include, for example, alerting a user of the ADC circuit, adjusting an input range of the ADC circuit, or adjusting an output of the ADC circuit.

In combination with any of the above embodiments, each subset of the set of enabling capacitors may be configured to set the ADC circuit to perform a gain of 1.

In combination with any of the above embodiments, the given gain value of the ADC circuit may be a multiple of 2.

In combination with any of the above embodiments, each subset of the set of capacitors may be enabled for the same number of samples.

In combination with any of the above embodiments, the control logic may be further configured to: determining another gain value of the ADC circuit to be calibrated for the gain error during a calibration operation phase; determining another set of capacitors in the sampling circuit for implementing another gain value; continuously enabling a subset of capacitors in the other set of capacitors to sample a voltage of the ADC reference input terminal at the sampling voltage input terminal while disabling remaining capacitors in the other set of capacitors until all capacitors in the other set of capacitors have been enabled; determining an output code generated after enabling all capacitors in the set of another plurality of capacitors; and determining a gain error for another gain value of the ADC circuit from the output code. This may be repeated for any suitable gain value of the ADC circuit.

In combination with any of the above embodiments, the control logic may be further configured to sample a voltage of the ADC reference input terminal at the sampling voltage input terminal to obtain a given number of samples; and sampling each subset of the set of the plurality of capacitors to obtain a subset of the given number of samples, wherein the subset of the given number of samples is equal to the given number of samples divided by the given gain value.

In combination with any of the above embodiments, there is no remainder for the division of a given number of samples by the resulting number of a given gain value.

Fig. 1 is an illustration of an example system 100 for ADC gain error calibration, according to some implementations. The system 100 may include an ADC 102. ADC 102 may be a delta-sigma ADC. The system 100 may be configured to determine a gain error in the ADC 102.

The ADC 102 may be configured to convert an analog input signal into a digital output code. The analog input signal may be single-ended (not shown, in which case a voltage is received as an input and compared to a ground voltage) or differential, as shown in fig. 1. The differential analog input may be the voltage difference between the VIN + terminal and the VIN-terminal of ADC 102, resulting in a sum VIN (VIN + — VIN-). The ADC 102 may be configured to receive a reference voltage. The reference voltage may be single ended (not shown, in which case the voltage is received as a reference and the received reference voltage is compared to a ground voltage) or differential, as shown in fig. 1. The differential analog input may be the voltage difference between the VREF + terminal and the VREF-terminal of ADC 102, resulting in a sum VREF, which is given by:

VREF＝VREF+-VREF-

these differential voltages may be added to some common mode, not depicted in the figure. The output code may be a value proportional to VIN/VREF. The ADC code may be given by:

ADC code K VIN/VREF

Where K is a constant.

The ADC 102 may have an analog gain denoted G. The analog gain G amplifies the input signal VIN inside the ADC 102 such that the voltage converted by the ADC 102 is effectively G VIN. In this case, the transfer function of the ADC 102 becomes:

ADC code G K VIN/VREF

VREF may define a range of voltage inputs that may be converted by ADC 102. For a single-ended converter, the range of input voltages suitable for a/D conversion may then be the range [0, VREF ]. For a fully differential converter, the input voltage range suitable for a/D conversion may be the range [ -VREF, + VREF ]. When the gain G is applied, the input voltage range of the ADC 102 remains the same, but applies to G VIN, so that the input voltage range effectively becomes the range of a single-ended converter [0, VREF/G ] and the range of a fully-differential converter [ -VREF/G, + VREF/G ]. Outside this range, a/D conversion may suffer greater inaccuracies, the output code may be clipped, and the overall linearity of the converter may no longer be guaranteed.

The ADC 102 may be configured to achieve the analog gain G by various methods, but due to physical implementation limitations (such as mismatch between analog components in the ADC 102), the actual transfer function performance of the ADC 102 may not be exactly equal to the expected or ideal transfer function performance. Thus, the system 100 may cause the gain measurement and compensation to be performed in the ADC 102 so as to be closer to the desired or ideal transfer function (G × K × VIN/VREF). The error produced in achieving the gain of the transfer function is referred to as the gain error of the ADC. The ADC transfer function may then be equal to G K 'VIN/VREF, where (K'/K-1) is the gain error of gain G. The inventors of embodiments of the present disclosure have found that the gain error may vary and depend on the gain G, in addition to other parameters such as temperature or supply voltage. The gain error is the error in the slope of the linear transfer function of the ADC 102. Other errors may also occur and be characterized, where such errors occur in addition to gain errors. Such other errors may include offset errors, integral non-linearity errors, and differential non-linearity errors. These other errors may be independent of the gain error and may be accounted for separately.

To measure the gain of the ADC 102 (and thus evaluate the gain error), two measurements are performed. From these two measurements, the equation of the line of intersection of these data points can be extracted and the slope of the line determined. If the two points are further apart, the measurement-induced inaccuracies will become less important, and can be ignored if the measurement inaccuracies are small compared to the measured voltage. Typically, these two measurements are made over the 0 voltage input and full scale voltage range (FS) of the single ended converter and the negative full scale (-FS) and positive full scale (+ FS) of the fully differential converter. The full-scale signal may include an extreme value of the input voltage range. To maximize the accuracy of the gain error measurement, the system typically measures in the following manner: for a single-ended converter, VIN is set to zero and VIN is set to FS, which is (REF/G); for a fully differential converter, VIN-is set to-FS, which is (-VREF/G), and VIN + is set to FS, which is (VREF/G). This is depicted in fig. 1 as the VIN input of ADC 102 being connected to voltage source 101 which applies either a-FS value, a 0 value, or a + FS value. Meanwhile, the VREF input of ADC 102 is connected to voltage source 103, whose value is constant and equal to VREF.

The zero value measurement may measure the offset of the ADC 102. To measure the offset, zero volts may be applied at the VIN input of the ADC 102 and the output of the ADC 102 observed. A zero value measurement may be achieved by shorting the VIN + and VIN-inputs together, resulting in VIN at the VIN input of ADC 102 being 0. This may be performed inside ADC 102. However, this may be more difficult to accurately generate the FS signal, where the entire input range of the ADC 102 is used by the voltage input. When G ═ 1, VIN with VREF voltage can be generated by input switches that multiplex the VREF input and VIN input. However, if G is not equal to 1, the FS signal cannot be easily generated because it is not a simple replica of the existing voltage, such as by shorting VIN + and VIN-to get 0 volts, or by connecting to the VREF + and VREF-terminals to get VREF. The FS-VREF/G input voltage is typically generated by another voltage source or by a DAC using a reference voltage as a reference element. However, the inventors of the present disclosure have found that such FS signals may be inaccurate due to total unregulated error of the DAC or inaccuracy of the reference voltage. The inaccuracy of the reference voltage may directly result in creating an additional source of error in the gain measurement of the ADC 102 and, in some cases, may even be a major source of error in the performance of the ADC 102. Also, adding a DAC or voltage source to generate such a reference voltage may increase the overall system cost of the system 100. Furthermore, during operation of the system 100, the DACs or voltage sources added to generate such reference voltages may not be effectively applied to the ADC 102 to measure gain error. Furthermore, because a given ADC may include many different gain settings, a different voltage is generated for each new value of G to be tested. The settling time required to create each such reference voltage may delay the evaluation of ADC 102.

Accordingly, the inventors of embodiments of the present disclosure have found that a system that does not require the FS signal to be generated by dividing the reference voltage by the gain (VREF/G) to measure the gain error is desirable. The inventors of embodiments of the present disclosure have discovered a system that may have significant advantages, such as no need for an external voltage source or DAC, and a shorter settling time. Such systems may measure gain error using only zero value measurements (VIN-0) and VIN-VREF voltages instead of full scale (VREF/G) voltages, thereby reducing inaccuracies caused by voltage measurements by using input voltages across all gains. However, with a standard ADC, a gain greater than 1 cannot allow the input voltage VIN to be greater than VREF/G (and therefore VIN × G is greater than VREF). Embodiments of the present disclosure address at least some of these issues and include an ADC that allows for the input VIN ═ VREF for any given gain G, while still allowing for accurate evaluation of the gain error obtained if any given gain G is selected and applied to the ADC.

Fig. 2 is an illustration of an example system 200 for ADC ratio gain error calibration, according to an embodiment of the disclosure.

System 200 may be suitable or include any suitable ADC, such as ADC 203. The ADC 203 may be included in a microcontroller, processor, mobile device, computer, smartphone, tablet, power converter, controller, power supply, sensor, vehicle, or any other suitable electronic device. ADC 203 may be a delta-sigma ADC. Also, the ADC 203 may include a capacitive gain input stage. The system 200 may be configured to determine a gain error in the ADC 203. Moreover, system 200 may be configured to calibrate the operation of ADC 203 based on any determined gain error, or take any other suitable corrective action.

ADC 203 may include ADC voltage input terminals such as VIN + and VIN-. ADC 203 may include ADC reference input terminals, such as VREF + and VREF-.

The ADC 203 may be configured to convert an analog input signal to a digital output code. The analog input signal may be single-ended (not shown, in which case a voltage is received as an input and compared to ground) or differential, as shown in fig. 2. The differential analog input may be the voltage difference between VIN + and VIN-, such that the sum VIN (VIN + — VIN-) may be obtained. The ADC 203 may be configured to receive a reference voltage. The reference voltage may be single ended (not shown, in which case the received voltage is taken as a reference and the received reference voltage is compared to ground) or differential, as shown in fig. 2. The differential analog input may be the voltage difference between VREF + and VREF-, so that the sum VREF is available (VREF ═ VREF + — VREF-). These differential voltages may be added to some common mode, not depicted in the figure. The output code may then be a value proportional to VIN/VREF (ADC code K VIN/VREF, where K is a constant).

The ADC 203 may have a variable, selectable gain, whose value is denoted as G. The analog gain G amplifies the input signal VIN inside the ADC 203 such that the voltage converted by the ADC 102 is effectively G VIN. In this case, the transfer function of the ADC 203 becomes

ADC code G K VIN/VREF

VREF may define a range of voltage inputs that may be converted by ADC 203. For a single-ended converter, the input voltage range suitable for a/D conversion may be [0, VREF ]. For a fully differential converter, the input voltage range suitable for A/D conversion may be [ VREF-, VREF + ]. When gain G is applied, the input voltage range of ADC 203 remains the same, but applies to G VIN, so the input voltage range effectively becomes [0, VREF/G ] for single-ended converters and [ VREF-/G, VREF +/G ] for fully-differential converters. Outside this range, a/D conversion may suffer greater inaccuracies, the output code may be clipped, and the overall linearity of the converter may no longer be guaranteed.

The ADC 203 may be connected to a voltage source 201. The voltage of voltage source 201 may be selected between +/-VREF or 0. The voltage source 201 may generate a voltage external to the system 200 (using an external voltage source or multiplexer) or internal to the system 200. These voltages may be applied through analog input multiplexer 204. The analog input multiplexer 204 may be implemented in any suitable manner. Analog input multiplexer 204 may be configured to generate the VOUT signal (VOUT + -VOUT-), such that VOUT ═ VREF or 0. The VOUT signal may be provided to delta-sigma modulator circuit 205.

The ADC 203 may be a delta-sigma ADC, and thus include a delta-sigma modulator circuit 205. The delta-sigma modulator circuit 205 may be implemented in any suitable manner, e.g., by digital circuitry, analog circuitry, instructions executed by a processor (not shown), or any suitable combination thereof. The delta-sigma modulator circuit 205 may include stages with analog gain G to enable amplification of an input received on the VI +/VI-input terminals. The delta-sigma modulator circuit 205 may receive the reference voltage signal routed from the VREF +/-input terminal of the ADC 203 without any modification.

The system 100 may include a voltage reference component 202. The voltage reference component 202 may be implemented in any suitable manner. The voltage reference component 202 may generate a reference voltage for the system 200. The voltage reference component 202 may be internal to the ADC 203 (not shown) or external to the ADC 203 in the system 200. Also, the voltage reference component 202 may be external to the system 200.

The delta-sigma modulator circuit 205 may be configured to generate a bitstream based on its input. The voltage inputs of the delta-sigma modulator circuit 205 (to be amplified according to the gain G) may be represented as VI + and VI-. The delta-sigma modulator circuit 205 may also include inputs for reference voltages, denoted as VREF + and VREF-. The bit stream may be sent to a digital filter 206. Digital filter 206 may be implemented by digital circuitry, analog circuitry, instructions executed by a processor (not shown), or any suitable combination thereof. The digital filter 260 may be configured to produce a digital output code at the end of the conversion period, with a time increment denoted TCONV. TCONV may be long enough for the delta sigma modulator circuit 205 to process its input to generate a bitstream.

In one embodiment, system 200 may be configured to evaluate the gain error of ADC 203 for any given gain G (G integer) setting without generating a different reference signal, e.g., +/-VREF/G signal. In another embodiment, the system 200 may be configured to evaluate the gain error of the ADC 203 without switching the existing voltage at the input of the delta-sigma modulator circuit 205 by using the analog input multiplexer 204 to generate any external voltage reference or DAC.

The ADC 203 may include control logic 207. The control logic 207 may be implemented by digital circuitry, analog circuitry, instructions executed by a processor, or any suitable combination thereof. The control logic 207 may be configured to selectively operate the ADC 203 during a calibration phase of operation or during a normal phase of operation. During the calibration phase, the input of the delta-sigma modulator circuit 205 may be controlled to operate the ADC 203 in a manner that evaluates whether the ADC 203 has any gain errors, and based on such a determination, the operation of the ADC 203 is adjusted to account for such gain errors. In this normal phase, the input of the delta-sigma modulator circuit 205 may be controlled to operate the ADC 203 in a manner that generates a digital code output based on the inputs from the voltage source 201 and the reference component 202, which reflect the analog signal for which the system 200 requests an associated digital value. The control logic 207 may be configured to selectively operate one or more of the analog input multiplexer 204, the delta-sigma modulator circuit 205, and the digital filter 206.

During a calibration operation phase, the multiplexer 204 may be configured to route the ADC reference input terminals VREF +/VREF-to the sampled voltage input terminals VI + and VI-of the delta-sigma modulator circuit 205 and the sampling circuitry therein. During normal operation, the multiplexer 204 may be configured to route the ADC voltage input terminals VIN +/VIN-to the sampled voltage input terminals VI + and VI-of the delta-sigma modulator circuit 205 and the sampling circuits therein.

Fig. 3 illustrates an example implementation of an analog input multiplexer 204 according to an embodiment of the present disclosure. The analog input multiplexer may include eight switches 301-308. Switch 301 may connect VIN + to VOUT +. Switch 302 may connect VIN-to VOUT +. Switch 303 may connect VREF + to VOUT +. Switch 304 may connect VREF-to VOUT +. Switch 305 may connect VIN + to VOUT-. Switch 306 may connect VIN-to VOUT-. Switch 307 may connect VREF + to VOUT-. Switch 308 may connect VREF-to VOUT-. At any given time, only one of the switches 301, 302, 303, and 304 may be enabled, with the remainder disabled. Likewise, only one of the switches 305, 306, 307, and 308 may be enabled, with the remainder disabled/turned off. The enabling or disabling of the switches in fig. 3 may be performed in the direction of the control logic 207 (not shown). This implementation allows for the generation of a desired +/-VREF or zero differential voltage. For a zero value measurement, switch 301 and switch 305 may be enabled, or switch 302 and switch 306 may be enabled. For a + VREF measurement, switch 303 and switch 308 may be enabled. For a-VREF measurement, switch 304 and switch 307 may be enabled. In each of these examples, the remaining switches may be disabled. Although shown as separate components, the analog input multiplexer 104 may be implemented as a particular circuit internal to the ADC 203, external to the ADC 203, or internal to the delta-sigma modulator circuit 205. Analog input multiplexer 204 may also include additional components and may be implemented as part of a larger multiplexer, so long as analog input multiplexer 204 can connect VOUT to either +/-VREF or 0 throughout the A/D conversion.

Fig. 4 is an illustration of an example implementation of a delta-sigma modulator circuit 205, according to an embodiment of the disclosure.

The delta-sigma modulator circuit 205 may include a sampling circuit 401, a control circuit 402, and a delta-sigma analog loop circuit 403. The sampling circuit 401, control circuit 402, and delta-sigma analog loop circuit 403 may be implemented by analog circuits, digital circuits, instructions executed by a processor (not shown), or any suitable combination thereof.

The sampling circuit 401 may include sampling voltage input terminals VI + and VI-. The sampling circuit 401 may be configured to sample the input voltage on VI + and VI-. Furthermore, sampling circuit 401 may be configured to apply a gain G to the input voltage signal and output these signals on sampling voltage output terminals VO + and VO-. The sampling circuit 401 may be configured to operate based on a command or signal of the control circuit 402. The control circuit 402 may also receive commands or signals from the control logic 207 (not shown). The delta-sigma analog loop circuit 403 may be configured to generate an output bitstream to be fed to the digital filter 206 in the ADC 203. The reference input signals for VREF + and VREF-, (also denoted as VREF + and VREF-) may be routed unmodified to the delta-sigma analog loop input circuit 403 reference pin.

Fig. 5 illustrates an example implementation of a sampling circuit 401 according to an embodiment of the present disclosure. In one embodiment, as shown in FIG. 5, sampling circuit 401 may be implemented in a fully differential manner. It can be implemented in a single-ended fashion, with VI-ground.

The sampling circuit 401 may have two pairs of input switches 501 and 502. In a crossbar implementation, input switch 501 and input switch 502 may be connected to input VI +/-, where VI + is connected to switch 501A and switch 502B, and VI-is connected to switch 502A and switch 501B. The switch 501 may be controlled by a first switch control signal S1. The switch 502 may be controlled by a second switch control signal S2. Switch 501A and switch 502A may be connected to capacitor array 507A. Switch 501B and switch 502B may be connected to capacitor array 507B. The capacitor array 507 may be implemented by capacitors in parallel and configured to be selectively enabled or disabled. The capacitor array 507 may be configured to be disposed between the sampling input voltage terminal VI + and the sampling input voltage terminal VI-and between the sampling output voltage terminal VO + and the sampling output voltage terminal VO-.

Capacitor array 507A may include a series of input switches 505A and a series of output switches 506A configured to select which capacitance of capacitor array 507A will be connected to input switch 501A and input switch 502A. Likewise, capacitor array 507B may include a series of input switches 505B and a series of output switches 506B configured to select which capacitance of capacitor array 507B will be connected to input switch 501B and input switch 502B. Each capacitor array 507 may include up to n pairs of capacitors having the same and matched values, with the capacitors in capacitor array 507A being designated CIN_1...n+ and the capacitors in capacitor array 507B are named CIN_1...n-. Switch 505 and switch 506 may be controlled by a command SG applied to two capacitor arrays 507_1...nControl so that the enable command SG is given_kEnabled capacitor CIN_k+/-to sample the input signal routed by switch 501 and switch 502. Switch 501 and switch 502 may not be enabled at the same time. The switch commands S1 and S2 applied to switch 501 and switch 502, respectively, can be clocked in a non-overlapping manner on two different phases of the same clock. Switches 503A and 503B may be configured to couple each CIN via voltage source 504_1...nEach plate of the +/-capacitor is connected to an internal common mode Voltage (VCM). The VCM may also be generated externally. If all capacitors are matched and only G pairs of capacitors are actually connected through switch 505 and switch 506, the gain of the system will be G times that of the case where only one pair of capacitors is connected through one pair of switches 505 and 506. Thus, sampling circuit 401 effectively achieves analog gain G while sampling the input signal present at input VI +/V. If G capacitors are selected, the sampled charge on capacitor array 507 will be G times greater than if only one capacitor were selected to sample the VI + and VI-input signals. The VO +/-output may then be sent to a delta-sigma loop circuit 403, which may be configured to evaluate the amount of charge already stored on the sampling circuits within the capacitor array 507 and thus generate a bit stream that will be filtered by the digital filter 206 to give the output code of the ADC 203. Other sources of gain error may be inherent to the delta-sigma analog loop circuit 403, the delta-sigma modulator circuit 205, or the digital filter 206. However, these errors may not depend on the gain G, and this may be ignored for simplicity of the description of the present disclosure.

The gain G realized by the sampling circuit 401 is affected by inaccuracies in its realization, such as CIN_1...nCapacitor mismatch between +/-capacitors. The gain may also be affected by the parasitic capacitors used to implement switch 505 and switch 506. Therefore, such switches should be made small enough so that additional capacitance is associated with each CIN_1...nThe unit capacitance of +/-is negligible by comparison. Switch 505 and switch 506 should also be implemented such that the leakage current through them is negligible when they are in the disabled state. Since ADC 203 is a delta-sigma converter, delta-sigma analog loop circuit 403 may include an integrator circuit, and thus any leakage current from sampling circuit 401 may be integrated into the loop, resulting in potentially greater inaccuracies. This leakage current effect can be minimized by appropriate switching implementation techniques and faster switching times. These inaccuracies are taken into account in the gain error measurement system described herein. The maximum gain of the sampling circuit 401 is determined by the number of paired capacitors in each array 507. At the position ofIn the example, the maximum value is n. The source of gain error at each incremental value of ADC 203 is primarily in sampling circuit 401 due to capacitor mismatch and switching inaccuracies.

During the calibration operation phase, the control circuit 402 and the control logic 207 may be configured to issue switching signals to the switch 501, the switch 502, the switch 503, the switch 505, and the switch 506. Such switching signals are shown in more detail in the timing diagrams below. Control logic 207 may be configured to operate multiplexer 204 to route a reference voltage input (VREF) of ADC circuit 200 to the VI +/-input of sampling circuit 401 during a calibration operation phase. The control circuit 402 and control logic 207 may be configured to determine what gain value to test. The gain value to be tested may be determined on any suitable basis, such as by a command to the ADC circuit 200, a register value, a setting, or any other suitable input. Also, the possible gain values of the ADC circuit 200 may be tested continuously. Based on the gain values to be tested, control circuit 402 and control logic 207 may be configured to determine which subsets of capacitors 507 are associated with the gain values. The subset may be defined in terms of capacitor pairs. Which capacitor subsets 507 are associated with gain values may be determined in any suitable manner, such as with reference to user commands, settings, or register values. Based on which subsets of capacitors 507 associated with the gain values, each subset is enabled in turn for a determined number of samples, while the other subsets and the remainder of capacitors 507 are disabled. This may be performed by using control signals sent to switch 501, switch 502, switch 503, switch 505, and switch 506, as will be shown in more detail below. This process may be repeated for each subset of capacitors 507 associated with a gain value. During the enabling of each subset of capacitors 507, the ADC circuit 200 and the sampling circuit 401 may have an effective gain of 1. Each subset of capacitors 507 may be enabled for the same number of samples. After all subsets of the capacitors 507 associated with the gain values have been enabled, the values stored in the capacitors 507 may be integrated by the delta-sigma analog loop circuit 403, which may generate an output code in the form of a bit stream. The control logic 207 may be configured to take corrective action to correct the gain error based on the gain error determined from the output code. The control logic 207 may determine another gain value of the ADC circuit 200 for the ADC circuit 200 to be calibrated, determine another set of capacitors 507 to implement the another gain value, successively enable a subset of the set of capacitors 507 while disabling the remaining capacitors 507, determine another output code resulting from enabling all capacitors 507 of the other set, and determine another gain error for the another gain value of the ADC circuit 200 from the another output code. The control logic 207 may be configured to sample each subset of the set of capacitors 507 to obtain a subset of the total number of samples. All sampling may be performed across all subsets to obtain a given gain value. The total number of samples taken for a given gain value divided by the given gain value is the number of samples in each subset of the total number of samples. The total number of samples divided by the gain value may have no remainder.

Fig. 6 shows a timing diagram to be generated by the control circuit 402 and applied to the sampling circuit 401 according to an embodiment of the present disclosure. The timing diagram of fig. 6 depicts switch command S1, switch command S2, and switch command SG during a standard transition in normal phase for a given set value of analog gain G of ADC 203_1...n. With this timing diagram, when converting from voltage to charge by using the capacitor array 507, the voltage converted at the input VIN +/-of the VIN terminal of the ADC 203 is amplified by a factor of G within the sampling circuit 401.

In fig. 6, the timing diagram shows one switching cycle with a total time TCONV. One conversion may be divided into multiple samples. The necessary number of samples may be an over-sampling rate (OSR). Each sample is clocked with a constant sample time taken at the sampling frequency fs. Therefore, the temperature of the molten metal is controlled,

TCONV＝OSR/fs。

to achieve gain G, control circuit 402 may have to be SG_1...nThe switch generates a control signal. Of the n pairs of capacitors in the capacitive array 507, only the digital G should be selected to achieve the gain G. The particular capacitor of the n capacitors may be chosen arbitrarily, but since the gain error depends largely on the capacitor mismatch, the control circuit 402 should always choose the same capacitanceThe pair of taps to produce a repeatable gain error at each transition so that the gain error can be taken into account. Since the order of selecting the capacitors is not important, the example shown in fig. 6 selects the first SG_1...GA pair of capacitors. These capacitor pairs are selected by enabling respective ones of switches 505 and 506. In FIG. 6, SG_1...GThe timing diagram shows that the logic signal is high during the entire transition period (where a logic high enables the switch in the convention selected in fig. 6). Other switches SG_G+1...nIs disabled (logic low level during the entire transition period) and therefore does not sample the charge on these capacitors at the time of transition.

During each sampling period, the signals S1 and S2 that control the switches 501, 502, and 503 represent two phases of the same clock running at the fs frequency. To avoid any short circuits, these signals are not simultaneously logic high. During stage S1 (when S2 is logic low and S1 is logic high), switch 501 and switch 503 are enabled, thus at capacitor CIN_1...GThe input voltages VI + and VI-are sampled on +/-S. During this time, the input voltage is converted into electric charges stored in the capacitor array 507. If all capacitors are matched and their value is equal to C, then the storage on capacitor CIN is made_1...GThe sum of the charges on + will be equal to G C (VI + -VCM). Likewise, stored in capacitor CIN_1...GThe sum of the charges on-will be equal to G C (VI — VCM). Thus, the total charge difference between the capacitors is

Q＝G*C*(VI+-VI-)。

If each capacitor is equal to CIN_kAnd is therefore equal to C × e_k(error factor e for each capacitor is taken into account_k) Then the sum will be

Q＝C*Σ{(e_k)*(VI+-VI-)}。

Here, for simplicity, the capacitor has been defined as CIN_k+ and CIN_kEqual because their mismatch between positive and negative results in common mode variations that will be filtered out by the fully differential nature of the converter. The gain error will be

GERR＝Σ{(e_k)/G-1}。

The gain error is caused by capacitor mismatch and includes parasitic effects of each capacitor in switch 505 and switch 506. The gain error is the ADC gain error caused by the sampling circuit 401. The ADC 203 may have other sources of gain error, but these may not rely on gain selection, but rather are inherent to other parts of the system 200. Therefore, these other sources of gain error should remain constant as the gain selection changes, and because they do not affect this, they can be ignored for gain error measurement.

During the S2 phase (when S2 is a logic high level and S1 is a logic low level), terminal VO + and terminal VO-are typically connected to virtual ground (e.g., the input of an operational amplifier) so that the charge stored on the capacitor can be transferred to the rest of the circuitry to be integrated in the delta-sigma analog loop circuit 403. In this example, switch 502 is enabled and switches 501 and 503 are disabled. By connecting switch 502 to the opposite input (compared to switch 501), another sampling of the VI +/-input is performed, in synchronism with the charge transfer achieved in stage S2. This extra sampling does not change the gain error but has the effect of multiplying the gain of the sampling circuit by 2, so it improves the signal-to-noise ratio of the sampling and transmission events at each sampling time. Then, the total charge of the S1 and S2 phases is given by:

Qtot＝2*C*Σ(e_k)*(VI+-VI-)。

in one embodiment, sampling circuit 401 may be used in a configuration where the gain would be 1 instead of G, but where the gain error would be substantially equal to the estimated gain error when the gain is G, as shown in fig. 6. In one embodiment, no modification of sampling circuit 401 may be required to achieve the case where the gain is 1 but the gain error is substantially equal to the estimated gain error for gain G. Instead, the control of switches 505 and 506 may be modified as described below.

Fig. 7 depicts another timing diagram to be applied to the sampling circuit 401 according to an embodiment of the present disclosure. The timing diagram of fig. 7 may achieve the same gain error as the timing diagram of fig. 6, but the timing diagram of fig. 7 may define this same gain error with a gain of 1 when applied to sampling circuit 401.

In fig. 7, the signal S1 and the signal S2 are the same as the signal S1 and the signal S2 in fig. 6. The sampling events are timed simultaneously. Signal SG_G+1...nAlso similar to FIG. 6, wherein capacitor pairs CIN_G+1...nRemain unselected during the transition period. Since these signals are identical, they are not shown in fig. 7.

The timing diagram of fig. 7 may enable gain errors for different gain settings while using signal SG_1...GTo use only gain 1. In fig. 7, the SG is simultaneously enabled at each sampling time_1...GOnly one signal of. If all capacitors are matched, the charge stored by the sampling circuit on each phase will be equal to Q ═ C (VI + -VI-), resulting in a gain of 1. This is in contrast to the timing diagram of fig. 6, where the stored charge is Q ═ G × (VI + -VI-). When the capacitor has a capacitance of CIN_k＝C*e_kWith a defined mismatch, CIN is measured at the capacitor each time a sample is taken_kThe charge sampled up will be

Q_k＝2*e_k*C*(VI+-VI-)。

The factor 2 comes from the double sampling achieved in the S1 and S2 phases.

Enable signal SG during a certain number of OSR/G samples_1…GEach signal of (1). This imposes conditions on G and OSR, where OSR should be a multiple of G. The control circuit 402 may be configured to define the OSR such that the OSR is a multiple of G. Further, the digital filter 206 may be configured to generate the desired decimation using OSR samples, where OSR is a multiple of G.

The delta-sigma analog loop circuit 403 may be configured to perform integration to average each sample. Thus, the conversion output code is proportional to the sum of the charges sampled during the conversion period. If each CIN is selected during OSR/G sampling_kAnd when a given CIN is selected_kThe average charge can be evaluated without selecting other capacitors. This is SG in FIG. 7_1...GIs done in the timing signal of (1). Such average charge can be expressedShown as Q { (total charge per sample period)/OSR }. If the total charge (Q) sampled on the input capacitor_ktot＝2*C*e_k(VI + -VI-)) is replaced with an OSR/G sample, the result may be

Q＝2*C*(VI+-VI-)*Σ{(e_k)/G}

In view of this resulting charge, the gain error resulting from using the timing diagram of FIG. 7 compared to an ideal gain of 1 will be equal to

GERR＝Σ{(e_k)/G-1}，

Which is equal to the gain error calculated by applying the timing diagram of fig. 6 to sampling circuit 401, but where the timing diagram of fig. 7 uses gain 1 instead of gain G as used in the timing diagram of fig. 6.

Thus, the timing diagram of FIG. 7 may be used with signals at a differential input that is as large as VREF. This can be performed without greater inaccuracy due to saturation of the ADC 203, since the voltage is too large for the defined input voltage range. When the effective gain is 1, the range of the converter is [ -VREF, + VREF ]. Thus, when + VREF is applied to the VIN input of ADC 203, and when the control signals of the timing diagram of fig. 7 are used on sampling circuit 401 by control block 402, the gain error is substantially the same as when the control signals of the timing diagram of fig. 6 are applied. The converter code output resulting from the timing diagram of fig. 7 is equivalent to the converter code output when the ADC gain is G and its input is + FS (which may be defined as + VREF/G). Gain error calibration may then be performed on gain G using the timing diagram of fig. 7 without applying a different input voltage, as long as the conversion includes OSR sampling and the OSR is a multiple of G.

Since VREF may be applied at the input of ADC 203 for any given gain G (as long as G is a divisor of OSR), and since the timing diagram of fig. 7 results in a gain error for ADC 203 while achieving an effective gain of 1, gain calibration may be performed on gains G1... Gm in any given order without adding settling time at the input of ADC 203. Therefore, the calibration process for all selected gains G1... Gm may be faster. The control logic 207 may be configured to iterate through all available selectable gain settings G1... Gm of the ADC 203 to evaluate the gain error for each such gain setting.

In the timing diagram of fig. 7, SGs may be enabled in any order_1...GA signal. This may be caused by the sampling circuit 401 averaging the stored charge. Any such order may be used, as long as for each given sample, the SG_1...GOnly one of the signals enables the switching of the corresponding capacitor while all signals disable the switching of the other capacitors. And, as long as SG_1...GAny such order may be used with each of the signals enabling the switching of the respective capacitor for the same number of samples (equal to OSR/G). The sampling order does not change the effective gain of the conversion, which remains equal to 1.

Embodiments of the present disclosure may not require any additional voltage source other than VREF to perform gain error calibration for different gain values. Embodiments of the present disclosure may not require the VREF to be generated accurately. VREF is applied to both inputs of the delta-sigma analog loop circuit 403, so the solution to determine the gain error can be said to be ratiometric. Moreover, embodiments of the present disclosure may not require a precision voltage source or device to measure the gain error. Embodiments of the present disclosure may utilize any available dc voltage with sufficiently low noise as VREF. It may not be necessary to generate an accurate VREF/G value as in the methods used to test gain errors in other solutions. Furthermore, since VREF is used as the VIN input during calibration, any noise or other non-idealities caused by the generation of VREF may be eliminated by the ratio measurement. Further, calibration can be performed without waiting for a settling time of the input between transitions.

Once the gain error for a given gain value is determined, the ADC 203 may be configured to take any suitable corrective action. For example, the ADC 203 may be configured to selectively apply the compensation signal to future measurements made at a given gain value during the normal operation phase.

Fig. 8 illustrates an example method 800 for determining a ratiometric gain error of an ADC having a capacitive gain input stage according to an embodiment of the disclosure. Method 800 may include more or fewer steps than shown in fig. 8. Moreover, the various steps of the method 800 may be omitted, repeated, performed in parallel, performed in a different order, or performed recursively. Method 800 may be implemented by the elements of fig. 2-5 using the timing diagram shown in fig. 7. In particular, the method 800 may be performed directly or indirectly by the control logic 207.

At step 805, it may be determined whether to operate the ADC in the normal phase or the calibration phase. If the ADC is to be operated in the normal phase, the method 800 may proceed to step 810. Otherwise, the method 800 may proceed to step 815.

At step 810, the gain to be used in the ADC may be determined. A gain may be applied to the input voltage to be converted to a digital value. After applying the gain, the input voltage may be converted within a range defined by a reference voltage range of the ADC. The ADC may output a digital code based on the input voltage. The method 800 may proceed to step 850.

At step 815, different possible gain settings for the ADC may be determined. Further, a reference voltage of the ADC may be applied to the ADC voltage input.

At step 820, untested ADC gain settings may be selected for testing. A set of capacitor pairs to be used for the selected ADC gain setting may be determined.

At step 825, a subset of the capacitor pairs, such as a single capacitor pair, may be enabled. The capacitor pair may be enabled for a time long enough to capture a large number of samples, defined by the sampling period divided by the gain. When a capacitor pair is enabled, the other capacitors may be disabled. At the end of the sampling period, the result may be integrated.

At step 830, it may be determined whether there are additional unsampled capacitor pairs from the set of capacitor pairs determined in step 820. If so, method 800 may repeat, for example, at step 825. Otherwise, the method 800 may proceed to step 835.

At step 835, a gain error may be determined from the integration result of the selected gain setting. At step 840, gain error correction values for the gains may be set for future operations in the normal phase.

At step 845, it may be determined whether there are additional gain settings that are untested. If so, method 800 may repeat, for example, at step 820. Otherwise, the method 800 may proceed to step 850.

At step 850, it may be determined whether the method 800 is to be repeated. The method 800 may be repeated based on any suitable criteria, such as whether a larger device or system in which the ADC is implemented has commanded the ADC to continue operating or stop. If the method 800 is to be repeated, the method 800 may repeat, for example, at step 805. Otherwise, the method 800 may proceed to step 855.

The present disclosure has been described in terms of one or more embodiments, and it is to be understood that many equivalents, alternatives, variations, and modifications, in addition to those expressly stated, are possible and are within the scope of the present disclosure. While the disclosure is susceptible to various modifications and alternative forms, specific exemplary embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific exemplary embodiments is not intended to limit the disclosure to the particular forms disclosed herein.