阅读说明：本技术 用于ldo防倒灌的衬底切换电路 (Substrate switching circuit for preventing LDO backflow ) 是由 徐一宸 尹喜珍 于 2021-09-30 设计创作，主要内容包括：本发明提供了一种用于LDO防倒灌的衬底切换电路,包括：第一场效应管、第二场效应管、第三场效应管、第四场效应管、第五场效应管、第六场效应管、第七场效应管、第八场效应管、第一二极管、第二二极管、限流电阻以及双极结型晶体管；还包括比较器。本电路结构在主通路上不会产生额外的压降,不需要加入电荷泵带来的额外电容,可以将衬底切换的效果最大化,让功率管能够完全关断,同时仅采用两个高压管即可实现耐高压的性能。(The invention provides a substrate switching circuit for preventing LDO backflow, which comprises: the current limiting circuit comprises a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a first diode, a second diode, a current limiting resistor and a bipolar junction transistor; a comparator is also included. This circuit structure can not produce extra pressure drop on the main route, need not add the extra electric capacity that the charge pump brought, can be with the effect maximize that the substrate switched, let the power tube turn-off completely, only adopt two high-voltage tube to realize high pressure resistant performance simultaneously.)

1. A substrate switching circuit for LDO back-flow prevention, comprising: a first field effect transistor (P1), a second field effect transistor (P2), a third field effect transistor (P3), a fourth field effect transistor (P4), a fifth field effect transistor (N1), a sixth field effect transistor (N2), a seventh field effect transistor (N3), an eighth field effect transistor (N4), a first diode (D1), a second diode (D2), a current limiting resistor (R0) and a bipolar junction transistor (B1);

the drain of the first field effect transistor (P1) forms a VIN end, the source of the first field effect transistor (P1) is respectively connected with the source of the second field effect transistor (P2), the anode of the first diode (D1), the anode of the second diode (D2), the source of the third field effect transistor (P3), the source of the fourth field effect transistor (P4) and one end of the current limiting resistor (R0), the gate of the first field effect transistor (P1) is respectively connected with the cathode of the first diode (D1), the drain of the third field effect transistor (P3), the gate of the fourth field effect transistor (P4) and the drain of the fifth field effect transistor (N1), the drain of the second field effect transistor (P2) forms a VBAT end, the gate of the second field effect transistor (P2) is respectively connected with the cathode of the second diode (D2), the drain of the fourth field effect transistor (P4), the gate of the third field effect transistor (P3) and the sixth field effect transistor (P2) of the sixth field effect transistor (P3), one end of the current limiting resistor (R0) forms a VCC end; the grid of the fifth field effect transistor (N1) is respectively connected with the other end of the current-limiting resistor (R0), the grid of the sixth field effect transistor (N2) and the emitter of the bipolar junction transistor (B1), the source of the fifth field effect transistor (N1) is connected with the drain of the seventh field effect transistor (N3), the source of the sixth field effect transistor (N2) is connected with the drain of the eighth field effect transistor (N4), the grid of the seventh field effect transistor (N3) forms an S1 end, the source of the seventh field effect transistor (N3) is respectively connected with the collector of the bipolar junction transistor (B1) and the source of the eighth field effect transistor (N4), the source of the seventh field effect transistor (N3) is grounded, the base of the bipolar junction transistor (B1) is connected with the collector, and the grid of the eighth field effect transistor (N4) forms an S2 end;

the hysteresis comparator outputs signals of the magnitude relation between the VIN end and the VBAT end to the S1 end and the S2 end, the positive pole of the hysteresis comparator is connected with the VIN end, and the negative pole of the hysteresis comparator is connected with the VBAT end.

2. The substrate switching circuit for LDO backflow prevention according to claim 1, wherein: the first field-effect tube (P1), the second field-effect tube (P2), the third field-effect tube (P3) and the fourth field-effect tube (P4) are all PMOS tubes, and the fifth field-effect tube (N1), the sixth field-effect tube (N2), the seventh field-effect tube (N3) and the eighth field-effect tube (N4) are all NMOS tubes.

3. The substrate switching circuit for LDO backflow prevention according to claim 1, wherein: the first field effect transistor (P1) and the second field effect transistor (P2) are both high-voltage MOS transistors.

4. The substrate switching circuit for LDO backflow prevention according to claim 1, wherein: when VIN is larger than VBAT, S1 obtains high level, and S2 obtains low level; when VIN is smaller than VBAT, S1 gets low, and S2 gets high.

5. The substrate switching circuit for LDO backflow prevention according to claim 1, wherein: when the voltage of the VIN end and the VBAT end exceeds the maximum bearing voltage of the hysteresis comparator, the VIN end and the VBAT end are respectively divided and then input into the hysteresis comparator, or a source input comparator is adopted to replace the hysteresis comparator, and the VIN end and the VBAT end are directly input into the source input comparator.

6. The utility model provides a high-pressure substrate switches chip for LDO prevents flowing backward which characterized in that: the substrate switching circuit for LDO backflow prevention, comprising any one of claims 1 to 5.

Technical Field

The invention relates to the field of power management chips, in particular to a substrate switching circuit for preventing LDO backflow, and especially relates to a high-voltage substrate switching circuit for preventing LDO backflow.

Background

In the operation of the power management chip, when the charger is under-voltage or not connected, the discharging module of the chip still needs to work normally, but the battery current may flow backwards. It is necessary to perform substrate switching and turn off the linear charging module when necessary. And because of the influence of high voltage, even if a high-voltage MOS tube is adopted, Vgs of the high-voltage MOS tube is still limited, and the typical process is 5V, so that how to achieve the ideal substrate switching effect under high voltage is a technical difficulty.

Referring to fig. 1, VIN is connected to the battery through a power PMOSFET, and the gate is controlled by the linear charging module. When VIN is not connected, the VIN is generally pulled to ground potential, or when VIN voltage is low, the battery may leak to VIN or ground through a body diode of the power tube, thereby causing large power consumption and damaging the battery.

There are three main approaches to this problem, the first is to add diodes or back-to-back power tubes in the charging path to prevent the battery current from flowing backwards. However, this method will generate a larger voltage drop, and thus has a higher requirement for the turn-on resistance of the power transistor. The second method is to use an NMOS power transistor, but also introduces a new problem that the linear charging control module needs a higher VDD to drive the gate of the power transistor, i.e. a charge pump is needed, and a large capacitor or an external component is introduced. The third solution is to use ordinary substrate switching, as shown in fig. 2, to get a higher intermediate potential to the substrate of the power transistor by using two opposite diodes or MOSFET body diodes, and when VIN is not connected or is low, the substrate potential is provided by VBAT to prevent the current from flowing backwards. There is still a problem that the substrate potential always has a difference of a diode drop from VBAT or VIN, and if the size of the power transistor is very large and the turn-on voltage is very small, a large leakage current still occurs, and this problem is not solved essentially.

Nanjing micro alliance electronics Inc. proposes a backflow prevention protection circuit of an LDO linear voltage regulator, as shown in FIG. 3, but the structure does not have the function of high voltage (more than 5v, such as 28v on a vehicle). Because Bo is approximately equal to max [ VIN, VOUT ], when VIN is inputted with a high voltage, Bo is also high, and Bo is simultaneously high as P3, P4, when the P3 gate signal is low, the high of Bo will pass to the gate of N6, thereby making Vgs of N6 too large.

A transistor substrate switching circuit has also been proposed by shanghai, inc, for electronics, as shown IN fig. 4, although the structure is simple and clear, and the number of transistors used is small, but the substrate switching circuit also has no function of withstanding high voltage, such as the transistor M3, when the IN1 is connected to high voltage, Vgb is also high voltage, which may break down the gate, and there is a limit to the difference between IN1 and IN2, because when IN1> IN2, IN1-IN2 is Vgs 3. In a typical process, Vgs has no capability to withstand high voltage.

The seiko electrical appliances limited also proposes a low power consumption PMOS transistor substrate switching circuit with voltage isolation, as shown in fig. 5. This structure also has a low voltage difference and achieves a certain degree of withstand voltage depending on the ratio of the resistances, as in PM 2: vsg is Vspad- (Vspad-Vcc-Vth (PM 1)). R2/R1. However, for high voltage conditions, it is still not sufficient, for example, when Vcc is high, Vsg of PM1 is Vspad-Vcc, and when Vcc is too large, Vgs of PM1 will break down.

As shown in fig. 6, the novel LDO anti-backflow current circuit provided by the brilliant core semiconductor also has the problem that it cannot withstand high voltage (the principle is the same as the structure provided by the mikyo alliance), and two resistors R4 and R5 are added to generate a smaller voltage drop, thereby increasing the difference between Vbulk and Vin.

Disclosure of Invention

In view of the defects in the prior art, the present invention is directed to a substrate switching circuit for preventing backflow of LDO.

The invention provides a substrate switching circuit for preventing LDO (low dropout regulator) from flowing backwards, which comprises: the current limiting circuit comprises a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a first diode, a second diode, a current limiting resistor and a bipolar junction transistor;

the source electrode of the first field effect tube is connected with the source electrode of the second field effect tube, the anode of the first diode, the anode of the second diode, the source electrode of the third field effect tube, the source electrode of the fourth field effect tube and one end of a current limiting resistor respectively, the grid electrode of the first field effect tube is connected with the cathode of the first diode, the drain electrode of the third field effect tube, the grid electrode of the fourth field effect tube and the drain electrode of the fifth field effect tube respectively, the drain electrode of the second field effect tube forms a VBAT end, the grid electrode of the second field effect tube is connected with the cathode of the second diode, the drain electrode of the fourth field effect tube, the grid electrode of the third field effect tube and the drain electrode of the sixth field effect tube respectively, and one end of the current limiting resistor forms a VCC end; the grid electrode of the fifth field effect transistor is connected with the other end of the current-limiting resistor, the grid electrode of the sixth field effect transistor and the emitter electrode of the bipolar junction transistor respectively, the source electrode of the fifth field effect transistor is connected with the drain electrode of the seventh field effect transistor, the source electrode of the sixth field effect transistor is connected with the drain electrode of the eighth field effect transistor, the grid electrode of the seventh field effect transistor forms an S1 end, the source electrode of the seventh field effect transistor is connected with the collector electrode of the bipolar junction transistor and the source electrode of the eighth field effect transistor respectively, the source electrode of the seventh field effect transistor is grounded, the base electrode of the bipolar junction transistor is connected with the collector electrode, and the grid electrode of the eighth field effect transistor forms an S2 end;

the hysteresis comparator outputs signals of the magnitude relation between the VIN end and the VBAT end to the S1 end and the S2 end, the positive pole of the hysteresis comparator is connected with the VIN end, and the negative pole of the hysteresis comparator is connected with the VBAT end.

Preferably, the first field effect transistor, the second field effect transistor, the third field effect transistor and the fourth field effect transistor are PMOS transistors, and the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the eighth field effect transistor are NMOS transistors.

Preferably, the first field effect transistor and the second field effect transistor are both high-voltage MOS transistors.

Preferably, when VIN > VBAT, S1 gets high level, and S2 gets low level; when VIN is smaller than VBAT, S1 gets low, and S2 gets high.

Preferably, when the voltage at the VIN terminal and the VBAT terminal exceeds the maximum withstand voltage of the hysteresis comparator, the VIN terminal and the VBAT terminal are respectively divided and then input into the hysteresis comparator, or the source input comparator is adopted to replace the hysteresis comparator, and the VIN terminal and the VBAT terminal are directly input into the source input comparator.

The invention provides a high-voltage substrate switching chip for preventing LDO backflow, which comprises the substrate switching circuit for preventing LDO backflow.

Compared with the prior art, the invention has the following beneficial effects:

1. the circuit structure does not generate extra voltage drop on the main path.

2. The circuit structure does not need to add extra capacitance brought by a charge pump.

3. The circuit structure can maximize the effect of substrate switching, enables the power tube to be completely turned off, and has high-voltage resistance.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a circuit diagram of a prior art solution;

FIG. 2 is a circuit diagram employing a substrate switching scheme;

FIG. 3 is a circuit diagram of a backflow prevention protection circuit of an LDO linear regulator in the prior art;

FIG. 4 is a circuit diagram of a prior art transistor substrate switching circuit;

FIG. 5 is a circuit diagram of a prior art substrate switching circuit of a low power consumption PMOS transistor with voltage isolation;

FIG. 6 is a circuit diagram of a novel LDO anti-back-flow current circuit in the prior art;

FIG. 7 is a circuit diagram of a substrate switch for LDO backflow prevention according to an embodiment of the present application.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

A substrate switching circuit for LDO backflow prevention, referring to fig. 7, comprising: the current limiting circuit comprises a first field effect transistor P1, a second field effect transistor P2, a third field effect transistor P3, a fourth field effect transistor P4, a fifth field effect transistor N1, a sixth field effect transistor N2, a seventh field effect transistor N3, an eighth field effect transistor N4, a first diode D1, a second diode D2, a current limiting resistor R0 and a bipolar junction transistor B1.

The drain electrode of the first field effect transistor P1 forms a VIN end, the source electrode of the first field effect transistor P1 is respectively connected with the source electrode of the second field effect transistor P2, the anode of the first diode D1, the anode of the second diode D2, the source electrode of the third field effect transistor P3, the source electrode of the fourth field effect transistor P4 and one end of the current-limiting resistor R0, the grid electrode of the first field effect transistor P1 is respectively connected with the cathode of the first diode D1, the drain electrode of the third field effect transistor P3, the grid electrode of the fourth field effect transistor P4 and the drain electrode of the fifth field effect transistor N1, the drain electrode of the second field effect transistor P2 forms a VBAT end, the grid electrode of the second field effect transistor P2 is respectively connected with the cathode of the second diode D2, the drain electrode of the fourth field effect transistor P4, the grid electrode of the third field effect transistor P3 and the drain electrode of the sixth field effect transistor N2, one end of the current-limiting resistor R0 forms a VCC end, and VCC is the output of the substrate switching circuit and provides the substrate potential of the power tube on the main path. The grid of the fifth field effect transistor N1 is connected to the other end of the current-limiting resistor R0, the grid of the sixth field effect transistor N2 and the emitter of the bjt B1, the source of the fifth field effect transistor N1 is connected to the drain of the seventh field effect transistor N3, the source of the sixth field effect transistor N2 is connected to the drain of the eighth field effect transistor N4, the grid of the seventh field effect transistor N3 forms the S1 terminal, the source of the seventh field effect transistor N3 is connected to the collector of the bjt B1 and the source of the eighth field effect transistor N4, the source of the seventh field effect transistor N3 is grounded, the base of the bjt B1 is connected to the collector, and the grid of the eighth field effect transistor N4 forms the S2 terminal.

The voltage-withstanding circuit also comprises a hysteresis comparator, in order to realize the voltage-withstanding function, a source input comparator can be adopted, or VIN and VBAT are subjected to differential comparison after being subjected to proportional voltage division, the comparator outputs signals of the magnitude relation between the VIN end and the VBAT end to the S1 end and the S2 end, the positive electrode of the comparator is connected with the VIN end, and the negative electrode of the comparator is connected with the VBAT end. VCC is the output of the substrate switching circuit and provides the substrate potential for the power transistor in the main path.

VCC is connected to the gates of the fifth FET N1 and the sixth FET N2 through a current limiting resistor R0. The gate potentials of the fifth fet N1 and the sixth fet N2 are clamped by the bjt B1 and are stabilized at a lower level, and the sub-threshold conduction occurs when the sources of the fifth fet N1 and the sixth fet N2 are pulled to ground.

First, a hysteresis comparator can divide the voltage of VIN and VBAT and then input the VIN and the VBAT, and a common comparator with source input can be adopted to output a signal indicating the magnitude relation of VIN and VBAT.

When VIN is normally turned on, VIN > VBAT, S1 gets high level, the seventh fet N3 is turned on, the source of the fifth fet N1 is pulled to a lower potential, the fifth fet N1 is turned on at sub-threshold to pull down the gate potential of the fourth fet P4, i.e., Vgs is increased, and the fourth fet P4 is turned on linearly to make the gate potential of the second fet P2 equal to VCC. At this time, Vgs of the second fet P2 is substantially 0, and the second fet P2 is turned off. And the body diode direction of the second field effect transistor P2 is from VBAT to VCC, and VCC is larger than or equal to VBAT, and can not be conducted. Meanwhile, the gate of the fourth fet P4 is also the gate of the first fet P1, and when the potential at this point is pulled low, the | Vgs1| -VCC-Vg 1 of the first fet P1 becomes large, so that the first fet P1 enters a linear region, VCC rises, Vgs becomes larger, positive feedback is formed, and | -Vgs 1| further increases, and maximum VCC is obtained. I.e. the voltage drop of the body diode is eliminated.

On the other hand, when VIN is not accessed, is pulled down to ground or VIN < VBAT, S1 is low and S2 is high. The eighth field effect transistor N4 is turned on, the source of the sixth field effect transistor N2 is pulled to a low potential, and the sixth field effect transistor N2 is turned on at a sub-threshold value to pull down the gate potential of the third field effect transistor P3, so that the third field effect transistor P3 is linearly turned on, and the gate potential of the first field effect transistor P1 is equal to VCC. At this time, Vgs of the first fet P1 is substantially 0, and the first fet P1 is turned off. And the diode direction of the first field effect transistor P1 is from VIN to VCC, and VCC is more than or equal to VIN, and can not be conducted. Meanwhile, the gate of the third fet P3 is also the gate of the second fet P2, and when the potential at this point is pulled low, the | Vgs2| -VCC-Vg 2 of the second fet P2 becomes large, so that the second fet P2 enters the linear region, VCC increases, positive feedback is formed, and | Vgs2| further increases, and maximum VCC is obtained. The voltage drop of the other side body diode is also eliminated.

In particular, the gate potentials of the third fet P3 and the fourth fet P4 are not pulled down to the ground by the seventh fet N3 and the eighth fet N4, but are only about 1v lower than the potentials when the seventh fet N3 and the eighth fet N4 are turned off, because the gate voltages of the fifth fet N1 and the sixth fet N2 are limited to a very low potential by the current limiting resistor Ro, i.e., the current is limited, and is not pulled to 0 only at the order of tens of nanoamperes. Meanwhile, due to the existence of the first diode D1 and the second diode D2, Vgs of the first field-effect transistor P1 and the second field-effect transistor P2 are further limited, and D1 and D2 can be diode strings to adapt to the limitation of Vgs of PMOS devices in different processes, so that the function of high voltage resistance is achieved. Meanwhile, the current limiting resistor R0 is used as a current limiting resistor, the resistance is large, a high-voltage resistant resistor is needed to bear most of voltage drop, and the current is limited, so that the potential reaching the grid electrode of the fifth field effect transistor N1 and the potential reaching the grid electrode of the sixth field effect transistor N2 are slightly lower than the threshold voltage of the fifth field effect transistor N1 and the sixth field effect transistor N2.

Therefore, except for the first fet P1 and the second fet P2, high voltage transistors may be used, and deep n-well low voltage MOS transistors may be used, but the breakdown voltage between DNWELL and PSUB needs to be high enough to enable the circuit to safely operate at high voltage.

According to the invention, through a special substrate switching module, when the VIN terminal voltage is lower than VBAT, the substrate terminal of the power tube is switched to the highest potential, and the difference between the VIN terminal voltage and the VBAT is only millivolt level, so that the current backflow is prevented, and the battery power consumption is reduced. The core design principle of substrate switching is to make the difference between the high voltage VCC and max { VIN, VBAT } as small as possible. At the same time, Vds of each pipe needs to be satisfied within a reasonable range. VIN is connected to BAT through two back-to-back PMOSs, the intermediate potential is VCC, but there is still a diode drop between max { VIN, VBAT }, thus adding the third FET P3 and the fourth FET P4. The respective gate voltages of the third field-effect transistor P3 and the fourth field-effect transistor P4 can change along with VCC by conducting the third field-effect transistor P3 and the fourth field-effect transistor P4, and if VCC is low, the gates of the third field-effect transistor P3 and the fourth field-effect transistor P4 are respectively reduced under respective judgment conditions, so that Vgs is improved, positive feedback is formed, and the highest VCC effect is obtained. Meanwhile, due to the existence of the first diode D1 and the second diode D2, Vgs of two tubes is limited, and the same function can be kept under high voltage.

The voltage environment for the present switching circuit depends on two factors, first: the maximum value of Vds which can be borne by the first field-effect tube P1 and the second field-effect tube P2 is Vdsmax; secondly, the method comprises the following steps: the breakdown voltage between the dnwell and the psub of the two deep n-well transistors P3 and P4, i.e., bvdnwell psub, is min { Vdsmax, bvdnwell psub }.

Typical processes for BVdnwellpsub are typically 40-50V, generally higher than Vdsmax. The common high-voltage scenario is the vehicle charging situation, where Vds may reach 28v-30v, so that in this situation, only the first fet P1 and the second fet P2 with Vds exceeding 30v are generally selected.

The embodiment further provides a high-voltage substrate switching chip for preventing the LDO from flowing backwards, which comprises the substrate switching circuit for preventing the LDO from flowing backwards, and therefore, the description is omitted.

Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, units provided by the present invention as pure computer readable program code, the system and its various devices, modules, units provided by the present invention can be fully implemented by logically programming method steps in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units included in the system for realizing various functions can also be regarded as structures in the hardware component; means, modules, units for performing the various functions may also be regarded as structures within both software modules and hardware components for performing the method.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.