阅读说明：本技术 一种输出缓冲器和源极驱动器 (Output buffer and source driver ) 是由 钟汶林 于 2020-07-03 设计创作，主要内容包括：本申请公开了一种输出缓冲器和源极驱动器,该输出缓冲器包括前置驱动电路、输出级电路、第一栅极驱动增强电路和第二栅极驱动增强电路；前置驱动电路包括第一或门和第一与门；输出级电路包括第一P型晶体管和第一N型晶体管,第一P型晶体管的栅极VPG通过第一栅极驱动增强电路与第一或门的输出端连接,第一栅极驱动增强电路用于向第一P型晶体管的栅极VPG增加过驱动电压以增强第一P型晶体管的驱动能力；第一N型晶体管的栅极VNG通过第二栅极驱动增强电路与第一与门的输出端连接,第二栅极驱动增强电路用于向第一N型晶体管的栅极VNG增加过驱动电压以增强第一N型晶体管的驱动能力。上述方案,能够增强输出级的驱动能力。(The application discloses an output buffer and a source driver, wherein the output buffer comprises a pre-drive circuit, an output stage circuit, a first grid drive enhancement circuit and a second grid drive enhancement circuit; the front driving circuit comprises a first OR gate and a first AND gate; the output stage circuit comprises a first P-type transistor and a first N-type transistor, wherein a grid electrode VPG of the first P-type transistor is connected with the output end of the first OR gate through a first grid electrode driving enhancement circuit, and the first grid electrode driving enhancement circuit is used for increasing an overdrive voltage to the grid electrode VPG of the first P-type transistor so as to enhance the driving capability of the first P-type transistor; the gate VNG of the first N-type transistor is connected to the output terminal of the first and gate through a second gate drive enhancement circuit, and the second gate drive enhancement circuit is configured to increase an overdrive voltage to the gate VNG of the first N-type transistor to enhance the driving capability of the first N-type transistor. According to the scheme, the driving capability of the output stage can be enhanced.)

1. An output buffer is characterized by comprising a pre-drive circuit, an output stage circuit, a first grid drive enhancement circuit and a second grid drive enhancement circuit;

the front driving circuit comprises a first OR gate and a first AND gate;

the output stage circuit comprises a first P-type transistor and a first N-type transistor; the grid electrode VPG of the first P-type transistor is connected with the output end of the first OR gate through the first grid electrode driving enhancement circuit, and the first grid electrode driving enhancement circuit is used for increasing an overdrive voltage to the grid electrode VPG of the first P-type transistor so as to enhance the driving capability of the first P-type transistor; the gate VNG of the first N-type transistor is connected to the output terminal of the first and gate through the second gate drive enhancement circuit, and the second gate drive enhancement circuit is configured to increase an overdrive voltage to the gate VNG of the first N-type transistor to enhance a driving capability of the first N-type transistor.

2. The output buffer of claim 1,

the first grid drive enhancement circuit comprises a third inverter, a fourth inverter, a second P-type transistor, a third P-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor and a first boosting capacitor;

the third inverter, the fourth inverter and the first boost capacitor are sequentially connected in series, and the input end of the third inverter is connected with the output end of the first OR gate;

a source electrode of the second P-type transistor is connected with a VDDIO interface, a drain electrode of the second P-type transistor is connected with a drain electrode of the second N-type transistor, and a grid electrode of the second P-type transistor and a grid electrode of the second N-type transistor are respectively connected with an output end of the third inverter;

the third P-type transistor, the fourth N-type transistor and the third N-type transistor are sequentially connected in series, the grid electrode of the third N-type transistor is connected with the drain electrode of the second P-type transistor, and the source electrode of the second N-type transistor and one end, far away from the fourth phase inverter, of the first boosting capacitor are respectively connected to the drain electrode of the third N-type transistor.

3. The output buffer of claim 2,

the capacitance value of the first boosting capacitor is larger than the first grid parasitic capacitance of the first P-type transistor.

4. The output buffer of claim 1,

the second grid drive enhancement circuit comprises a fifth inverter, a sixth inverter, a fourth P-type transistor, a fifth P-type transistor, a sixth P-type transistor, a fifth N-type transistor, a sixth N-type transistor and a second boosting capacitor;

the fifth inverter, the sixth inverter and the second boost capacitor are sequentially connected in series, and the input end of the fifth inverter is connected with the output end of the first AND gate;

a source electrode of the sixth N-type transistor is connected with a VSSIO interface, a drain electrode of the sixth N-type transistor is connected with a drain electrode of the sixth P-type transistor, and a grid electrode of the sixth N-type transistor and a grid electrode of the sixth P-type transistor are respectively connected with an output end of the fifth inverter;

the fourth P-type transistor, the fifth P-type transistor and the fifth N-type transistor are sequentially connected in series, the grid electrode of the fourth P-type transistor is connected with the drain electrode of the sixth N-type transistor, and the source electrode of the sixth P-type transistor and one end, far away from the sixth inverter, of the second boost capacitor are respectively connected to the drain electrode of the fourth P-type transistor.

5. The output buffer of claim 4,

the capacitance value of the second boosting capacitor is larger than the second grid parasitic capacitance of the first N-type transistor.

6. The output buffer of claim 1, further comprising:

the control circuit of the enhancement circuit is used for respectively controlling the working states of the first gate drive enhancement circuit and the second gate drive enhancement circuit according to the voltage value of the VDDIO interface so as to adjust the magnitude of the overdrive voltage provided for the gate VPG of the first P-type transistor and/or the gate VNG of the first N-type transistor.

7. The output buffer of claim 6,

the control circuit of the enhancement circuit comprises a control bus and a VDDIO voltage detection circuit, the VDDIO voltage detection circuit is used for detecting the voltage value of the VDDIO interface, and the control bus is used for outputting a control signal according to the voltage value of the VDDIO interface so as to control the working states of the first grid driving enhancement circuit and the second grid driving enhancement circuit.

8. The output buffer of claim 6,

the voltage value of the VDDIO interface is not more than half of the nominal voltage of the first P-type transistor or the first N-type transistor;

the control circuit of the enhancement circuit comprises a digital register and a control bus, wherein the digital register is used for controlling the control bus to output a control signal so as to control the working states of the first grid driving enhancement circuit and the second grid driving enhancement circuit.

9. The output buffer of claim 7 or 8,

the first gate drive enhancement circuit further comprises a control bit VPEN, a control bit VPCB0, a control bit VPCB1, a control bit VPCB 2;

the control signals respectively control the control bit VPEN, the control bit VPCB0, the control bit VPCB1 and the control bit VPCB2 to control the working state of the first gate driving enhancement circuit.

10. The output buffer of claim 7 or 8,

the second gate drive enhancement circuit further comprises a control bit VNEN, a control bit VNCB0, a control bit VNCB1, a control bit VNCB 2;

the control signals respectively control the control bit VNEN, the control bit VNCB2, the control bit VNCB1, and the control bit VNCB0 to control the operating state of the second gate drive enhancement circuit.

Technical Field

The present disclosure relates to circuit technologies, and in particular, to an output buffer and a source driver.

Background

The output buffer generally comprises a first P-type transistor and a first N-type transistor, wherein, during operation, the first P-type transistor and the first N-type transistor are used for charging and discharging a capacitive load Cload of the output stage, and at the moment, the first P-type transistor and the first N-type transistor are respectively equivalent to a first resistor and a second resistor, if the first resistor and the second resistor are large, the overturning process of charging and discharging the Cload is slow, and even the Cload is not enough to be overturned to the highest potential and the lowest potential under normal operating frequency, the first resistor and the second resistor represent the driving capability of the output buffer; because when output drive ability is not enough, the output buffer can't support the chip and work under rated operating frequency, at this moment, either strengthen output drive ability, or alleviate external capacitance load Cload.

However, Cload is often determined by the external working environment, and often cannot be adjusted, and only the output driving capability can be enhanced to solve the problem. The driving capability is related to the size of the first P-type transistor, the first N-type transistor and the operating voltage. For example, the larger the sizes of the first P-type transistor and the first N-type transistor are, the smaller the equivalent output resistance is, and the larger the driving capability is; however, increasing the sizes of the first P-type transistor and the first N-type transistor may increase the on-chip parasitic capacitance of the output stage, and if the sizes of the first P-type transistor and the first N-type transistor are simply increased, the area of the output stage may be very large, which increases the chip cost. For another example, the higher the operating voltage is, the higher the overdrive voltage of the first P-type transistor and the first N-type transistor is, the smaller the equivalent output resistance is, and the larger the driving capability is; however, the working voltage of the output stage is determined by the application of the chip, and even under some applications, in order to reduce power consumption, the chip is required to maintain high driving capability under an extremely low working voltage so as to push an external large capacitive load; for example, after a certain process is selected, devices used in an output stage are often fixed, for example, 5V devices are selected, but an application circuit requires that the output stage operates at a voltage of 3.3V or even 1.8V, a threshold voltage Vth of the devices is fixed, low voltage causes insufficient overdrive voltage of a gate of the output stage device, driving capability is very weak, and even the size of the output stage is increased, the requirements required by the application cannot be met.

Disclosure of Invention

The technical problem that this application mainly solved provides an output buffer and source driver, can strengthen the driving capability of output stage.

In order to solve the above problems, the present application provides an output buffer including a pre-driver circuit, an output stage circuit, a first gate drive enhancement circuit, and a second gate drive enhancement circuit; the front driving circuit comprises a first OR gate and a first AND gate; the output stage circuit comprises a first P-type transistor and a first N-type transistor; the grid electrode VPG of the first P-type transistor is connected with the output end of the first OR gate through the first grid electrode driving enhancement circuit, and the first grid electrode driving enhancement circuit is used for increasing an overdrive voltage to the grid electrode VPG of the first P-type transistor so as to enhance the driving capability of the first P-type transistor; the gate VNG of the first N-type transistor is connected to the output terminal of the first and gate through the second gate drive enhancement circuit, and the second gate drive enhancement circuit is configured to increase an overdrive voltage to the gate VNG of the first N-type transistor to enhance a driving capability of the first N-type transistor.

The invention has the beneficial effects that: different from the prior art, the output buffer of the application comprises a pre-drive circuit and an output stage circuit; the front driving circuit comprises a first OR gate and a first AND gate; the output stage circuit comprises a first P-type transistor and a first N-type transistor; the grid electrode VPG of the first P-type transistor is connected with the output end of the first OR gate through a first grid electrode driving enhancement circuit, and the first grid electrode driving enhancement circuit is used for increasing an overdrive voltage to the grid electrode VPG of the first P-type transistor so as to enhance the driving capability of the first P-type transistor; the gate VNG of the first N-type transistor is connected to the output terminal of the first and gate through a second gate drive enhancement circuit, and the second gate drive enhancement circuit is configured to increase an overdrive voltage to the gate VNG of the first N-type transistor to enhance the driving capability of the first N-type transistor. The first gate drive boosting circuit supplies an overdrive voltage to the gate VPG of the first P-type transistor, and the second gate drive boosting circuit boosts the overdrive voltage to the gate VNG of the first N-type transistor, so that the overdrive voltage of the output stage can be enhanced, and the drive capability of the output stage is enhanced on the premise that the sizes of the first P-type transistor and the first N-type transistor are not increased.

Drawings

FIG. 1 is a schematic diagram of a first embodiment of an output buffer according to the present application;

FIG. 2a is an equivalent schematic diagram of the output stage circuit 12 in the output buffer of FIG. 1;

FIG. 2b is a diagram illustrating the output driving capability of the output buffer and the output waveform;

FIG. 3 is a schematic diagram of an embodiment of a first gate drive enhancement circuit 14 in the output buffer of the present application;

FIG. 4 is a schematic diagram of an embodiment of a second gate drive enhancement circuit 16 in the output buffer of the present application;

FIG. 5 is a schematic diagram of the operation of the first gate drive enhancement circuit 14 of FIG. 3;

FIG. 6 is a schematic diagram of a second embodiment of an output buffer according to the present application;

FIG. 7 is a schematic diagram of a third embodiment of an output buffer according to the present application;

FIG. 8 is a schematic structural diagram of another embodiment of the first gate drive enhancement circuit 14 in the output buffer of the present application;

FIG. 9 is a schematic diagram of an embodiment of the tri-state inverter of FIG. 8;

FIG. 10 is a schematic diagram of another embodiment of the second gate drive enhancement circuit 16 in the output buffer of the present application;

fig. 11 is a schematic structural diagram of a fourth embodiment of the output buffer of the present application.

Detailed Description

The following describes in detail the embodiments of the present application with reference to the drawings attached hereto.

In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, interfaces, techniques, etc. in order to provide a thorough understanding of the present application.

The terms "system" and "network" are often used interchangeably herein. The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship. Further, the term "plurality" herein means two or more than two.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an output buffer according to a first embodiment of the present application. The output buffer of the present embodiment includes a pre-driver circuit 10 and an output stage circuit 12; the front-end driving circuit 10 comprises a first or gate 100 and a first and gate 102; the first or gate 100 receives the output enable signal OE through the first inverter 104, receives the output signal DATA through the second inverter 106, and outputs the logic control signal VP; the first and gate 102 receives the output enable signal OE, receives the output signal DATA through the second inverter 106, and outputs the logic control signal VN; the output stage circuit 12 includes a first P-type transistor 120 and a first N-type transistor 122, the source of the first P-type transistor 120 is connected to the VDDIO interface, the source of the first N-type transistor 122 is connected to the VSSIO interface, the drain of the first P-type transistor 120 and the drain of the first N-type transistor 122 are respectively connected to one end of an output stage load capacitor 124, and the other end of the output stage load capacitor 124 is grounded; the output buffer further comprises a first gate drive enhancement circuit 14 and a second gate drive enhancement circuit 16; the gate VPG of the first P-type transistor 120 is connected to the output terminal of the first or gate 100 through a first gate drive enhancement circuit 14, the first gate drive enhancement circuit 14 is configured to add an overdrive voltage to the gate VPG of the first P-type transistor 120 to enhance the driving capability of the first P-type transistor 120; the gate VNG of the first N-type transistor 122 is connected to the output terminal of the first and gate 102 through a second gate drive enhancement circuit 16, and the second gate drive enhancement circuit 16 is configured to add an overdrive voltage to the gate VNG of the first N-type transistor 122 to enhance the driving capability of the first N-type transistor 122.

It can be understood that the output signal DATA is DATA that needs to be output to the outside of the chip, and the output enable signal OE can control the output to become a high impedance state; the first P-type transistor 120 and the first N-type transistor 122 form a push-pull output buffer (push-pull output buffer), wherein the gate VPG of the first P-type transistor 120 is controlled by a first or gate 100, and the gate VNG of the first N-type transistor 122 is controlled by a first and gate 102; the output-stage load capacitor 124 may be composed of an on-chip parasitic capacitor, a package parasitic capacitor, a PCB trace parasitic capacitor, an input capacitor of an interactive chip, and the like. In operation, the first P-type transistor 120 and the first N-type transistor 122 can charge or discharge the output stage load capacitor 124, so that the signal seen at the output terminal after the output signal DATA passes through the output buffer can be inverted from 0 to 1 or from 1 to 0, where 0 represents low level, 1 represents high level, 0 is the potential of VSSIO interface, and 1 is the potential of VDDIO interface.

Referring to fig. 2a and fig. 2b, fig. 2a is a schematic diagram illustrating an equivalent principle of the output stage circuit 12 in the output buffer of fig. 1, and fig. 2b is a schematic diagram illustrating a relationship between the output driving capability and the output waveform of the output buffer. When the output-stage load capacitor 124 is charged and discharged, as shown in fig. 2a, the first P-type transistor 120 may be equivalent to a first resistor 1200, the first N-type transistor 122 may be equivalent to a second resistor 1220, and the charging and discharging time of the first P-type transistor 120 is determined by the time constant of the RC formed by the first resistor 1200, the second resistor 1220 and the output-stage load capacitor 124, if the equivalent resistances of the first P-type transistor 120 and the first N-type transistor 122 are large, the signal inversion process is slow, so the first resistor 1200 and the second resistor 1220 represent the driving capability of the output buffer; it is understood that the values of the first resistor 1200 and the second resistor 1220 may be equal or unequal, and the specific values of the first resistor 1200 and the second resistor 1220 need to be set according to different designs. Fig. 2b shows output waveforms of different output driving capacities of the output buffer, and in the top ideal output waveform, the resistance values of the first resistor 1200 and the second resistor 1220 are both 0, and the output driving capacity is infinite, but actually cannot be realized; actual output waveforms 1-4 represent the variation trend of the output waveforms when the output driving capability gradually weakens from strong: in the actual output waveform 1, the output driving capability has little influence on the output waveform, and the signal inversion is normal; in the actual output waveform 2, the rise and fall times of the output waveform have become significantly longer; in the actual output waveform 3, the output waveform can only just be inverted to the highest potential VDDIO and the lowest potential VSSIO; in the actual output waveform 4, the output waveform is further deteriorated, the signal is not enough to be inverted to the highest potential VDDIO and the lowest potential VSSIO at the normal operating frequency, and the output driving capability is obviously not enough to support the normal operation.

Therefore, in order to solve the problem of insufficient output driving capability of the output buffer under the standard operating voltage or even the extremely low operating voltage, the present application adds the first gate drive enhancement circuit 14 between the gate VPG of the first P-type transistor 120 and the output terminal of the first or gate 100, adds the second gate drive enhancement circuit 16 between the gate VNG of the first N-type transistor 122 and the output terminal of the first and gate 102, the first gate drive enhancement circuit 14 is used for adding the overdrive voltage to the gate VPG of the first P-type transistor 120, the overdrive voltage is provided to the gate VPG of the first P-type transistor 120 through the first gate drive enhancement circuit 14, and the overdrive voltage is added to the gate VNG of the first N-type transistor 122 through the second gate drive enhancement circuit 16, so that the overdrive voltage of the output stage can be enhanced, and further, without increasing the sizes of the first P-type transistor 120 and the first N-type transistor 122, The driving capability of the output stage is enhanced under the working voltage of 1/2 or even 1/4 of the standard working voltage of the used device, so that the output buffer realizes high driving capability and can drive large capacitive load.

Referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment of the first gate driving enhancement circuit 14 in the output buffer of the present application. In this embodiment, the first gate drive enhancement circuit 14 includes a third inverter 140, a fourth inverter 141, a second P-type transistor 142, a third P-type transistor 143, a second N-type transistor 144, a third N-type transistor 145, a fourth N-type transistor 146, and a first boost capacitor 147; the third inverter 140, the fourth inverter 141 and the first boost capacitor 147 are sequentially connected in series, and the input end of the third inverter 140 is connected to the output end of the first or gate 100; a source of the second P-type transistor 142 is connected to the VDDIO interface, a drain of the second P-type transistor 142 is connected to a drain of the second N-type transistor 144, and a gate of the second P-type transistor 142 and a gate of the second N-type transistor 144 are respectively connected to an output terminal of the third inverter 140; the third P-type transistor 143, the fourth N-type transistor 146 and the third N-type transistor 145 are sequentially connected in series, the source of the third P-type transistor 143 is connected to the VDDIO interface, the drain of the third P-type transistor 143 and the drain of the fourth N-type transistor 146 are respectively connected to the gate VPG of the first P-type transistor 120, the source of the fourth N-type transistor 146 is connected to the drain of the third N-type transistor 145, the source of the third N-type transistor 145 is connected to the VSSIO interface, the gate of the third N-type transistor 145 is connected to the drain of the second P-type transistor 142, the gate of the third P-type transistor 143 and the gate of the fourth N-type transistor 146 are respectively connected to the output terminal of the third inverter 140, and the source of the second N-type transistor 144 and the end of the first boost capacitor 147, which is far from the fourth inverter 141, are respectively connected to the drain of the third N-type transistor 145.

It is understood that when the logic control signal VP output by the first or gate 100 is 1, the output is 0 after passing through the third inverter 140, so that the second P-type transistor 142 and the third P-type transistor 143 are in an on state, and the second N-type transistor 144 and the fourth N-type transistor 146 are off; the second P-type transistor 142 can then pull the gate of the third N-type transistor 145 high, putting the third N-type transistor 145 in a conducting state, while the third P-type transistor 143 pulls the gate VPG of the first P-type transistor 120 in the output stage circuit 12 high, putting the first P-type transistor 120 off; meanwhile, the signal is output as 1 after passing through the fourth inverter 141, and since the third N-type transistor 145 is in a conducting state, one end of the first boost capacitor 147 is connected to the output terminal of the fourth inverter 141, and the other end is connected to the drain of the third N-type transistor 145, both ends of the first boost capacitor 147 are charged to have a voltage equal to VDDIO, and the potential of the node VFP is VSSIO. When the logic control signal VP output by the first or gate 100 is equal to 0, the output of the third inverter 140 is 1, such that the second P-type transistor 142 and the third P-type transistor 143 are turned off, and the second N-type transistor 144 and the fourth N-type transistor 146 are turned on, the turn-on of the second N-type transistor 144 may pull the gate of the third N-type transistor 145 to a low potential equal to the node VFP, and at this time, the third N-type transistor 145 is turned off; meanwhile, the output of the fourth inverter 141 is 0, and since the first boost capacitor 147 already stores the charge equal to the voltage of VDDIO, the node VFP becomes a negative voltage, and since the fourth N-type transistor 146 is turned on, the negative voltage of the node VFP directly drives the gate VPG of the first P-type transistor 120. It is understood that when it is required to turn on the first P-type transistor 120, the overdrive voltage can be provided to the first P-type transistor 120 by the negative voltage of the node VFP of the first gate drive enhancement circuit 14, so as to enhance the driving capability of the first P-type transistor 120.

Referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of a second gate driving enhancement circuit 16 in the output buffer of the present application. In this embodiment, the second gate drive enhancement circuit 16 includes a fifth inverter 160, a sixth inverter 161, a fourth P-type transistor 162, a fifth P-type transistor 163, a sixth P-type transistor 164, a fifth N-type transistor 165, a sixth N-type transistor 166, and a second boost capacitor 167; the fifth inverter 160, the sixth inverter 161 and the second boost capacitor 167 are sequentially connected in series, and the input end of the fifth inverter 160 is connected with the output end of the first and gate 102; the source of the sixth N-type transistor 166 is connected to the VSSIO interface, the drain of the sixth N-type transistor 166 is connected to the drain of the sixth P-type transistor 164, and the gate of the sixth N-type transistor 166 and the gate of the sixth P-type transistor 164 are connected to the output of the fifth inverter 160, respectively; the fourth P-type transistor 162, the fifth P-type transistor 163 and the fifth N-type transistor 165 are sequentially connected in series, the source of the fourth P-type transistor 162 is connected to the VDDIO interface, the drain of the fourth P-type transistor 162 is connected to the source of the fifth P-type transistor 163, the drain of the fifth P-type transistor 163 and the drain of the fifth N-type transistor 165 are respectively connected to the gate VNG of the first N-type transistor 122, the source of the fifth N-type transistor 165 is connected to the VSSIO interface, the gate of the fourth P-type transistor 162 is connected to the drain of the sixth N-type transistor 166, the gate of the fifth P-type transistor 163 and the gate of the fifth N-type transistor 165 are respectively connected to the output end of the fifth inverter 160, and the source of the sixth P-type transistor 164 and the end of the second boost capacitor 167, which is far away from the sixth inverter 161, are respectively connected to the drain of the fourth P-type transistor 162.

When the logic control signal VN output from the first and gate 102 is 0, the output is 1 after passing through the fifth inverter 160, so that the fifth N-type transistor 165 and the sixth N-type transistor 166 are in an on state, and the fifth P-type transistor 163 and the sixth P-type transistor 164 are off; thus, the sixth N-type transistor 166 may pull the gate of the fourth P-type transistor 162 to a low potential, so that the fourth P-type transistor 162 is in a conducting state, and the fifth N-type transistor 165 pulls the gate VNG of the first N-type transistor 122 in the output stage circuit 12 to a low potential, so that the first N-type transistor 122 is turned off; meanwhile, the signal is output as 0 after passing through the sixth inverter 161, since the fourth P-type transistor 162 is in a conducting state, one end of the second boost capacitor 167 is connected to the output end of the sixth inverter 161, and the other end is connected to the drain of the fourth P-type transistor 162, the two ends of the second boost capacitor 167 are charged, the voltage is equal to VDDIO, and the potential of the node VFN is VDDIO. When the logic control signal VN output by the first and gate 102 is equal to 1, the output of the fifth inverter 160 is 0, so that the fifth N-type transistor 165 and the sixth N-type transistor 166 are turned off, and the fifth P-type transistor 163 and the sixth P-type transistor 164 are turned on, the turn-on of the sixth P-type transistor 164 can pull the gate of the fourth P-type transistor 162 to a high potential equal to the node VFN, and at this time, the fourth P-type transistor 162 is turned off; meanwhile, the output of the sixth inverter 161 is 1, and since the second boost capacitor 167 has stored the charge equal to the VDDIO voltage, the voltage of the node VFN will be higher than the VDDIO voltage, and since the fifth P-type transistor 163 is turned on, the high voltage of the node VFN will directly drive the gate VNG of the first N-type transistor 122. It is understood that when it is required to turn on the first N-type transistor 122, the high voltage of the node VFN of the second gate drive enhancing circuit 16 can be provided to the first N-type transistor 122 for providing the overdrive voltage, so as to enhance the driving capability of the first N-type transistor 122.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating an operation principle of the first gate driving enhancement circuit 14 of fig. 3. Further, the capacitance of the first boost capacitor 147 is larger than the first gate parasitic capacitor 1201 of the first P-type transistor 120. It can be understood that, since the first gate parasitic capacitor 1201 exists at the gate VPG of the first P-type transistor 120, the charge at the two ends of the first boost capacitor 147 partially charges the first gate parasitic capacitor 1201, the negative voltage at the node VFP after stabilization does not reach VDDIO, but as long as the capacitance of the first boost capacitor 147 is large enough, the sufficient negative voltage at the gate VPG of the first P-type transistor 120 provides the sufficient overdrive voltage to the first P-type transistor 120, so as to enhance the driving capability of the first P-type transistor 120.

Likewise, the second gate drive enhancement circuit 16 operates in a similar manner to the first gate drive enhancement circuit 14. The capacitance of the second boost capacitor 167 is larger than the second gate parasitic capacitor (not shown) of the first N-type transistor 122, and since the second gate parasitic capacitor exists at the gate VNG of the first N-type transistor 122, a part of the charge at the two ends of the second boost capacitor 167 charges the second gate parasitic capacitor, the high voltage of the node VFN after stabilization does not reach 2 × VDDIO, but as long as the capacitance of the second boost capacitor 167 is large enough, the gate VNG of the first N-type transistor 122 has enough high voltage to provide enough overdrive voltage for the first N-type transistor 122, so as to enhance the driving capability of the first N-type transistor 122.

Referring to fig. 5, the first gate driving enhancement circuit 14 and the second gate driving enhancement circuit 16 work in a similar manner, and here, taking the first gate driving enhancement circuit 14 as an example, the first gate parasitic capacitance 1201 of the first P-type transistor 120 is shown in the figure, and the first gate parasitic capacitance 1201 equivalently includes all gate parasitic capacitances including the gate-source parasitic capacitance Cgs, the gate-drain parasitic capacitance Cgd, and the like. When the two ends of the first boost capacitor 147 are fully charged and the positive terminal of the first boost capacitor 147 is driven to a low potential by the output 0 of the fourth inverter 141, the negative terminal of the first boost capacitor 147 actually needs to charge the first gate parasitic capacitor 1201 to reach the negative potential, and since the current direction and the negative charge moving direction are opposite, the current direction flows from the first gate parasitic capacitor 1201 to the first boost capacitor 147 at this time, and the negative charge stored at the negative terminal of the first boost capacitor 147 goes to the negative terminal of the first gate parasitic capacitor 1201, so that the negative terminal potential of the first gate parasitic capacitor 1201 is pulled down, and the gate VPG of the first P-type transistor 120 can be changed to the negative potential. Further, the first boost capacitor 147 and the second boost capacitor 167 are collectively referred to by the boost capacitor Cb, and the first gate parasitic capacitor 1201 of the first P-type transistor 120 and the second gate parasitic capacitor of the first N-type transistor 122 are collectively referred to by the gate parasitic capacitor Cbar; before boosting, the two ends of the boost capacitor Cb are fully charged, the voltage is VDDIO, and at this time, no charge is stored at the two ends of the gate parasitic capacitor Cbar due to the equal potential, so that in the boosting process, the charge stored in the boost capacitor Cb and the gate parasitic capacitor Cbar are redistributed, the voltage at the two ends of the gate parasitic capacitor Cbar after the distribution is the gate-source voltage Vgs of the first P-type transistor 120 or the first N-type transistor 122, and since the gate-source voltages Vgs of the first P-type transistor 120 and the first N-type transistor 122 are respectively negative and positive when being turned on, the voltage at the two ends of the gate parasitic capacitor Cbar is recorded as the gate-source voltage | Vgs |; the magnitude of the gate-source voltage | Vgs | at this time is as shown in equation (1):

|Vgs|＝2*VDDIO*(Cb/(Cb+Cbar)) (1)

it can be seen that when Cb > > Cpar, | Vgs | ≈ 2 ≈ VDDIO, therefore, the application can enhance the overdrive voltage of the first P-type transistor 120 and the first N-type transistor 122 of the output stage circuit 12 by two times through the action of the first gate driving enhancement circuit 14 and the second gate driving enhancement circuit 16, so that the driving capability of the first P-type transistor 120 and the first N-type transistor 122 can be enhanced.

Referring to fig. 6, fig. 6 is a schematic structural diagram of an output buffer according to a second embodiment of the present application. The difference from the previous embodiment is that the output buffer of the present embodiment further includes a control circuit 18 of the enhancement circuit, and the control circuit 18 of the enhancement circuit is configured to control the operation states of the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16 according to the voltage value of the VDDIO interface, so as to adjust the magnitude of the overdrive voltage provided to the gate VPG of the first P-type transistor 120 and/or the gate VNG of the first N-type transistor 122; wherein the absolute value of the gate-source voltage Vgs of the first P-type transistor 120 and the first N-type transistor 122 does not exceed the nominal voltage of the first P-type transistor 120 or the first N-type transistor 122. It will be appreciated that the overdrive voltage of the first P-type transistor 120 and the first N-type transistor 122 of the output stage circuit 12 can be enhanced due to the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16, and when the gate-source voltage exceeds the nominal operating voltage, the gate-source may be damaged due to overvoltage. Therefore, the present embodiment can adjust the magnitude of the overdrive voltage provided to the gate VPG of the first P-type transistor 120 and/or the gate VNG of the first N-type transistor 122 by providing the control circuit 18 of the enhancement circuit, so that the absolute value of the gate-source voltage Vgs of the first P-type transistor 120 and the first N-type transistor 122 does not exceed the nominal voltage of the first P-type transistor 120 or the first N-type transistor 122, thereby enhancing the driving capability, ensuring that no gate-source overvoltage of the first P-type transistor 120 and the first N-type transistor 122 of the output stage circuit 12 occurs, and ensuring the reliability of the output buffer.

As an implementation manner, as shown in fig. 7, fig. 7 is a schematic structural diagram of a third embodiment of the output buffer of the present application, please refer to fig. 6, a control circuit 18 of the enhancement circuit includes a control bus 180 and a VDDIO voltage detection circuit 181, the VDDIO voltage detection circuit 181 is used for detecting a voltage value of the VDDIO interface, and the control bus 180 is used for outputting a control signal according to the voltage value of the VDDIO interface to control the operation states of the first gate driving enhancement circuit 14 and the second gate driving enhancement circuit 16. It can be understood from the above formula (1), that the overdrive voltage of the first P-type transistor 120 and the first N-type transistor 122 of the output stage circuit 12 can be boosted to twice the voltage value of the VDDIO interface by the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16, and therefore, the absolute value of the gate-source voltage Vgs of the first P-type transistor 120 and the first N-type transistor 122 of the output stage circuit 12 can be prevented from exceeding the nominal voltage of the first P-type transistor 120 or the first N-type transistor 122 by detecting the voltage value of the VDDIO interface and then controlling the operation state of the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16 according to the voltage value of the VDDIO interface.

Further, referring to fig. 8, fig. 8 is a schematic structural diagram of another embodiment of the first gate driving enhancement circuit 14 in the output buffer of the present application. The first gate driving enhancement circuit 14 in this embodiment further includes a control bit VPEN, a control bit VPCB0, a control bit VPCB1, a control bit VPCB 2; the control signals output by the control bus control the control bit VPEN, the control bit VPCB0, the control bit VPCB1, and the control bit VPCB2, respectively, to control the operating state of the first gate driver enhancement circuit 14. The control signal can control whether the first gate drive enhancement circuit 14 is in the boost operation mode or not through the control bit VPEN, the control bit VPCB0, the control bit VPCB1, and the control bit VPCB2, and control a specific boost range when the first gate drive enhancement circuit 14 is in the boost operation mode, so that the driving capability of the output stage circuit 12 can be specifically adjusted.

Specifically, the first gate drive enhancement circuit 14 includes a control bit VPEN, a control bit VPCB0, a control bit VPCB1, a control bit VPCB2, and a second and gate 148; the fourth inverter 141 specifically includes a first tri-state inverter 1411, a second tri-state inverter 1412, and a third tri-state inverter 1413; the first boost capacitor 147 specifically includes a first sub-capacitor 1471, a second sub-capacitor 1472, and a third sub-capacitor 1473; the second and gate 148 is connected to the control bit VPEN, the second and gate 148 receives the logic control signal VP through the third inverter 140, and the gate of the second P-type transistor 142 and the gate of the second N-type transistor 144 are respectively connected to the output terminal of the second and gate 148; the first tri-state inverter 1411 is connected in series with the first sub-capacitor 1471, the control bit VPCB0 is connected to the first tri-state inverter 1411, the input terminal of the first tri-state inverter 1411 is connected to the output terminal of the third inverter 140, and the end of the first sub-capacitor 1471 away from the first tri-state inverter 1411 is connected to the drain of the third N-type transistor 145; the second tri-state inverter 1412 is connected in series with the second sub-capacitor 1472, the control bit VPCB1 is connected to the second tri-state inverter 1412, the input terminal of the second tri-state inverter 1412 is connected to the output terminal of the third inverter 140, and the end of the second sub-capacitor 1472 away from the second tri-state inverter 1412 is connected to the drain of the third N-type transistor 145; the third tri-state inverter 1413 is connected in series with the third sub-capacitor 1473, the control bit VPCB2 is connected to the third tri-state inverter 1413, the input terminal of the third tri-state inverter 1413 is connected to the output terminal of the third inverter 140, and the end of the third sub-capacitor 1473 away from the third tri-state inverter 1413 is connected to the drain of the third N-type transistor 145. It can be understood that the first gate drive enhancement circuit 14 of the present embodiment has the control bit VPEN, the control bit VPCB0, the control bit VPCB1, the control bit VPCB2 and the second and gate 148 added thereto, and the fourth inverter 141 is extended to the first tri-state inverter 1411, the second tri-state inverter 1412 and the third tri-state inverter 1413, and the first boost capacitor 147 is extended to the first sub-capacitor 1471, the second sub-capacitor 1472 and the third sub-capacitor 1473, compared to the first gate drive enhancement circuit 14 of fig. 3. The control circuit 18 of the enhancement circuit controls the operating state of the first gate driving enhancement circuit 14 through the control bit VPEN, the control bit VPCB0, the control bit VPCB1 and the control bit VPCB2 to control the driving capability of the output stage circuit 12.

The first tri-state inverter 1411, the second tri-state inverter 1412 and the third tri-state inverter 1413 are all inverters with tri-state control. Referring to fig. 8 and 9, fig. 9 is a schematic structural diagram of an embodiment of the tri-state inverter in fig. 8, in which any one of the tri-state inverters in the present application includes a seventh P-type transistor 1001 and an eighth P-type transistor 1002 sequentially connected in series, a seventh N-type transistor 1003 and an eighth N-type transistor 1004, wherein the source of the seventh P-type transistor 1001 is connected to the VDDIO interface, the drain of the eighth P-type transistor 1002 is connected to the drain of the seventh N-type transistor 1003 and to the output OUT of the tristate inverter, respectively, the source of the seventh N-type transistor 1003 is connected to the drain of the eighth N-type transistor 1004, the source of the eighth N-type transistor 1004 is connected to the VSSIO interface, the gate of the seventh P-type transistor 1001 and the gate of the eighth N-type transistor 1004 are connected to the input IN of the tristate inverter, and the gate of the eighth P-type transistor 1002 and the gate of the seventh N-type transistor 1003 are connected to the input TENB of the tristate inverter, respectively. Specifically, the control bit VPCB0 is coupled to the input TENB of the first tri-state inverter 1411, the control bit VPCB1 is coupled to the input TENB of the second tri-state inverter 1412, and the control bit VPCB2 is coupled to the input TENB of the third tri-state inverter 1413; when the input TENB of a tri-state inverter is 0, the corresponding tri-state inverter operates like a normal inverter, and when the input TENB of a tri-state inverter is 1, the output OUT of the tri-state inverter is IN a high-impedance state regardless of whether the input IN of the tri-state inverter is 0 or 1.

Accordingly, the control circuit 18 of the boost circuit can control whether the first gate drive boost circuit 14 is in the boost operation mode by the control bit VPEN, and control the size of the first boost capacitor 147 by the control bits VPCB0, VPCB1, VPCB 2. For example, when the control bit VPEN is 1, the first gate drive enhancement circuit 14 is in the boost operation mode, and the capacitance of the first boost capacitor 147 can be controlled by the control bits VPCB0 to VPCB 2; when the control bit VPCB0 is 0 and the control bit VPCB1 is control bit VPCB2 is 1, the first tri-state inverter 1411 is equivalent to a common inverter, the first sub-capacitor 1471 operates as a boost capacitor, the outputs of the third tri-state inverter 1413 and the fourth tri-state inverter 1611 are in a high-impedance state, the positive terminals of the second sub-capacitor 1472 and the third sub-capacitor 1473 are floating and do not operate as boost capacitors, and the second sub-capacitor 1472 and the third sub-capacitor 1473 do not affect the operation of the circuit. Different values are configured through the control bits VPCB0-VPCB2, so that whether the first sub-capacitor 1471, the second sub-capacitor 1472 and the third sub-capacitor 1473 work as boosting capacitors can be controlled respectively, and the capacitance value of the first boosting capacitor 147 can be adjusted freely. When the control bit VPEN is equal to 0, the first gate driving enhancement circuit 14 is in the non-boosting operation mode, and at this time, the second and gate 148 outputs 0 due to the control bit VPEN being equal to 0, so that the second P-type transistor 142 is turned on, and then the gate of the third N-type transistor 145 is pulled to a high potential, so that the third N-type transistor 145 is also turned on; meanwhile, the control bits VPCB0-VPCB2 are all 1, so that the outputs of the first tri-state inverters 1411-TINV 1 are all in a high-impedance state, the positive terminals of the first sub-capacitor 1471, the second sub-capacitor 1472 and the third sub-capacitor 1473 are all floating, and the first sub-capacitor 1471, the second sub-capacitor 1472 and the third sub-capacitor 1473 do not affect the circuit operation; since the third N-type transistor 145 is turned on and the third P-type transistor 143 and the fourth N-type transistor 146 form an inverter structure, the logic control signal VP can reach the gate VPG of the first P-type transistor 120 through the third inverter 140 and the inverter structure formed by the third P-type transistor 143 and the fourth N-type transistor 146, that is, the logic control signal VP directly controls the gate VPG of the first P-type transistor 120.

Referring to fig. 7 and 8, in an application scenario, the nominal voltages of all the P-type transistors and N-type transistors are 5V; if the voltage value of VDDIO is 5V, the VDDIO voltage detection circuit 181 sets the control bit VPEN to 0 and the control bits VPCB0 to VPCB2 to 1 in the control bus 180, and at this time, the first gate driver enhancement circuit 14 is in the non-boost operation mode, so as to prevent the gate-source voltage of the first P-type transistor 120 of the output stage circuit 12 from being damaged due to overvoltage; if the voltage value of VDDIO is 4V, the VDDIO voltage detection circuit 181 may cause the control bus 180 to set the control bit VPEN to 1, the control bit VPCB0 to 0, and the control bit VPCB1 to VPCB2 to 1, where the first gate driver enhancement circuit 14 is in the boost operation mode, the first sub-capacitor 1471 operates as the boost capacitor, the first gate parasitic capacitor 1201 and the first sub-capacitor 1471 are precisely matched according to the above formula (1), and the gate-source voltage Vgs of the first P-type transistor 120 may exceed 4V but not exceed 5V, so that the gate VPG of the first P-type transistor 120 may be increased by the first gate driver enhancement circuit 14 without exceeding the nominal voltage of the device and being damaged; if the voltage value of VDDIO is 3V, the VDDIO voltage detection circuit 181 may cause the control bus 180 to set the control bit VPEN to 1, the control bit VPCB0 to VPCB1 to 0, and the control bit VPCB2 to 1, where the first gate driver enhancement circuit 14 is in the boost operation mode, the first sub-capacitor 1471 and the second sub-capacitor 1472 operate as boost capacitors, and the gate-source voltage Vgs of the first P-type transistor 120 may exceed 3V and not exceed 5V by performing precise matching on the first gate parasitic capacitor 1201, the first sub-capacitor 1471, and the second sub-capacitor 1472 according to the above formula (1), so that the gate-source voltage Vgs of the first P-type transistor 120 may exceed 3V and may not exceed 5V, and the gate VPG of the first P-type transistor 120 may be increased by the first gate driver enhancement circuit 14 and may not be damaged by exceeding the nominal voltage of the device; by analogy, the voltage value of VDDIO is detected by the VDDIO voltage detection circuit 181, and then the accurate calculation is performed by the formula (1), so that the first gate drive enhancement circuit 14 is in the boosting operation mode without damaging the circuit due to overvoltage, and the reliability of the output buffer is greatly improved.

Further, referring to fig. 10, fig. 10 is a schematic structural diagram of another embodiment of the second gate driving enhancement circuit 16 in the output buffer of the present application. The second gate driving enhancement circuit 16 in this embodiment further includes a control bit VNEN, a control bit VNCB0, a control bit VNCB1, a control bit VNCB 2; the control signals output by the control bus respectively control the control bit VNEN, the control bit VNCB2, the control bit VNCB1 and the control bit VNCB0 to control the operating state of the second gate driving enhancement circuit. The control signal may control whether the second gate drive enhancement circuit 16 is in the boost operation mode or not through the control bit VNEN, the control bit VNCB2, the control bit VNCB1, and the control bit VNCB0, and control a specific boost range when the second gate drive enhancement circuit 16 is in the boost operation mode, so that the driving capability of the output stage circuit 12 may be specifically adjusted.

Specifically, the second gate drive enhancement circuit 16 includes a control bit VNEN, a control bit VNCB0, a control bit VNCB1, a control bit VNCB2, a seventh inverter 168, and a second or gate 169; the sixth inverter 161 specifically includes a fourth tri-state inverter 1611, a fifth tri-state inverter 1612, and a sixth tri-state inverter 1613; the second boost capacitor 167 specifically includes a fourth sub-capacitor 1671, a fifth sub-capacitor 1672, and a sixth sub-capacitor 1673; the second or gate 169 is connected to the control bit VNEN through the seventh inverter 168, the second or gate 169 receives the logic control signal VN through the fifth inverter 160, and the gates of the sixth P-type transistor 164 and the sixth N-type transistor 166 are respectively connected to the output terminal of the second or gate 169; the fourth tri-state inverter 1611 is connected in series with the fourth sub-capacitor 1671, the control bit VPCB2 is connected to the fourth tri-state inverter 1611, the input terminal of the fourth tri-state inverter 1611 is connected to the output terminal of the fifth inverter 160, and the end of the fourth sub-capacitor 1671 far away from the fourth tri-state inverter 1611 is connected to the drain of the fourth P-type transistor 162; the fifth tri-state inverter 1612 is connected in series with the fifth sub-capacitor 1672, the control bit VPCB1 is connected to the fifth tri-state inverter 1612, the input terminal of the fifth tri-state inverter 1612 is connected to the output terminal of the fifth inverter 160, and the end of the fifth sub-capacitor 1672 far away from the fifth tri-state inverter 1612 is connected to the drain of the fourth P-type transistor 162; the sixth tri-state inverter 1613 is connected in series with the sixth sub-capacitor 1673, the control bit VPCB0 is connected to the sixth tri-state inverter 1613, the input terminal of the sixth tri-state inverter 1613 is connected to the output terminal of the fifth inverter 160, and the end of the sixth sub-capacitor 1673 remote from the sixth tri-state inverter 1613 is connected to the drain of the fourth P-type transistor 162. It is understood that the second gate drive enhancement circuit 16 of the present embodiment has the control bit VNEN, the control bit VNCB0, the control bit VNCB1, the control bit VNCB2 and the second or gate 169 added thereto, and expands the sixth inverter 161 into the fourth tri-state inverter 1611, the fifth tri-state inverter 1612 and the sixth tri-state inverter 1613, and expands the second boost capacitor 167 into the fourth sub-capacitor 1671, the fifth sub-capacitor 1672 and the sixth sub-capacitor 1673, compared with the second gate drive enhancement circuit 16 of fig. 4. The control circuit 18 of the enhancement circuit controls the operating state of the second gate driving enhancement circuit 16 through the control bit VNEN, the control bit VNCB0, the control bit VNCB1, and the control bit VNCB2 to control the driving capability of the output stage circuit 12.

The structure and function of the fourth tri-state inverter 1611, the fifth tri-state inverter 1612 and the sixth tri-state inverter 1613 are shown in fig. 9.

Accordingly, the control circuit 18 of the boost circuit may control whether the second gate drive boost circuit 16 is in the boost operation mode by the control bit VNEN, and control the size of the second boost capacitor 167 by the control bits VNCB0, VNCB1, and VNCB 2. Similar to the control manner of the second gate drive enhancement circuit 16, when the control bit VNEN is equal to 1, the second gate drive enhancement circuit 16 is in the boost operation mode, and the capacitance of the second boost capacitor 167 can be controlled by the control bits VNCB0 to VNCB 2; when the control bit VNEN is equal to 0, the second gate drive enhancement circuit 16 is in the non-boosting operation mode, and the control bits VNCB0 through VNCB2 are all 1. The specific operation principle is similar to that of the first gate driving enhancement circuit 14, and is not described herein again.

It is understood that, in the above embodiments, the control bits VPCB0-VPCB2 or VNCB0-VNCB2 are used as three-bit control bits, and in practical applications, the number of bits of the control bits may be set as required to accurately control the values of the first boost capacitor 147 or the second boost capacitor 167.

As an implementation manner, as shown in fig. 11, fig. 11 is a schematic structural diagram of a fourth embodiment of the output buffer of the present application, and a voltage value of the VDDIO interface does not exceed half of a nominal voltage of the first P-type transistor 120 or the first N-type transistor 122; the control circuit 18 of the enhancement circuit includes a digital register (not shown) for controlling the control bus 180 to output a control signal to control the operating states of the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16, and a control bus 180. It can be understood that, since it is determined that the voltage value of the VDDIO interface does not exceed half of the nominal voltage of the first P-type transistor 120 or the first N-type transistor 122, even if the overdrive voltage of the first P-type transistor 120 and the first N-type transistor 122 of the output stage circuit 12 is boosted to twice the voltage value of the VDDIO interface by the action of the first gate drive enhancement circuit 14 and the second gate drive enhancement circuit 16, the absolute value of the gate-source voltage Vgs of the first P-type transistor 120 and the first N-type transistor 122 does not exceed the nominal voltage of the first P-type transistor 120 or the first N-type transistor 122; therefore, the control bus 180 can be controlled by outputting the digital control signal VM through the digital register to adjust the driving capability of the output stage circuit 12, for example, the overdrive voltage can be adjusted through the control bus 180 to perform 2 times boosting, 1.8 times boosting, 1.5 times boosting and no boosting, so as to achieve the purpose of controlling the driving capability of the output stage circuit 12. For example, if the nominal voltage of all the first P-type transistors 120 or the first N-type transistors 122 is 5V, and the voltage value of the VDDIO interface is 1.8V, even if the overdrive voltage is increased to be twice the voltage value of the VDDIO interface, i.e., 3.6V, there is no risk of the gate-source overvoltage of the first P-type transistors 120 and the first N-type transistors 122 of the output stage circuit 12.

It can be understood that, in the output buffer in the third embodiment of the present application, after the voltage value of the VDDIO interface is detected by the VDDIO voltage detection circuit 181, the control bus 180 may respectively control the potentials of the control bit VPEN and the control bits VPCB0-VPCB2 to be 0 or 1, and further may respectively control whether the first sub-capacitor 1471, the second sub-capacitor 1472, and the third sub-capacitor 1473 operate as boost capacitors, and similarly, the control bus 180 may also respectively control the potentials of the control bit VNEN, the control bits VNCB0-VNCB2 to be 0 or 1, and further may respectively control whether the fourth sub-capacitor 1671, the fifth sub-capacitor 1672, and the sixth sub-capacitor 1673 operate as boost capacitors; therefore, the first sub-capacitor 1471, the second sub-capacitor 1472, and the third sub-capacitor 1473 may be combined to form a boost multiple actually required by the overdrive voltage, and the fourth sub-capacitor 1671, the fifth sub-capacitor 1672, and the sixth sub-capacitor 1673 may also be combined to form a boost multiple actually required by the overdrive voltage. The output buffer in the fourth embodiment of the present application stores the correspondence between the voltage value of the VDDIO interface and the potential of the control bit in the digital memory in advance, and when the output buffer is used, the voltage value of the VDDIO interface is automatically stored in the digital memory when the output buffer is powered on, so that the corresponding digital control logic can be found according to the correspondence between the voltage value of the VDDIO interface and the potential of the control bit and the voltage value of the VDDIO interface, and the boost multiple actually required by the overdrive voltage can be adjusted through the digital control logic, similar to a table look-up method. It can be found that the output buffer in the third embodiment of the present application needs to adjust the boost multiple actually required by the overdrive voltage according to the voltage value of the VDDIO interface detected by the VDDIO voltage detection circuit 181 each time, that is, the detection of the voltage value of the VDDIO interface needs to be performed once each time the driving capability of the output stage circuit 12 is adjusted, whereas the output buffer in the fourth embodiment of the present application does not need to detect the voltage value of the VDDIO interface each time the driving capability of the output stage circuit 12 is adjusted.

In the output buffer of the present application, the first gate drive enhancement circuit 14 supplies the overdrive voltage to the gate VPG of the first P-type transistor 120, and the second gate drive enhancement circuit 16 increases the overdrive voltage to the gate VNG of the first N-type transistor 122, so that the gate overdrive voltages of the first P-type transistor 120 and the first N-type transistor 122 of the output stage circuit 12 can be greatly enhanced, and even if the output buffer operates at 1/2 or 1/4, the output buffer can still provide high drive capability and can drive an external large capacitance load.

In the several embodiments provided in the present application, it should be understood that the disclosed output buffer may be implemented in other ways. For example, the above-described output buffer embodiments are merely illustrative, and for example, a division of modules or units is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.