阅读说明：本技术 一种fpga嵌入式管理系统、设计方法及介质 (FPGA embedded management system, design method and medium ) 是由 陳正川 于 2021-02-10 设计创作，主要内容包括：本发明公开了一种FPGA嵌入式管理系统,应用于服务器,包括：FPGA单元、电源模组和显示模块；FPGA单元分别与所述电源模组和所述显示模块连接；电源模组用于供电所述服务器；显示模块用于显示所述服务器的状态；FPGA单元中设有CPU、控制模块和存储模块；CPU用于读取并执行所述存储模块中代码；控制模块用于控制电源模组和显示模块；存储模块用于存储所述代码以及所述CPU产生的数据；通过上述方式,本发明能够充分利用FPGA内部资源,达到利用率最大化,进而节省零件成本,CPU易于实现基于Console Port的复杂控制及显示选单,且设计不会额外占用LE资源。(The invention discloses an FPGA embedded management system, which is applied to a server and comprises the following components: the system comprises an FPGA unit, a power supply module and a display module; the FPGA unit is respectively connected with the power supply module and the display module; the power supply module is used for supplying power to the server; the display module is used for displaying the state of the server; the FPGA unit is provided with a CPU, a control module and a storage module; the CPU is used for reading and executing the codes in the storage module; the control module is used for controlling the power supply module and the display module; the storage module is used for storing the codes and the data generated by the CPU; through the mode, the FPGA internal resource can be fully utilized, the utilization rate is maximized, the part cost is further saved, the CPU is easy to realize the Console Port-based complex control and display menu, and the LE resource is not additionally occupied by the design.)

1. The FPGA embedded management system is applied to a server and is characterized by comprising the following components: the system comprises an FPGA unit, a power supply module and a display module;

the FPGA unit is respectively connected with the power supply module and the display module;

the power supply module is used for supplying power to the server;

the display module is used for displaying the state of the server;

the FPGA unit is provided with a CPU, a control module and a storage module;

the CPU is used for reading and executing the program in the storage module;

the control module is used for controlling the power supply module and the display module;

the storage module is used for storing the program and the data generated by the CPU.

2. The FPGA embedded management system of claim 1, characterized in that: the power supply module is also used for sending a first power supply signal to the control module when the power supply module is normally started;

the power module comprises a plurality of power supplies.

3. The FPGA embedded management system of claim 2, characterized in that: the control module comprises a port control module, a power supply module control module and a display control module;

the FPGA unit is connected with the server through the port control module;

the power supply module control module is connected with the power supply module and is provided with a plurality of output interfaces and a plurality of input interfaces;

the power supply module control module sends a second power supply signal to the power supply module through the output interface, and controls the power supply module through the second power supply signal;

the display control module controls the display module through an output input pin.

4. The FPGA embedded management system of claim 3, characterized in that: the power module control module is also used for controlling the power-on sequence of the components in the server, controlling the delay time of the plurality of power supplies and monitoring whether the power module is normally started.

5. The FPGA embedded management system of claim 1, characterized in that: the storage module comprises a random storage module and a variable storage module;

the random storage module is used for storing data generated by the CPU, and the data in the random storage module is cleared when the power is off;

the variable storage module is used for storing a functional program, a hardware burning file and parameters of the server, and data in the variable storage module is not cleared when the power is off.

6. The FPGA embedded management system of claim 1, characterized in that: the CPU, the control module and the storage module in the FPGA unit are communicated through a parallel transmission protocol.

7. The design method of the FPGA embedded management system according to any one of claims 1 to 6, characterized by comprising the following steps:

establishing a control module and a storage module, setting starting addresses of the control module and the storage module, and designing a drive file through the starting addresses;

setting parameters of a control module and a storage module;

hardware synthesis is carried out, and the control module and the storage module are synthesized through a logic unit in the FPGA;

generating a hardware burning file and a design function program;

compiling the functional program, generating a format file, and burning the hardware burning file and the format file into the storage module.

8. The design method of the FPGA embedded management system according to claim 7, characterized in that: the step of setting the parameters of the control module and the storage module further comprises: the storage space of the storage module is set through developing software or hardware description language, the number of input and output pins in the CPU is set, and the baud rate of a port control module in the control module is set.

9. The design method of the FPGA embedded management system according to claim 7, characterized in that: the information in the hardware burning file comprises: the positions of the control module and the storage module in the FPGA and the layout of the routing in the FPGA.

10. A computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, carries out the steps of a method for designing an FPGA-embedded management system according to any one of claims 7 to 9.

Technical Field

The invention relates to the field of system design, in particular to an FPGA (field programmable gate array) embedded management system, a design method and a medium.

Background

FPGAs or CPLDs are often used for system and power management in server and memory applications, including power timing control, combinational logic applications, and other active components such as: communication of electronic components such as BMC, PCH, CPU, etc., control or collection of peripheral signals, control of fans, etc.

The design of the present FPGA or CPLD in such applications is implemented by using hardware (i.e. by using LE resources inside the element), but because there are fewer LE resources inside, the goal of FPGA design is to achieve the highest performance that can be achieved by the system with as little resource occupancy as possible. The more complex management is difficult to realize, such as Console Port, centralized management scheme and the like which support complex menu and command; besides LE, the interior of FPGA or CPLD also has many other resources that are relatively rarely used, such as: the Block RAM, the Flash Memory and the like are not applied in system management and power management, so that resource waste is caused.

Disclosure of Invention

The invention mainly solves the problems that the existing FPGA has less internal LE resources and cannot realize complex management functions.

In order to solve the technical problems, the invention adopts a technical scheme that: the FPGA embedded management system is applied to a server and comprises the following components: the system comprises an FPGA unit, a power supply module and a display module;

the FPGA unit is respectively connected with the power supply module and the display module;

the power supply module is used for supplying power to the server;

the display module is used for displaying the state of the server;

the FPGA unit is provided with a CPU, a control module and a storage module;

the CPU is used for reading and executing the program in the storage module;

the control module is used for controlling the power supply module and the display module;

the storage module is used for storing the program and the data generated by the CPU.

As a further improvement of the FPGA embedded management system of the present invention, the power module is further configured to send a first power signal to the control module when the power module is normally turned on;

the power module comprises a plurality of power supplies.

As a further improvement of the FPGA embedded management system, the control module comprises a port control module, a power supply module control module and a display control module;

the FPGA unit is connected with the server through the port control module;

the power supply module control module is connected with the power supply module and is provided with a plurality of output interfaces and a plurality of input interfaces;

the power supply module control module sends a second power supply signal to the power supply module through the output interface, and controls the power supply module through the second power supply signal;

the display control module controls the display module through an output input pin.

As a further improvement of the FPGA embedded management system of the present invention, the power module control module is further configured to control a power-on sequence of components in the server, to control a delay time of the plurality of power supplies, and to monitor whether the power module is normally turned on.

As a further improvement of the FPGA embedded management system, the storage module comprises a random storage module and a variable storage module;

the random storage module is used for storing data generated by the CPU, and the data in the random storage module is cleared when the power is off;

the variable storage module is used for storing a functional program, a hardware burning file and parameters of the server, and data in the variable storage module is not cleared when the power is off.

As a further improvement of the FPGA embedded management system, the CPU, the control module and the storage module in the FPGA unit are communicated through a parallel transmission protocol.

The invention further provides a design method of the FPGA embedded management system, which comprises the following steps:

establishing a control module and a storage module, setting starting addresses of the control module and the storage module, and designing a drive file through the starting addresses;

setting parameters of a control module and a storage module;

hardware synthesis is carried out, and the control module and the storage module are synthesized through a logic unit in the FPGA;

generating a hardware burning file and a design function program;

compiling the functional program, generating a format file, and burning the hardware burning file and the format file into the storage module.

Preferably, the step of setting the parameters of the control module and the storage module further comprises: the storage space of the storage module is set through developing software or hardware description language, the number of input and output pins in the CPU is set, and the baud rate of a port control module in the control module is set.

Preferably, the information in the hardware burning file includes: the positions of the control module and the storage module in the FPGA and the layout of the routing in the FPGA.

The invention also provides a computer readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the steps of the method of the FPGA embedded management system are realized.

The invention has the beneficial effects that:

1. the FPGA embedded management system can fully utilize the internal resources of the FPGA to achieve the maximum utilization rate, further save the part cost, and the CPU is easy to realize the complex control and display menu based on the Console Port and does not occupy extra LE resources in design.

2. According to the design method of the FPGA embedded management system, the starting address of each module is set, communication is carried out through the starting address, execution is convenient, efficiency is improved, complex functions are written into the variable storage module, LE resources are not occupied additionally, and the complex functions can be achieved.

3. The computer readable storage medium provided by the invention is controlled by using a programming language, so that each task can be managed conveniently, and the efficiency is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic diagram of an FPGA embedded management system architecture according to embodiment 1 of the present invention;

fig. 2 is a schematic diagram of control module and display module architectures in the FPGA embedded management system according to embodiment 1 of the present invention;

fig. 3 is a schematic diagram of a design method of an FPGA embedded management system according to embodiment 2 of the present invention;

fig. 4 is a program flowchart in the design method of the FPGA embedded management system according to embodiment 2 of the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

It is noted that in the description of the present invention

CPU (Central Processing Unit) is a central Processing unit;

a bmc (baseboard management controller) remote management controller, which is a baseboard management controller;

FPGA (field Programmable Gate array) is a field Programmable logic Gate array;

CPLD (Complex Programmable Logic device) is a complex Programmable Logic device used to realize various operations and combinational Logic;

LE ((Logic Element) is the minimum unit of the Logic unit, and is used for completing the minimum unit of the user Logic;

PCH (platform Controller hub) is a platform Controller;

console Port is a configuration Port, which is an interface type;

the Block RAM is a Block random access memory and is mainly applied to constructing a data cache, a deep FIFO, a buffer and the like;

flash Memory is a form of electrically erasable programmable read-only Memory that allows for multiple erases or writes during operation; the method is mainly used for general data storage and data exchange and transmission between the computer and other digital products.

ELF (executable and Linable Format) is a file used for binary files, executable files, object code, shared libraries and core dump formats.

The Avalon bus is an on-chip bus with a simpler protocol;

the Avalon Interface is a parallel transmission protocol defined by Intel;

UART (Universal Asynchronous Receiver/Transmitter) is a Universal Asynchronous Receiver/Transmitter that converts data to be transmitted between serial and parallel communications, and is usually integrated into the connections of other communication interfaces as a chip that converts parallel input signals into serial output signals.

Power Enable is an Enable input signal, and each group of Power supplies has an Enable input signal for turning on or turning off the Power supplies.

The Power Good signal is a signal which is output when the Power supply is started up and reaches a normal state.

In order to avoid the damage of the circuit caused by abnormal voltage, the power supply firstly checks whether the output voltage is normal, and if the output voltage is normal, a Powergood signal is output to the core component to start the core component.

The bottom layer driver is used for realizing man-machine interaction by a program in a mode of accessing bottom layer hardware, corresponding information interaction is required to be realized between the driver and an application program, on one hand, the application program sends a corresponding instruction to the driver to realize an action instruction controlled by the hardware, and on the other hand, the driver transmits the read-write state of the hardware and data obtained from the hardware to the application program to realize the interaction between the application program and the driver.

AUX is an auxiliary power supply, and is used for realizing a suspension mode of the system, and providing smaller current to quickly recover the working state when the display card stops working;

DDR Double Data Rate, in this embodiment, refers to the memory in the server.

FIFO (First Input First output) refers to FIFO memory in short.

Example 1

An embodiment of the present invention provides an FPGA embedded management system, which is applied to a server, and please refer to fig. 1 and fig. 2, where a hardware level includes: the system comprises an FPGA unit, a power supply module and a display module;

the power supply module is used for supplying power to the server;

the FPGA unit is respectively connected with the power supply module and the display module;

the FPGA unit is provided with a port control module, a random storage module, a power supply module control module, a CPU, a variable storage module and a display control module;

all modules in the FPGA are connected through a bus and communicate through different addresses among the modules;

particularly, the internal modules of the FPGA unit are communicated with each other through a parallel transmission protocol;

the interface externally connected with the port control module is a UART interface, and the FPGA unit is connected with the server through the UART interface;

the Power module control module comprises a Power module control module, a Power module control module and a Power module, wherein an external interface of the Power module control module is provided with a plurality of input interfaces and a plurality of output interfaces, the input interfaces are connected with the Power module, an input signal of Power Enable is sent to the Power module through the input interfaces to turn on or turn off the Power module, and when the Power module is correctly turned on, the Power module sends a Power Good signal to the Power module control module through the output interfaces;

the power supply module control module is used for controlling the power supply modules, and the number of the control power supply modules can be changed according to requirements;

the output and output interfaces are due to dozens of groups of power supplies, such as 3.3VAUX, 2.5VAUX, 1.5VAUX, 5V main power supply, 2.5V main power supply, 1.8V main power supply, DDR power supply, BMC power supply, CPU power supply, etc., applied to the server. The power module control module controls the power-on sequence of the components in the server according to the system requirements and controls the delay time between the power supplies. It will also monitor whether the Power supply is normally on (i.e., whether Power Good is equal to 1);

the display control module is used for controlling the display module to display a specific state through a parallel transmission protocol and an input/output pin;

the display module displays corresponding contents in different situations according to the system, for example:

and in the power-on and power-on stage, the display module displays the power-on progress.

And after the electrification is finished, the display module displays the electrification state.

And when the power supply is abnormal, the display module displays the abnormal category, so that convenience is brought to Debug.

And remote updating, wherein the display module displays the updating progress.

The above shows that the specific state is designed using C language in the present invention and is stored in the variable memory of the FPGA.

The random storage module is hardware carried in the FPGA, wherein the memory size of a memory of the random storage module depends on the software requirement of the FPGA, and the random storage module is communicated in the FPGA unit through a parallel transmission protocol;

the random storage module is used for storing data and is mainly used for storing temporary data generated by the CPU, and the temporary data generated by the CPU is lost when power is off;

the size of the RAM of the random access memory module is changed by designing firmware through the C language, when a large number of global variables are set in the C language, the space requirement of the RAM is very large, and if the rain fly variables are set in the C language, the RAM in the random access memory module can be repeatedly used, so that the effect of saving the RAM requirement amount is achieved;

the variable storage module is hardware in the FPGA and is used for storing codes for FPGA firmware design through C language and parameters of the server, and data are not cleared when power is off.

The parameters of the server include many, for example:

1. delay enabling time among the power modules;

2. an error feedback log;

the port control module, the random storage module, the power supply module control module, the variable storage module and the display control module are realized by designing FPGA firmware through C language by LE in FPGA.

Example 2

The embodiment of the present invention further provides a method for designing an FPGA embedded management system, please refer to fig. 3, which includes the following steps:

s100, establishing each module and a connection relation in the system, setting a starting address of each module in the management system according to the connection relation, and designing a bottom layer drive file through the starting address;

the communication between the CPU and each module in the system is carried out through the initial address of each module, so that each module in the system needs to have an independent and unrepeated address; therefore, each module in the system needs to be set with its own initial address;

for example, a 1024byte FIFO is set in the FPGA, and the start address of the FIFO is set, for example, the start address is 0x00008000, then the address of the FIFO is 0x00008000-0x000083FF, and the address cannot be used by other modules; so the starting address of the other modules is 0x 00008400;

this address can be set in a Verilog or VHDL file directly using a hardware description language;

in this embodiment, a method for designing an architecture of an FPGA is mainly described, if there are other newly added modules, only the new module is pulled in, addresses occupied by the modules are set, addresses of the modules are listed in a file by using a driver, and a corresponding API is designed, so that the C language can be directly called.

S300, setting parameters, namely setting the parameters of modules in the FPGA, for example, setting the storage space size of a random storage module and a variable storage module and the number of GPIO pins of a CPU; baud rate of the port control module, etc.; the parameter setting can be divided into two types, the first type is to call an IP address configured by a manufacturer and can be directly set in software of a development module, and the second type is to directly set parameters in Verilog through a module self-designed by a hardware description language;

after parameter setting is completed, hardware synthesis is carried out, all modules are synthesized through LE in the FPGA, Timing closure time sequence convergence is carried out after synthesis, the positions of all the modules in the FPGA and wiring design in the FPGA are designed through development software, and finally the design is put into a file to generate a hardware burning file.

The hardware burning file does not contain codes of firmware design.

S300, referring to fig. 4, code for designing FPGA firmware is performed: through C language design, the programs including management menu, power supply time sequence control and various function tasks are designed, and the function tasks can be increased or decreased according to different requirements.

The method comprises the following specific steps:

s401, initializing each module, waiting for 100 mus, and then printing initialization information; operating the power modules in sequence;

s402, judging whether the Power supply module outputs a Power Good signal or not, if not, turning off all Power supplies and printing error information, and if the Power Good signal is output, printing a main menu;

s403, whether a task in the main menu is selected or not is judged, and if the task is selected, the task is executed; if not, continuing to return to the main menu task;

the different function tasks comprise power supply electrifying program, port control module display and input identification, time function setting of power supply delay, display control, random storage module and variable storage module data access and the like.

S400, setting a starting position for reading a C language code in a CPU, setting a starting position for reading a code from a variable storage module by the CPU, wherein the code for FPGA firmware design in C language is stored in the variable storage module, and the position of the code read by the CPU needs to be pointed to the starting position, so that the CPU can be executed from the starting position of the code when executing;

and S500, compiling the program designed by the C language to generate an ELF file, burning the hardware burning file and the ELF file to the variable storage module, and finishing the design.

Based on the same inventive concept as the method in the foregoing embodiments, an embodiment of the present specification further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the design method of the FPGA embedded management system as disclosed in the foregoing are implemented.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, and a program that can be implemented by the hardware and can be instructed by the program to be executed by the relevant hardware may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic or optical disk, and the like.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.