阅读说明：本技术 一种测试方法及装置 (Test method and device ) 是由 陈广甸 范光龙 陈金星 于 2021-01-05 设计创作，主要内容包括：本发明提供一种测试方法及装置,用于测试3D NAND存储器中字线的可靠性,提供测试装置,测试装置包括：第一测试端和第二测试端,第一测试端将第奇数条字线的接触结构串联在一起,第二测试端将第偶数条字线的接触结构串联在一起,第奇数条字线和第偶数条字线相互平行,且相邻的字线之间存在间隔。由于第奇数条字线串联在一起,第偶数条字线串联在一起,若相邻的两条字线之间存在刻蚀穿通的情况,将使得所有的字线串联在一起,即第一测试端和第二测试端处于连接状态,若相邻的两条字线之间不存在刻蚀穿通的情况,第一测试端和第二测试端处于断开状态。因而,通过该测试方法可以直接线上测试字线之间的刻蚀穿通缺陷,提高检测效率。(The invention provides a test method and a test device, which are used for testing the reliability of word lines in a 3D NAND memory and provided with the test device, wherein the test device comprises the following components: the test circuit comprises a first test end and a second test end, wherein the first test end connects the contact structures of the odd word lines in series, the second test end connects the contact structures of the even word lines in series, the odd word lines and the even word lines are parallel to each other, and intervals exist between the adjacent word lines. Because the odd word lines are connected in series, and the even word lines are connected in series, if there is etching punch-through between two adjacent word lines, all the word lines are connected in series, that is, the first testing terminal and the second testing terminal are in a connected state, and if there is no etching punch-through between two adjacent word lines, the first testing terminal and the second testing terminal are in a disconnected state. Therefore, the etching punch-through defects between the word lines can be directly tested on the line by the testing method, and the detection efficiency is improved.)

1. A method for testing reliability of word lines in a 3D NAND memory, comprising:

providing a test device, the test device comprising: a first test terminal and a second test terminal;

the first testing end connects the contact structures of the odd-numbered word lines together in series, the second testing end connects the contact structures of the even-numbered word lines together in series, and the odd-numbered word lines and the even-numbered word lines are parallel to each other and have intervals between adjacent word lines;

and testing whether the first test end and the second test end are in a connection state.

2. The test method according to claim 1, wherein an ordering direction of the odd and even word lines is a direction perpendicular to a substrate in the 3D NAND memory, and an extending direction of the odd and even word lines is a direction extending along a core storage region or a direction extending along a dummy step region in the 3D NAND memory.

3. The method of testing of claim 1, wherein the first testing end comprises: a first metal line and a first pad, the second test end including: a second metal line and a second pad;

the first end of the first metal line connects the contact structures of the odd numbered word lines together in series, and the second end of the first metal line is connected with the first pad;

the first ends of the second metal lines connect the contact structures of the even number of word lines together in series, and the second ends of the second metal lines are connected with the second pads.

4. The method according to any one of claims 1 to 3, wherein the testing whether the first test terminal and the second test terminal are in a connected state comprises:

connecting the first test end with a first end of a voltmeter, and connecting the second test end with a second end of the voltmeter;

measuring, by the voltmeter, whether a voltage exists between the first test terminal and the second test terminal.

5. The method according to any one of claims 1 to 3, wherein the testing whether the first test terminal and the second test terminal are in a connected state comprises:

connecting a power supply and an ammeter between the first test end and the second test end;

and measuring whether current exists between the first test end and the second test end through the ammeter.

6. A test apparatus for testing reliability of a word line in a 3D NAND memory, comprising: a first test terminal and a second test terminal;

the first test end is used for connecting the contact structures of the odd-numbered word lines in series, and the second test end is used for connecting the contact structures of the even-numbered word lines in series;

the odd word lines and the even word lines are parallel to each other, and a space exists between adjacent word lines.

7. The test device as claimed in claim 6, wherein the odd and even word lines have a sorting direction perpendicular to the substrate in the 3D NAND memory, and the odd and even word lines have an extending direction along the core storage region or along the dummy step region in the 3D NAND memory.

8. The test device of claim 6, wherein the first test end comprises: a first metal line and a first pad, the second test end including: a second metal line and a second pad;

the first end of the first metal line connects the contact structures of the odd word lines together in series, and the second end of the first metal line is connected with the first pad;

the first ends of the second metal lines connect the contact structures of the even number of word lines together in series, and the second ends of the second metal lines are connected with the second pads.

9. The test device as claimed in any one of claims 6 to 8, wherein the contact structure is a contact hole filled with a metal material.

10. A test device as claimed in any one of claims 6 to 8, characterized in that the test device is located in a dicing lane between chips.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a test method and a test device.

Background

In a 3D NAND memory, the memory array may include a core (core) region and a staircase (SS) region. The step region is used for leading out a contact part of a control gate in each layer of the memory array and is used as a word line connection region. These control gates are used as word lines of the memory array to perform programming, erasing, reading, etc.

In the manufacturing process of the 3D NAND memory, contact holes are formed on all levels of stepped structures in the stepped region in an etching mode, and then contact parts are filled, so that control gates are led out. In the actual production process, it is not easy to realize that the contact hole just falls on the step structure, and there may be a defect of Punch Through (Punch Through).

The existing method for detecting the defect of etching punch-through is to detect the contact hole under the line by a nanoprobe (nanoprobe) method after the chip is manufactured, but the method has low efficiency.

Disclosure of Invention

In view of the above, the present invention provides a testing method and apparatus for improving the efficiency of detecting the punch-through defect of the contact hole etching.

In order to achieve the purpose, the invention has the following technical scheme:

a testing method for testing reliability of word lines in a 3D NAND memory, comprising:

providing a test device, the test device comprising: a first test terminal and a second test terminal;

the first testing end connects the contact structures of the odd-numbered word lines together in series, the second testing end connects the contact structures of the even-numbered word lines together in series, and the odd-numbered word lines and the even-numbered word lines are parallel to each other and have intervals between adjacent word lines;

and testing whether the first test end and the second test end are in a connection state.

Optionally, the sorting direction of the odd word lines and the even word lines is a direction perpendicular to the substrate in the 3D NAND memory, and the extending direction of the odd word lines and the even word lines is a direction extending along the core storage region or a direction extending along the dummy step region in the 3D NAND memory.

Optionally, the first testing end includes: a first metal line and a first pad, the second test end including: a second metal line and a second pad;

the first end of the first metal line connects the contact structures of the odd numbered word lines together in series, and the second end of the first metal line is connected with the first pad;

the first ends of the second metal lines connect the contact structures of the even number of word lines together in series, and the second ends of the second metal lines are connected with the second pads.

Optionally, the testing whether the first test end and the second test end are in a connected state includes:

connecting the first test end with a first end of a voltmeter, and connecting the second test end with a second end of the voltmeter;

measuring, by the voltmeter, whether a voltage exists between the first test terminal and the second test terminal.

Optionally, the testing whether the first test end and the second test end are in a connected state includes:

connecting a power supply and an ammeter between the first test end and the second test end;

and measuring whether current exists between the first test end and the second test end through the ammeter.

A test apparatus for testing reliability of word lines in a 3D NAND memory, comprising: a first test terminal and a second test terminal;

the first test end is used for connecting the contact structures of the odd-numbered word lines in series, and the second test end is used for connecting the contact structures of the even-numbered word lines in series;

the odd word lines and the even word lines are parallel to each other, and a space exists between adjacent word lines.

Optionally, the sorting direction of the odd word lines and the even word lines is a direction perpendicular to the substrate in the 3D NAND memory, and the extending direction of the odd word lines and the even word lines is a direction extending along the core storage region or a direction extending along the dummy step region in the 3D NAND memory.

Optionally, the first testing end includes: a first metal line and a first pad, the second test end including: a second metal line and a second pad;

the first end of the first metal line connects the contact structures of the odd word lines together in series, and the second end of the first metal line is connected with the first pad;

the first ends of the second metal lines connect the contact structures of the even number of word lines together in series, and the second ends of the second metal lines are connected with the second pads.

Optionally, the contact structure is a contact hole filled with a metal material.

Optionally, the testing device is located in a scribe line between the chips.

The test method provided by the embodiment of the invention is used for testing the reliability of the word line in the 3D NAND memory, and comprises the following steps: providing a test device, the test device comprising: the testing device comprises a first testing end and a second testing end, wherein the first testing end is used for connecting contact structures of odd-numbered word lines in series, the second testing end is used for connecting contact structures of even-numbered word lines in series, the odd-numbered word lines and the even-numbered word lines are parallel to each other, intervals exist between the adjacent word lines, and whether the first testing end and the second testing end are in a connection state or not is tested. Therefore, as the odd word lines are connected in series and the even word lines are connected in series, if the etching punch-through exists between two adjacent word lines, all the word lines are connected in series, namely the first testing end and the second testing end are in a connected state, and if the etching punch-through does not exist between two adjacent word lines, the first testing end and the second testing end are in a disconnected state. Therefore, the etching punch-through defects between the word lines can be directly tested on the line by the testing method, and the detection efficiency is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 shows a schematic perspective view of a 3D NAND memory;

FIG. 2 shows a schematic cross-sectional structure of a 3D NAND memory;

FIG. 3 shows a schematic diagram of a top view structure of a 3D NAND memory;

fig. 4 is a schematic structural diagram of a testing apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.

The existing method for detecting the defect of etching punch-through is to detect the contact hole under the line by a nanoprobe (nanoprobe) method after the chip is manufactured, but the method has low efficiency.

To this end, the embodiment of the present application provides a test method for testing reliability of a word line in a 3D NAND memory, including: providing a test device, the test device comprising: the testing device comprises a first testing end and a second testing end, wherein the first testing end is used for connecting contact structures of odd word lines in series, the second testing end is used for connecting contact structures of even word lines in series, the odd word lines and the even word lines are parallel to each other, and intervals exist between the adjacent word lines. Therefore, as the odd word lines are connected in series and the even word lines are connected in series, if the etching punch-through exists between two adjacent word lines, all the word lines are connected in series, namely the first testing end and the second testing end are in a connected state, and if the etching punch-through does not exist between two adjacent word lines, the first testing end and the second testing end are in a disconnected state. Therefore, the etching punch-through defects between the word lines can be directly tested on the line by the testing method, and the detection efficiency is improved.

In order to better understand the testing method provided by the embodiment of the present application, the related 3D NAND memory is first described.

In forming the 3D NAND memory, first, a stack layer 110 in which an insulating layer 102 and a sacrificial layer are alternately stacked is formed on a substrate 100, the insulating layer 102 may be, for example, silicon oxide, and the sacrificial layer may be silicon nitride. Stack layer 110 is then etched to form a trench hole in stack layer 110, which is used to form a memory structure. Specifically, the epitaxial structure 132 may be formed at the bottom of the channel hole by Selective Epitaxial Growth (SEG), and then the memory structure 130 may be formed on the epitaxial structure 132. The epitaxial structure 132 serves as a connection to the memory structure 130 and a support to the memory structure 130. The memory structure 130 includes a memory function layer and a channel layer, the memory function layer includes a blocking layer, a charge trapping layer and a tunneling layer, which are sequentially stacked, the blocking layer, the charge trapping layer and the tunneling layer may be specifically an ONO stack, that is, a stack of silicon oxide-silicon nitride-silicon oxide, and the channel layer may be a polysilicon layer. A fill layer of insulating material, such as silicon oxide, may also be formed between the channel layers. A contact plug 134 may also be formed on the channel structure 130 for extracting the channel structure. And then, etching the stacked layer 110 between the channel holes to form a gate line gap, and removing the sacrificial layer in the stacked layer 110 by using the gate line gap to form a hollow structure. And filling metal in the hollow structure to form a gate layer 104, thereby forming a stacked layer 110 in which the insulating layer 102 and the gate layer 104 are alternately stacked, as shown in fig. 1 and fig. 2, fig. 1 is a schematic perspective view of a 3D NAND memory, and fig. 2 is a schematic cross-sectional view of the 3D NAND memory. The greater the number of gate layers 104 in the stacked layers 110, the more memory cells included in the formed memory cell string, and the higher the integration of the device, the number of gate layers 104 may be, for example, 16, 32, 48, 64, 72, 96, 128, and the like. The stacked layer 110 includes a core storage region 1101 and a step region 1102, the core storage region 1101 is generally in a middle area of the stacked layer 110, the step region 1102 is generally around the core storage region 1101, steps on two sides of the core storage region 1101 in one direction are used for forming the gate contact 150, steps on two sides of the core storage region 1101 in the other direction are not used for forming a contact, and are pseudo steps, and fig. 3 is a schematic top view structure diagram of a 3D NAND memory, which is shown in fig. 3.

For convenience of description, the (3D) directions are respectively defined as a first axis X, a second axis Y and a third axis Z, where the first axis X and the second axis Y are two axes orthogonal in the plane of the surface of the substrate 100, the first axis X is an axis extending along the core storage region 1101, the axis extending from the core storage region 1101 is an axis of the core storage region 1101 extending to the step extending direction for forming the gate contact 150, the second axis is an axis extending along the dummy step, and the third axis Z is an axis perpendicular to the surface of the substrate 100, as shown in fig. 1. The step region 1102 is formed with a partition step, and the partition step is formed with steps in both the first axis X and the second axis Y directions, and it is understood that steps on both sides of the core storage region 1101 for forming the gate contact are formed with steps in both the first axis X direction and the second axis Y direction, then the step in the first axis X direction is formed with the gate contact 150, and the step in the second axis Y direction is formed with the gate contact 150. In the drawings of the embodiments of the present application, only the step structure on one side of the stacked layer 110 and a part of the core storage region connected to the step structure on the side are shown, that is, only the cross-sectional structures in the first axis X direction and the third axis Z direction are shown.

In order to detect the situation that the contact of a gate layer has etching punch-through, the embodiment of the application provides a testing method for testing the reliability of a word line in a 3D NAND memory, which includes:

providing a test device, the test device comprising: a first test terminal 10 and a second test terminal 20;

the first testing terminal 10 is used for connecting the contact structures 121 of the odd-numbered word lines 111 together in series, and the second testing terminal 20 is used for connecting the contact structures 122 of the even-numbered word lines 112 together in series;

the odd word line 111 and the even word line 112 are parallel to each other, and a space exists between adjacent word lines;

testing whether the first testing terminal 10 and the second testing terminal 20 are in a connected state.

In the embodiment of the present application, because the contact structures 121 of the odd-numbered word lines 111 are connected in series and the contact structures 122 of the even-numbered word lines 112 are connected in series in the testing apparatus, if the contact structures of two adjacent word lines have a situation of etching through, the contact structures of all the word lines are connected in series, and then the first testing terminal 10 and the second testing terminal 20 are in a connected state, and if the contact structures of two adjacent word lines do not have a situation of etching through, the first testing terminal 10 and the second testing terminal 20 are in a disconnected state. Therefore, whether there is an etching through between the contact structures of the word lines can be tested by testing the connection state of the first test terminal 10 and the second test terminal 20. Specifically, when the first test terminal 10 and the second test terminal 20 are in a connected state, there is an etching punch-through between the contact structures of the word lines, and when the first test terminal 10 and the second test terminal 20 are in an disconnected state, there is no etching punch-through between the contact structures of the word lines. Also, since the odd and even word lines are formed in synchronization with the word lines of the 3D NAND memory using the same process, the etch punch-through defect between the gate contacts is determined by the etch punch-through defect between the contact structures of the word lines.

The sorting direction of the odd and even word lines 111 and 112 is a direction perpendicular to the substrate in the 3D NAND memory, and the extending direction of the odd and even word lines 111 and 112 is a direction extending along the core storage region or a direction extending along the dummy step region in the 3D NAND memory. Specifically, steps are formed on the steps on the two sides of the core storage area in the first axis X direction and the second axis Y direction, a gate contact is formed on the step in the first axis X direction, and a gate contact is formed on the step in the second axis Y direction. When the situation that whether the etching punch-through exists in the gate contact in the first axis X direction needs to be tested, the word line structure can be designed according to the gate layer structure in the first axis X direction in the 3D NAND memory, so that the situation that whether the etching punch-through exists in the gate contact in the first axis X direction can be tested by using the testing device. When the situation that whether the gate contact in the second axis Y direction has the etching punch-through or not needs to be tested, the word line structure can be designed according to the gate layer structure in the 3D NAND memory in the second axis Y direction, so that the situation that whether the gate contact in the second axis Y direction has the etching punch-through or not can be tested according to the testing device.

The first test terminal 10 may include a first metal line 103 and a first pad 101, the second test terminal 20 includes a second metal line 203 and a second pad 201, and as shown in fig. 4, a first terminal of the first metal line 103 connects the contact structures 121 of the odd-numbered word lines 111 in series, a second terminal of the first metal line 103 is connected to the first pad 201, a first terminal of the second metal line 203 connects the contact structures 122 of the even-numbered word lines 112 in series, and a second terminal of the second metal line 203 is connected to the second pad 201.

In a specific application, the first test terminal 10 may be connected to a first terminal of a voltmeter, the second test terminal 20 may be connected to a second terminal of the voltmeter, whether a voltage exists between the first test terminal 10 and the second test terminal 20 is measured by the voltmeter, when a voltage exists between the first test terminal 10 and the second test terminal 20, it indicates that the first test terminal 10 and the second test terminal 20 are in a connected state, and when no voltage exists between the first test terminal 10 and the second test terminal 20, it indicates that the first test terminal 10 and the second test terminal 20 are in a disconnected state. Specifically, whether the first test terminal 10 and the second test terminal 20 have voltages is determined by whether the voltmeter has a number, and obviously, when the voltmeter has a number, it indicates that a voltage exists between the first test terminal 10 and the second test terminal 20, and when the voltmeter has no number, it indicates that a voltage does not exist between the first test terminal 10 and the second test terminal 20. In a specific embodiment, a first terminal of a voltmeter may be connected to the first pad 101 and a second terminal of the voltmeter may be connected to the second pad 201.

A power supply and an ammeter may be further connected between the first test terminal 10 and the second test terminal 20, and the ammeter is used to measure whether a current exists between the first test terminal 10 and the second test terminal 20, indicating that the first test terminal 10 and the second test terminal 20 are in a connected state when a current exists between the first test terminal 10 and the second test terminal 20, and indicating that the first test terminal 10 and the second test terminal 20 are in a disconnected state when no current exists between the first test terminal 10 and the second test terminal 20. Specifically, the state between the first test terminal 10 and the second test terminal 20 is judged by whether the ammeter has a number, when the ammeter has a number, it indicates that a current exists between the first test terminal 10 and the second test terminal 20, and when the ammeter does not have a number, it indicates that a current does not exist between the first test terminal 10 and the second test terminal 20.

In the above detailed description of a testing method provided in the present application, an embodiment of the present application provides a testing apparatus, shown in fig. 4, for testing reliability of a word line in a 3D NAND memory, including: a first test terminal 10 and a second test terminal 20;

the first testing terminal 10 is used for connecting the contact structures 121 of the odd-numbered word lines 111 together in series, and the second testing terminal 20 is used for connecting the contact structures 122 of the even-numbered word lines 112 together in series;

the odd word line 111 and the even word line 112 are parallel to each other, and there is a space between adjacent word lines.

It should be noted that, in the embodiment of the present application, the odd word line 111 and the even word line 112 are formed in synchronization with the word line of the 3D NAND memory by the same process, and the contact structure 112 of the odd word line 111 and the contact structure 122 of the even word line 112 are formed in synchronization with the word line contact of the 3D NAND memory by the same process. Therefore, in the test apparatus, the relative positional relationship between the odd word line 111 and the even word line 112 is the relative positional relationship between the odd gate layer and the even gate layer in the 3D NAND memory. Therefore, the defect of gate contact etching punch-through in the 3D NAND memory can be detected based on the testing device.

The odd-numbered word lines 111 and the even-numbered word lines 112 are parallel to each other and sequentially arranged from one end to the other end of a test device, for example, the test device includes n word lines, n word lines WL parallel to each other₁To WL_nThe word lines WL are marked as the 1 st word line WL from the lower end to the upper end of the testing device₁The first step2 word lines WL₂… …, nth word line WL_nWherein n is not less than 2 and n is an integer. There is a space between every two adjacent word lines, and the height of the space may be the same as the height of the insulating layer between the gate layers. In order to facilitate intuition of detection results, the gate layers in the 3D NAND memory are sequentially ordered from a direction close to the substrate to a direction away from the substrate, and the ordering includes: a first gate layer, a second gate layer, … …, and an Nth gate layer, wherein N is not less than 2, and N is an integer. Then, the 1 st word line corresponds to the first gate layer, the 2 nd word line corresponds to the second gate layer, … …, and the nth word line corresponds to the nth gate layer.

Each word line is formed with a corresponding contact structure, and the contact structure corresponds to a contact of the gate layer, for example, a contact of the first gate layer is referred to as a first contact, a contact of the second gate layer is referred to as a second contact, and a contact of the … … nth gate layer is referred to as an nth contact, so that the contact structure of the 1 st word line corresponds to the first contact, the contact structure of the 2 nd word line corresponds to the second contact, … …, and the contact structure of the nth word line corresponds to the nth contact.

The first testing terminal 10 connects the contact structures 121 of the odd-numbered word lines 111 in series, specifically, connects the contact structures of the 1 st word line, the contact structure of the 3 rd word line, … …, and the contact structure of the 2m +1 th word line in series, where m is an integer greater than or equal to 0, and the second testing terminal 20 connects the contact structures 122 of the even-numbered word lines 112 in series, specifically, connects the contact structures of the 2 nd word line, the contact structure of the 4 th word line, … …, and the contact structure of the 2m +2 th word line in series, where m is an integer greater than or equal to 0. When there is etching through in the contact structures of two adjacent word lines, for example, the contact structure of the 1 st word line penetrates onto the 2 nd word line, the contact structure of the 1 st word line contacts the contact structure of the 2 nd word line, that is, the contact structure of the 1 st word line is connected with the contact structure of the 2 nd word line, because the contact structure of the 1 st word line and the contact structure of the 3 rd word line, … … the contact structure of the 2m +1 th word line is connected in series, and the contact structure of the 2 nd word line and the contact structure of the 4 th word line, the contact structure of the … … the contact structure of the 2m +2 nd word line are connected in series, the contact structures of all word lines are connected in series, that is, the first test terminal 10 and the second test terminal 20 are in a connected state. When the contact structures of two adjacent word lines do not have the etching through condition, the contact structures 121 of the odd-numbered word lines 111 are connected in series, the contact structures 122 of the even-numbered word lines 112 are connected in series, the contact structures 121 of the serially connected odd-numbered word lines 111 and the contact structures 122 of the serially connected even-numbered word lines 112 are in an off state, that is, the first test terminal 10 and the second test terminal 20 are in the off state, so that the test device can test the condition that the contact structures of the word lines have the etching through condition. Since the odd word line 111 and the even word line 112 are formed simultaneously with the word lines of the 3D NAND memory by the same process, the test result obtained by the test apparatus can represent whether there is an etch-through condition in the contact of the adjacent gate layers.

In this embodiment, the sorting direction of the odd-numbered word line 111 and the even-numbered word line 112 is a direction perpendicular to the substrate in the 3D NAND memory, and the extending direction of the odd-numbered word line 121 and the even-numbered word line 122 is a direction extending along the core storage region or a direction extending along the dummy step region in the 3D NAND memory. Specifically, steps are formed on the steps on the two sides of the core storage area in the first axis X direction and the second axis Y direction, a gate contact is formed on the step in the first axis X direction, and a gate contact is formed on the step in the second axis Y direction. When the situation that whether the etching punch-through exists in the gate contact in the first axis X direction needs to be tested, the word line structure can be designed according to the gate layer structure in the first axis X direction in the 3D NAND memory, so that the situation that whether the etching punch-through exists in the gate contact in the first axis X direction can be tested by using the testing device. When the situation that whether the gate contact in the second axis Y direction has the etching punch-through or not needs to be tested, the word line structure can be designed according to the gate layer structure in the 3D NAND memory in the second axis Y direction, so that the situation that whether the gate contact in the second axis Y direction has the etching punch-through or not can be tested according to the testing device.

In a specific application, the first test terminal 10 may include a first metal line 103 and a first pad 101, and the second test terminal 20 includes a second metal line 203 and a second pad 201, and as shown in fig. 4, a first terminal of the first metal line 103 connects the contact structures 121 of the odd-numbered word lines 111 in series, a second terminal of the first metal line 103 is connected to the first pad 201, a first terminal of the second metal line 203 connects the contact structures 122 of the even-numbered word lines 112 in series, and a second terminal of the second metal line 203 is connected to the second pad 201.

As a specific example of the present application, the contact structure is a contact hole filled with a metal material, which may be, for example, metal tungsten.

As another specific example of the present application, the testing apparatus may be located in a scribe line region of a chip in order to not affect the performance of a finally manufactured device and to fully utilize the area of a wafer. The size of the entire reliability testing apparatus can be adjusted according to the size of the scribe line region.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points.

The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.