阅读说明：本技术 一种自对准低欧姆接触电阻GaN HEMT器件及其制造方法 (Self-aligned low-ohmic contact resistance GaN HEMT device and manufacturing method thereof ) 是由 朱广润 张凯 周建军 陈堂胜 于 2020-12-17 设计创作，主要内容包括：本发明涉及一种自对准超低欧姆接触电阻GaN HEMT器件及其制造方法,主要解决了超高频器件尺寸极限微缩条件下对栅源、栅漏间距的有效调制问题,并且具备较高的工艺稳定性,可以实现实验室外的生产制造；所述器件包括衬底、缓冲层、高掺杂n～+-GaN层、源极、势垒层、栅极、势垒金属层和漏极。所述器件基本制造流程为先制造出肖特基T型栅结构,利用所述T型栅结构的金属栅帽作为浮空掩膜,结合高各向异性刻蚀技术,实现对源漏区域的定义,进而实现可靠的短欧姆接触间距,有效降低GaN基器件沟道中载流子渡越时间带来的寄生延时,提升器件截止频率性能。(The invention relates to a self-aligned ultra-low ohmic contact resistance GaN HEMT device and a manufacturing method thereof, mainly solving the problem of effective modulation of the space between a grid source and a grid drain under the condition of ultra-high frequency device size limit shrink and having higher processThe stability is realized, and the production and the manufacture outside a laboratory can be realized; the device comprises a substrate, a buffer layer and a high-doped n + -a GaN layer, a source electrode, a barrier layer, a gate electrode, a barrier metal layer and a drain electrode. The basic manufacturing process of the device comprises the steps of firstly manufacturing a Schottky T-shaped gate structure, utilizing a metal gate cap of the T-shaped gate structure as a floating mask, combining a high-anisotropy etching technology, realizing the definition of a source-drain region, further realizing a reliable short ohmic contact interval, effectively reducing parasitic delay caused by the transition time of current carriers in a GaN-based device channel, and improving the cut-off frequency performance of the device.)

1. The self-aligned low-ohmic contact resistance GaN HEMT device sequentially comprises a substrate (1) and a buffer layer (2) from bottom to top, and is characterized in that the top of the buffer layer (2) is provided with highly-doped n⁺-a GaN layer (3) and barrier layers (5), the barrier layers (5) being arranged at the left and right two highly doped n-layers⁺Between the GaN layers (3), two highly doped n⁺A source metal (4) and a drain metal (8) are respectively arranged at the top of the GaN layer (3), a gate metal (6) is arranged above the barrier layer (5), the gate metal (6) is of a T-shaped gate structure, barrier metal layers (7) are coated on two sides and the bottom of the gate metal, and the highly doped n is used for doping n⁺-the GaN layer (3), the source metal (4) and the drain metal (8) together constitute an ohmic contact region, and the barrier layer (5), the gate metal (6) and the barrier metal layer (7) together constitute a schottky contact region.

2. The self-aligned low-ohmic contact resistance GaN HEMT device according to claim 1, wherein the barrier metal layer (7) is WN alloy and has a thickness of 10-30 nm.

3. The self-aligned low ohmic contact resistance GaN HEMT device according to claim 1, characterized in that the barrier layer (5) is made of AlGaN, InAlN, AlInGaN or AlN; the high doped n⁺-the GaN layer (3) is doped with Si in a concentration of 1X 10¹⁹cm^-3-8×10²⁰cm^-3(ii) a The grid metal (6) is obtained through electron beam evaporation, and the metal layer structure is Pt/Au or Pt/Au/Ti.

4. The self-aligned low ohmic contact resistance GaN HEMT device of claim 1, wherein the highly doped n⁺-the thickness of the GaN layer (3) is 80-200nm, and the thickness of the source metal (4) and the drain metal (8) is 100-400 nm.

5. A method of fabricating the self-aligned low ohmic contact resistance GaN HEMT device of claim 1, comprising the steps of:

1) sequentially growing a buffer layer (2) and a barrier layer (5) on a substrate (1) by using MOCVD;

2) spin-coating photoresist on the surface of the grown material, and manufacturing a grid (6) pattern by adopting a photoetching process;

3) depositing a WN alloy of a barrier metal layer (7) on the surface of the material;

4) evaporating a gate metal (6) on the surface of the material;

5) removing the photoresist and the gate metal (6) and the barrier metal layer (7) attached to the surface of the photoresist by a wet method;

6) depositing a medium sacrificial layer;

7) etching the medium sacrificial layer, the barrier layer (5) and the buffer layer (2);

8) growing highly doped n⁺-a GaN layer (3);

9) removing the dielectric sacrificial layer and the highly doped n attached to the surface thereof by a wet method⁺-a GaN layer (3);

10) in the remaining highly doped n⁺-the GaN layer (3) forms a source metal (4) and a drain metal (8), obtaining ohmic contacts.

6. The method according to claim 5, wherein the barrier layer (5) is made of AlGaN, InAlN, AlInGaN, or AlN; the high doped n⁺-the GaN layer (3) is doped with Si in a concentration of 1X 10¹⁹cm^-3-8×10²⁰cm^-3(ii) a The grid metal (6) is obtained through electron beam evaporation, and the metal layer structure is Pt/Au or Pt/Au/Ti.

7. The manufacturing method according to claim 5, characterized in that the material of the substrate (1) of step 1) is SiC, Si, diamond or GaN; the medium sacrificial layer in the steps 6), 7) and 9) is made of SiN, SiON or SiO₂Any one or more combinations thereof.

8. The manufacturing method according to claim 5, wherein the barrier metal layer (7) of step 3) is deposited by ALD or DC magnetron sputtering.

9. Manufacturing method according to claim 5, characterized in that step 7) the barrier layer (5) and buffer layer (2) are etched to a depth of 50-150nm, step 8) the highly doped n⁺-the thickness of the GaN layer (3) is 80-200nm, and the thickness of the source metal (4) and the drain metal (8) in step 10) is 100-400 nm.

10. Manufacturing method according to claim 5, characterized in that step 8) the high doping n⁺-the GaN layer (3) is grown in MBE or MOCVD.

Technical Field

The invention belongs to the technical field of semiconductor device manufacturing, and particularly relates to a self-aligned low-ohmic contact resistance GaN HEMT device and a manufacturing method thereof.

Background

Due to the advantages of wide forbidden band, high electronic saturation drift velocity, high breakdown field strength and the like, the GaN material has great application value in the fields of weaponry, space application, wireless communication and the like. Especially, ultra High Electron Mobility Transistors (HEMTs) based on GaN materials have developed many application scenarios in the field of civil and weaponry.

An important means for improving the cut-off frequency performance of GaN microwave devices is to control parasitic delay, and for lateral channel devices, it is required to achieve the performance of device size reduction, such as the distance from a drain to a source, the length of a gate, and the longitudinal aspect such as the distance between a gate schottky contact and a two-dimensional electron gas, so as to achieve the shortest possible carrier transit time and good gate control. Therefore, an ohmic contact pitch as short as possible is one of important issues to improve the cutoff frequency performance. The traditional ohmic contact manufacturing method is mainly based on an alloy process of a Ti/Al or Ti/Al/Ni/Au multilayer metal structure, wherein the alloy usually needs rapid thermal annealing at 800-. To overcome this problem, an ohmic contact manufacturing method based on a regrowth technology is gradually becoming the mainstream of the manufacture of the ultra-high frequency GaN HEMT device. In 2015, the space between a grid source and a grid drain is shortened to 50nm and the length of the grid is 20nm on the surface of an AlN/GaN heterojunction with an ultrathin potential barrier by Huiss laboratory in the United statesNow f_T/f_maxHigh cut-off frequency performance results at 444/454GHz (see Tang Y, Shinohara K, Regan D, et al, ultra High-Speed GaN High-Electron-Mobility Transistors With f_T/f_max of 454/444 GHz[J]IEEE Electron Device Letters,2015,36(6): 549-.

Chinese patent CN 1998085B discloses a method for fabricating a nitride-based transistor with a regrown ohmic contact region and a nitride-based transistor with a regrown ohmic contact region, whose basic principle is to perform Si, Ge and/or O doped InGaN, AlInGaN, InAlN, GaN, AlGaN and/or InN growth in a nitride semiconductor ohmic contact region using MOCVD or MBE technology to achieve low ohmic contact resistance characteristics. The scheme can well realize the low ohmic contact resistance of the surface of the nitride semiconductor, but is limited by a gate preparation technology, and cannot realize a high-performance microwave device.

Chinese patent 201710549494.2 discloses a GaN ultra-high frequency device based on self-aligned gate and its manufacturing method, which is based on the basic principle that after T-shaped gate is etched, barrier layer is directly etched and oxidized to form gate dielectric, and then gate metal is evaporated to realize self-alignment of T-shaped gate electrode, groove and gate dielectric. The scheme can realize the ultrahigh frequency GaN device with low grid leakage under the condition of short grid length, avoids the registration error caused by secondary photoetching of a T-shaped grid structure, and cannot shorten the transit time of a current carrier in the channel direction.

Chinese patent CN 103715255B discloses a self-aligned gate GaN HEMT device and a preparation method thereof, the basic principle is that SiN medium is deposited on the surface of a substrate, source and drain metal is manufactured in an etched source and drain area, the side face of the metal is protected by oxide, a gate groove is etched by utilizing the high selection ratio of SiN and photoresist in the dry etching process, and the manufacture of the self-aligned gate GaN HEMT is completed. According to the scheme, the self-alignment of the gate and source-drain ohmic contact can be realized, but the T-shaped gate required by an ultrahigh frequency device cannot be realized, and the barrier layer can be damaged unavoidably in the etching process of the gate protection SiN medium.

In addition, the active region of the microwave device generates certain heat under the high-frequency working state, and the reliability of the device work and the Schottky contact performance are greatly influenced. Experimental results show that the Schottky barrier characteristics of the Schottky metal half-contact formed by Ni and AlGaN are seriously degraded or even failed when the junction temperature reaches above 400 ℃.

Disclosure of Invention

The invention aims to provide a self-aligned low-ohmic contact resistance GaN HEMT device with high cut-off frequency performance and a manufacturing method thereof, which not only can realize higher device performance, but also can provide better reliability, and more simple and convenient process steps, and is suitable for the production and the manufacture of GaN microwave devices.

The technical solution for realizing the purpose of the invention is as follows: a self-aligned low-ohmic contact resistance GaN HEMT device sequentially comprises a substrate and a buffer layer from bottom to top, wherein the top of the buffer layer is provided with highly-doped n⁺A GaN layer and barrier layers arranged at the left and right sides of the highly doped n⁺Between the GaN layers, two highly doped n⁺A source metal and a drain metal are respectively arranged at the top of the GaN layer, a gate metal is arranged above the barrier layer, the gate metal is of a T-shaped gate structure, and barrier metal layers are coated at the two sides and the bottom of the grid metal; with said high doping of n⁺-the GaN layer, the source metal and the drain metal together constitute an ohmic contact region, and the barrier layer, the gate metal and the barrier metal layer together constitute a schottky contact region.

A manufacturing method of a self-aligned low-ohmic contact resistance GaN HEMT device comprises the following steps:

1) sequentially growing a buffer layer and a barrier layer on a substrate by using MOCVD;

2) spin-coating photoresist on the surface of the grown material, and manufacturing a grid pattern by adopting a photoetching process;

3) depositing a WN alloy of a barrier metal layer on the surface of the material;

4) evaporating grid metal on the surface of the material;

5) removing the photoresist and the gate metal and the barrier metal layer attached to the surface of the photoresist by a wet method;

6) depositing a medium sacrificial layer;

7) etching the medium sacrificial layer, the barrier layer and the buffer layer;

8) growing highly doped n⁺-a GaN layer;

9) removing the dielectric sacrificial layer and the highly doped n attached to the surface thereof by a wet method⁺-a GaN layer;

10) in the remaining highly doped n⁺The GaN layer forms the source and drain metals, obtaining ohmic contacts.

Compared with the prior art, the invention has the remarkable advantages that:

(1) according to the self-aligned low-ohmic contact resistance GaN HEMT device, selective etching and epitaxy of GaN materials are realized by using the suspended mask, self-alignment of a size micro device is realized by the mask structure, the process is simple and convenient, the requirement on the etching precision is low, and the production and manufacturing are convenient to realize.

(2) According to the self-aligned low-ohmic contact resistance GaN HEMT device, a WN refractory metal barrier structure is introduced into a microwave device, so that the reliability of the device is greatly improved, and the requirement of higher-temperature work can be met.

Drawings

Fig. 1 is a cross-sectional view of a self-aligned low ohmic contact resistance GaN HEMT device according to the present invention.

Fig. 2, fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, fig. 8, fig. 9, fig. 10, and fig. 11 are schematic flow charts of a method for manufacturing a self-aligned low ohmic contact resistance GaN HEMT device according to the present invention in sequence.

Fig. 12 is a dimension plot of a self-aligned low ohmic contact resistance GaN HEMT device.

Detailed Description

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.

Referring to fig. 1, the invention provides a self-aligned low-ohmic contact resistance GaN HEMT device, which comprises a substrate 1 and a buffer layerBuffer 2, highly doped n⁺GaN layer 3, source metal 4, barrier layer 5, gate metal 6, barrier metal layer 7 and drain metal 8.

The buffer layer 2 is arranged above the substrate 1, and the top of the buffer layer 2 is provided with highly doped n⁺A GaN layer 3 and barrier layers 5, the barrier layers 5 being disposed at the left and right sides of the highly doped n⁺Between the GaN layers 3, two highly doped n⁺A source metal 4 and a drain metal 8 are respectively arranged on the top of the GaN layer 3, a gate metal 6 is arranged above the barrier layer 5, the gate metal 6 is of a T-shaped gate structure, and barrier metal layers 7 are coated on two sides and the bottom of the GaN layer, wherein the two sides are the left side and the right side opposite to the source metal 4 and the drain metal 8; the transverse width of the barrier layer 5 is the same as the width of the capping layer metal of the grid electrode 6; with said high doping of n⁺The GaN layer 3, the source metal 4 and the drain metal 8 together form an ohmic contact region, and the barrier layer 5, the gate metal 6 and the barrier metal layer 7 together form a schottky contact region. Wherein:

the lateral width of the barrier layer is determined by the capping metal width of the gate.

The barrier metal layer 7 is made of WN and is 10-30nm thick.

The barrier layer 5 is made of one of AlGaN, InAlN, AlInGaN or AlN.

The high doped n⁺The doping element of the GaN layer is Si or Ge with the doping concentration of 1 × 10¹⁹cm^-3-8×10²⁰cm^-3。

The grid metal 6 is obtained by electron beam evaporation, and the metal layer structure comprises but is not limited to Pt/Au, Pt/Au/Ti and the like.

As shown in fig. 12, the high-doped n + -GaN layer 3, the source metal 4 and the drain metal 8 are retracted to form an equal-length spacing L1, which is 50-250 nm;

the top width L2 of the T-shaped structure formed by the gate metal 6 and the barrier metal layer 7 is equal to the distance between the highly doped n + -GaN layers 3 on the two sides, and the value L2 is 200-800 nm; the transverse width of the barrier layer 5 is the same as the width of a T-shaped structure cap layer metal formed by the gate metal 6 and the barrier metal layer 7.

And the width L3 of the lower part of the T-shaped structure formed by the gate metal 6 and the barrier metal layer 7 forms the characteristic gate length of the device, and the value of the characteristic gate length is 15-60 nm.

The total height H1 of the T-shaped structure formed by the gate metal 6 and the barrier metal layer 7 is 800-1800 nm;

the height H2 of the lower part of the T-shaped structure formed by the gate metal 6 and the barrier metal layer 7 is 150-500 nm;

the thicknesses of the source metal 4 and the drain metal 8 are equal to form H3, and the value of H3 is 100-400 nm;

the thickness H4 of the highly doped n + -GaN layer 3 is 80-200 nm.

Referring to the attached drawings 2-11, the invention provides a manufacturing method of a self-aligned low-ohmic contact resistance GaN HEMT device, which comprises the following specific steps:

1) on a substrate, a buffer layer 2 and a barrier layer 5 are grown in sequence by using MOCVD, as shown in FIG. 2;

2) spin-coating photoresist on the surface of the material, and manufacturing a gate pattern by adopting a photoetching process, as shown in FIG. 3;

3) depositing a WN alloy of a barrier metal layer on the surface of the material subjected to photoetching;

4) evaporating or sputtering gate metal on the surface of the material, as shown in fig. 4;

5) removing the photoresist and the redundant gate and barrier metal layer metal attached to the surface thereof by a wet method, as shown in fig. 5;

6) depositing a medium sacrificial layer on the surface of the material, as shown in FIG. 6;

7) etching the dielectric sacrificial layer, the barrier layer 5 and the buffer layer 2 by using strong anisotropy dry etching equipment, as shown in fig. 7 and 8;

8) growing highly doped n on the surface of the etched material⁺GaN layer 3, as in fig. 9;

9) removing the material surface medium sacrificial layer and the redundant highly doped n attached to the surface of the material surface by a wet method⁺GaN layer 3, as in fig. 10;

10) in the material is highly doped with n⁺The GaN layer defines the active area by photolithography, followed by evaporation and lift-off to form the source and drain metals, obtaining ohmic contacts, as in fig. 11.

Further, the substrate 1 in the step 1) is made of SiC, Si, diamond or GaN;

the medium sacrificial layer in the steps 6), 7) and 9) is made of SiN, SiON or SiO₂Any one or more combinations thereof.

Further, the deposition mode of the barrier metal layer 7 in the step 3) is ALD or direct current magnetron sputtering.

Further, in the step 7), the etching depth of the barrier layer 5 and the buffer layer 2 is 50-150 nm;

step 8) the high doping of n⁺The thickness of the GaN layer 3 is 80-200 nm;

step 10) the thickness of the source metal 4 and the drain metal 8 is 100-400 nm.

Further, step 8) said highly doped n⁺The GaN layer 3 is grown by MBE or MOCVD.

The basic principle of the invention is to use a large-span gate cap structure formed after gate manufacture as a suspension mask, to realize etching of a material surface dielectric sacrificial layer, a barrier layer and a buffer layer by adopting strong anisotropy dry etching, and to grow n⁺-a GaN region. In this way, the gate source/gate drain spacing is completely defined by the gate cap metal dimensions, ultimately achieving a self-aligned device structure.

According to the self-aligned low ohmic contact resistance GaN HEMT device and the method of fabricating the same of the present invention described above, specific embodiments of the present invention are further disclosed below, but not limited to these embodiments.

Example 1

The substrate 1 is made of SiC, and the barrier layer 5 is made of Al_xGa_1-xA GaN high electron mobility transistor with a 12nm thick split sub-device, N, x ═ 0.28, the process of fabrication is:

1) on a substrate 1 made of SiC, a 2 μm unintentionally doped GaN layer was grown at 950 ℃ by MOCVD, to form a buffer layer 2, and then an AlGaN barrier layer 5 having a thickness of 12nm was grown on the buffer layer 2, with an Al component of 28%.

2) Sequentially spin-coating ZEP520A and PMGI on the surface of the barrier layer 5 from bottom to topThe ZEP520A photoresist is used for completing grid exposure by using an electron beam direct writing process, and a one-time exposure technology is used for completing T-shaped structure exposure, and a T-shaped grid pattern is manufactured after development; the process conditions of the electron beam direct writing are as follows: the thicknesses of the electron beam glue ZEP520A, PMGI and ZEP520A from bottom to top are 250nm, 400nm and 250nm in sequence; the 50nm line width exposure energy is 800 mu C/cm²(ii) a The exposure energy of 500nm linewidth is 200 mu C/cm²(ii) a The developing solution was completed using ZED-N50, TMAH, ZED-N50 in this order from top to bottom.

3) Growing a WN alloy barrier metal layer 7 on the surface of the T-shaped gate pattern by adopting ALD equipment; the WN alloy growth process conditions are as follows: the growth temperature is 100 ℃, the source time of bis (tert-butylimino) bis (dimethylamino) tungsten (VI) is 1.5-3.5s, the source time of ammonia gas is 1.5-3.5s, the purging time is 4-6s, the radio frequency power is 40W, the number of growth cycles is 300, and the thickness is 15-25 nm.

4) Evaporating metal of a grid 6 on the surface of the deposition material of the barrier metal layer 7 through an electron beam, wherein the metal structure is Pt and Au from bottom to top, and the corresponding thickness is 100nm and 400nm from bottom to top; the process conditions of the electron beam evaporation are as follows: vacuum degree ≦ 2.0X 10^-6Torr, deposition rate less than

5) The material is alternately treated by acetone, N-methylpyrrolidone solution, ethanol and deionized water, and the photoresist on the surface of the barrier layer 5 and the metal on the surface of the photoresist are removed; then, using oxygen plasma to process the material, and then carrying out rapid thermal annealing treatment in a nitrogen atmosphere; the process conditions of the oxygen plasma treatment are as follows: oxygen flow is 500sccm, power is 200W, and time is 180 s; the process conditions of the rapid thermal annealing are as follows: the temperature is 400 ℃ and 550 ℃, and the time is 2-4 min.

6) Growing SiO on the surfaces of the barrier layer 5, the grid electrode 6 and the barrier metal layer 7 through PECVD₂A dielectric sacrificial layer; the technological conditions for growing the SiO2 dielectric sacrificial layer are as follows: gases are SiH respectively₄、N₂O, He and N₂The flow rates are 8sccm, 20sccm, 150sccm and 200sccm, the pressure is 250-400mT, the temperature is 250-340 ℃, the power is 50W, and the thickness isIs 150 nm.

7) Respectively etching the 150nm SiO2, the barrier layer 5 and the buffer layer 2 by using a high anisotropy ICP etching by taking a grid cap suspension structure formed by the grid electrode 6 and the barrier metal layer 7 as a mask; wherein the etching conditions of the SiO2 are as follows: the gas is SF6, the flow is 40sccm, the pressure is 0.2Pa, the temperature is 100 ℃, the power of an upper electrode is 150-200W, the power of a lower electrode is 10-20W, and the etching depth is 150 nm; the etching conditions of the barrier layer 5 and the buffer layer 2 are as follows: the gas being Cl₂The flow rate is 10sccm, the pressure is 1Pa, the temperature is 25 ℃, the power of an upper electrode is 80-120W, the power of a lower electrode is 5-10W, the etching depth of a barrier layer 5 is 12nm, and the etching depth of a buffer layer 2 is 100 nm.

8) MOCVD is used for forming the buffer layer 2, the barrier layer 5 and the dielectric sacrificial layer SiO₂Highly doped n is grown on the surfaces of the grid electrode 6 and the barrier metal layer 7⁺-a GaN layer 3; highly doped n⁺The process conditions for growing the GaN layer 3 are: the chamber pressure is 40-60mTorr, the temperature is 950-¹⁹cm^-3-8×10²⁰cm^-3And the thickness is 150 nm.

9) Highly doping the growth with n⁺Removing SiO on the surface of the material behind the GaN layer 3 by using standard BOE buffer oxide etching liquid₂Sacrificial dielectric layer and excess highly doped n attached to surface thereof⁺A GaN layer 3.

10) Highly doped n on both sides of the gate 6⁺The surface of GaN layer 3 is lithographically opened, and source 4 and drain 8 metals are formed by electron beam evaporation and lift-off; the process conditions for depositing the metal are as follows: vacuum degree ≦ 1.5X 10^-6Torr, deposition rate less thanThe material of the deposited metal lamination layer is sequentially Ti, Pt and Au from bottom to top, and the thickness of the deposited metal lamination layer is respectively 20nm, 100nm and 200 nm.

Example 2

A self-aligned low-ohmic contact resistance GaN HEMT device with a substrate 1 of Si, a barrier layer 5 of AlN and a thickness of 8nm is manufactured by the following steps:

1) on a substrate 1 made of Si, an unintentionally doped GaN layer of 2 μm is grown at 950 ℃ by MOCVD, to form a buffer layer 2, and then an AlN barrier layer 5 of 8nm in thickness is grown on the buffer layer 2.

2) Spin-coating PMMA, PMGI and PMMA photoresist on the surface of the barrier layer 5 from bottom to top in sequence, completing gate exposure by using an electron beam direct writing process, completing T-shaped structure exposure by using a one-time exposure technology, and manufacturing a T-shaped gate pattern after development; the process conditions of the electron beam direct writing are as follows: the thicknesses of the PMMA, the PMGI and the PMMA are 250nm, 400nm and 250nm in sequence from bottom to top; the 50nm line width exposure energy is 2000 mu C/cm²(ii) a The exposure energy of 500nm linewidth is 800 mu C/cm²(ii) a The developing solution is sequentially prepared from MIBK, TMAH and MIBK from top to bottom.

3) Growing a WN alloy barrier metal layer 7 on the surface of the T-shaped gate pattern by adopting ALD equipment; the WN alloy growth process conditions are as follows: thermal growth at 150 deg.C and W₂(NMe₂)₆The source supply time is 2-4s, the ammonia gas source supply time is 2-4s, the purging time is 2-6s, the number of growth cycles is 300, and the thickness is 15-25 nm.

4) Step 4) of example 2 is the same as step 4) of example 1.

5) The material is alternately treated by acetone, N-methylpyrrolidone solution, ethanol and deionized water, and the photoresist on the surface of the barrier layer 5 and the metal on the surface of the photoresist are removed; then, using oxygen plasma to process the material, and then carrying out rapid thermal annealing treatment in a nitrogen atmosphere; the process conditions of the oxygen plasma treatment are as follows: oxygen flow is 500sccm, power is 200W, and time is 180 s; the process conditions of the rapid thermal annealing are as follows: the temperature is 350 ℃ and 500 ℃, and the time is 2-3 min.

6) Sequentially growing SiN and SiO on the surfaces of the barrier layer 5, the grid 6 and the barrier metal layer 7 through PECVD₂A dielectric sacrificial layer; the technological conditions for the growth of the SiN medium sacrificial layer are as follows: gases are SiH respectively₄、NH₃He and N₂The flow rates are respectively 6sccm, 3sccm, 150sccm and 200sccm, the pressure is 300-450mTorr, the temperature is 300-340 ℃,the power is 25W, and the thickness is 50 nm; the technological conditions for growing the SiO2 dielectric sacrificial layer are as follows: gases are SiH respectively₄、N₂O, He and N₂The flow rates are 8sccm, 20sccm, 150sccm and 200sccm, respectively, the pressure is 250-400mT, the temperature is 250-340 ℃, the power is 50W, and the thickness is 100 nm.

7) Taking a grid cap suspension structure formed by the grid electrode 6 and the barrier metal layer 7 as a mask, and etching the 100nm SiO2, the 50nm SiN, the barrier layer 5 and the buffer layer 2 in sequence by using high anisotropy ICP etching; wherein the etching conditions of the SiO2 are as follows: the gas is SF6, the flow is 40sccm, the pressure is 0.2Pa, the temperature is 100 ℃, the power of an upper electrode is 150-200W, the power of a lower electrode is 10-20W, and the etching depth is 100 nm; the etching conditions of the SiO2 are as follows: the gas is SF6, the flow rate is 60sccm, the pressure is 0.2Pa, the temperature is 100 ℃, the power of an upper electrode is 170-220W, the power of a lower electrode is 15-25W, and the etching depth is 50 nm; the etching conditions of the barrier layer 5 and the buffer layer 2 are as follows: the gas being Cl₂The flow rate is 10sccm, the pressure is 1Pa, the temperature is 25 ℃, the power of an upper electrode is 80-120W, the power of a lower electrode is 5-10W, the etching depth of a barrier layer 5 is 12nm, and the etching depth of a buffer layer 2 is 100 nm.

8) MBE is used for the buffer layer 2, the barrier layer 5, the medium sacrificial layer SiN and the medium sacrificial layer SiO₂Highly doped n is grown on the surfaces of the grid electrode 6 and the barrier metal layer 7⁺-a GaN layer 3; highly doped n⁺The process conditions for growing the GaN layer 3 are: the growth temperature is 700-800 ℃, the ammonia gas flow is 30-80sccm, the silicon source temperature is 1200-1300 ℃, the doping concentration is 1 multiplied by 10¹⁹cm^-3-8×10²⁰cm^-3And the thickness is 150 nm.

9) Highly doping the growth with n⁺Removing SiO on the surface of the material behind the GaN layer 3 by using standard BOE buffer oxide etching liquid₂Sacrificial dielectric layer, SiN sacrificial dielectric layer and redundant highly doped n attached to surface of SiN sacrificial dielectric layer⁺A GaN layer 3.

10) Step 10) of example 2 is the same as step 10) of example 1.

The above embodiments and examples are specific supports for the technical ideas of the self-aligned low-ohmic contact resistance GaN HEMT device and the manufacturing method thereof proposed by the present invention, and therefore the protection scope of the present invention cannot be limited by the above embodiments and examples, and any equivalent changes or equivalent modifications made on the basis of the technical scheme according to the technical ideas proposed by the present invention still belong to the protection scope of the technical scheme of the present invention.