阅读说明：本技术 阵列基板及其制作方法、母板以及显示装置 (Array substrate and manufacturing method thereof, mother board and display device ) 是由 缪应蒙 张银淑 孙志华 于 2019-09-29 设计创作，主要内容包括：一种阵列基板(100)及其制作方法、母板以及显示装置。阵列基板(100)具有显示区域(DR)和非显示区域(PR),且包括衬底基板、设置在衬底基板上的多条信号线(400)和至少一个转接电极。多条信号线(400)沿第一方向从显示区域(DR)延伸至非显示区域(PR),多条信号线(400)中的至少一条包括位于显示区域(DR)内的第一走线(WL1)和位于非显示区域(PR)的第二走线(WL2),第二走线(WL2)包括至少两个彼此断开的子走线,其中,第二走线(WL2)的至少两个子走线中靠近显示区域(DR)的子走线和第一走线(WL1)直接连接,第二走线(WL2)中每相邻的两个子走线通过转接电极彼此电连接。阵列基板(100)可以改善或避免由于信号线(400)上的电荷累积而造成的断裂等不良。(An array substrate (100) and a manufacturing method thereof, a mother board and a display device are provided. The array substrate (100) has a Display Region (DR) and a non-display region (PR), and includes a substrate base, a plurality of signal lines (400) disposed on the substrate base, and at least one via electrode. The plurality of signal lines (400) extend from the display area (DR) to the non-display area (PR) along the first direction, at least one of the plurality of signal lines (400) comprises a first routing line (WL1) located in the display area (DR) and a second routing line (WL2) located in the non-display area (PR), the second routing line (WL2) comprises at least two sub-routing lines which are disconnected with each other, wherein the sub-routing line close to the display area (DR) in the at least two sub-routing lines of the second routing line (WL2) is directly connected with the first routing line (WL1), and every two adjacent sub-routing lines in the second routing line (WL2) are electrically connected with each other through the switching electrodes. The array substrate (100) can improve or avoid defects such as breakage caused by charge accumulation on the signal lines (400).)

An array substrate having a display area and a non-display area, comprising: a substrate base plate, a plurality of signal lines and at least one transfer electrode arranged on the substrate base plate, wherein,

the plurality of signal lines extend from the display area to the non-display area in a first direction,

at least one of the plurality of signal lines includes a first trace located in the display area and a second trace located in the non-display area,

the second trace comprises at least two sub-traces disconnected from each other, wherein the sub-trace close to the display area in the at least two sub-traces of the second trace is directly connected with the first trace,

every two adjacent sub-wirings in the second wirings are electrically connected with each other through the transfer electrode.

The array substrate of claim 1, wherein the first trace and the second trace are disposed in a same layer with respect to the substrate.

The array substrate of claim 1 or 2,

the signal lines are arranged in parallel along a second direction, and the first direction is intersected with the second direction;

the first sub-routing comprises a part used as a fan-out-shaped routing, the extending direction of the part used as the fan-out-shaped routing is a third direction, and the third direction is intersected with the first direction and the second direction.

The array substrate according to any one of claims 1 to 3,

the first sub-routing is connected with the switching electrode through at least one first via hole, and the second sub-routing is connected with the switching electrode through at least one second via hole.

The array substrate of claim 4,

the projection position of the first via hole on the board surface of the substrate base board is located at one end, away from the display area, of the first sub-routing;

the projection position of the second via hole on the board surface of the substrate base board is located at one end, close to the display area, of the second sub-routing.

The array substrate of claim 4 or 5,

the plurality of signal lines are a plurality of gate lines,

the array substrate comprises a gate metal layer, at least one insulating layer and a conducting layer which are sequentially arranged on the substrate, the gate metal layer comprises a plurality of gate lines, the conducting layer comprises at least one switching electrode, and the first via hole and the second via hole penetrate through the at least one insulating layer;

the projection of the through electrode and the at least one first via hole on the plate surface of the substrate base plate at least partially overlaps, and the projection of the through electrode and the at least one second via hole on the plate surface of the array base plate at least partially overlaps.

The array substrate of claim 6, wherein the array substrate further comprises a thin film transistor on the substrate,

wherein the thin film transistor includes a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode, the gate insulating layer being between the gate electrode and the active layer,

the gate metal layer further includes the gate electrode, the conductive layer further includes the source electrode and the drain electrode, and the at least one insulating layer includes the gate insulating layer.

The array substrate of claim 6, wherein the array substrate further comprises a thin film transistor, a passivation layer, and a pixel electrode on the substrate base,

wherein the thin film transistor includes a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode, the gate insulating layer being between the gate electrode and the active layer,

the passivation layer is arranged on one side of the thin film transistor far away from the substrate base plate and comprises a through hole exposing one of the source electrode and the drain electrode,

the pixel electrode is arranged on one side of the passivation layer far away from the substrate base plate and is electrically connected with one of the source electrode and the drain electrode through the through hole,

the gate metal layer further includes the gate electrode, the conductive layer further includes the pixel electrode, the pixel electrode is located in the display region, and the at least one insulating layer includes a stack of the gate insulating layer and the passivation layer.

A display device, comprising:

the array substrate of any one of claims 1-8,

an opposite substrate coupled to the array substrate,

and the flexible circuit board is bonded with the array substrate to be electrically connected.

A mother board comprising at least one array substrate unit having a display area and a non-display area, comprising: a substrate base plate, a plurality of signal lines arranged on the substrate base plate, at least one transfer electrode and a detection line, wherein,

the plurality of signal lines extend from the display area to the non-display area in a first direction,

at least one of the plurality of signal lines includes a first trace located in the display area and a second trace located in the non-display area,

the second trace comprises at least two sub-traces disconnected from each other, wherein the sub-trace close to the display area in the at least two sub-traces of the second trace is directly connected with the first trace,

every two adjacent sub-wirings in the second wiring are electrically connected with each other through the transfer electrode,

the detection lines are disposed in the non-display area in a second direction,

the sub-lines far away from the display area in at least two sub-lines of the detection line and the second line are connected, and the first direction is intersected with the second direction.

The motherboard of claim 10, wherein the second trace includes a first sub-trace and a second sub-trace that are disconnected from each other, the first sub-trace and the first trace being directly connected, the second sub-trace and the sense line being directly connected.

The motherboard of claim 11, wherein,

the distance between one end of the first sub-wiring far away from the display area and one end of the second sub-wiring close to the display area is a first distance, and the first distance is greater than or equal to 5 micrometers and less than or equal to 12 micrometers.

The motherboard of claim 12, wherein,

the distance of the transfer electrode in the direction perpendicular to the extending direction of the first sub-routing is a second distance, and the second distance is greater than or equal to 35 micrometers and less than or equal to 45 micrometers.

The motherboard according to any of claims 10 to 13,

the first sub-routing is connected with the switching electrode through at least one first via hole, and the second sub-routing is connected with the switching electrode through at least one second via hole.

The motherboard of claim 14, wherein,

the projection position of the first via hole on the board surface of the substrate base board is located at one end, away from the display area, of the first sub-routing;

the projection position of the second via hole on the board surface of the substrate base board is located at one end, close to the display area, of the second sub-routing.

The motherboard according to claim 14 or 15,

the plurality of signal lines are a plurality of gate lines,

the array substrate unit comprises a gate metal layer, at least one insulating layer and a conducting layer which are sequentially arranged on the substrate, the gate metal layer comprises a plurality of gate lines, the conducting layer comprises at least one switching electrode, and the first via hole and the second via hole penetrate through the at least one insulating layer;

the projection of the through electrode and the at least one first via hole on the board surface of the substrate base plate at least partially overlaps, and the projection of the through electrode and the at least one second via hole on the board surface of the substrate base plate at least partially overlaps.

A method for manufacturing an array substrate, the array substrate having a display area and a non-display area, the method comprising:

providing a substrate, and

a plurality of signal lines and at least one via electrode are formed on the substrate base plate,

wherein the plurality of signal lines extend from the display area to the non-display area in a first direction,

at least one of the plurality of signal lines includes a first trace located in the display area and a second trace located in the non-display area,

the second trace comprises at least two sub-traces disconnected from each other, wherein the sub-trace close to the display area in the at least two sub-traces of the second trace is directly connected with the first trace,

every two adjacent sub-wirings in the second wirings are electrically connected with each other through the transfer electrode.

The method of manufacturing of claim 17, wherein forming a plurality of signal lines and at least one via electrode on the substrate base substrate comprises:

sequentially forming a gate metal layer, at least one insulating layer, and a conductive layer on the substrate base plate,

the plurality of signal lines are a plurality of gate lines, the gate metal layer includes the plurality of gate lines,

the conductive layer comprises the at least one via electrode,

the at least one insulating layer comprises at least one first via hole and at least one second via hole, the first sub-routing is connected with the through electrode through the at least one first via hole, and the second sub-routing is connected with the through electrode through the at least one second via hole.

The method of manufacturing according to claim 17 or 18, further comprising:

detecting lines arranged in a second direction are formed in the non-display area,

the detection line is connected with a sub-line at one end, far away from the display area, of at least two sub-lines of the second line, and the first direction is intersected with the second direction.

The method of manufacturing of claim 19, further comprising:

and cutting off the part where the detection line is positioned from the substrate base plate.