阅读说明：本技术 闪存存储器的操作方法及装置 (Operation method and device of flash memory ) 是由 张黄鹏 于 2021-01-25 设计创作，主要内容包括：本发明提供了一种闪存存储器的操作方法及装置,操作方法的特征在于：在对所述闪存存储器进行数据操作时,向所述闪存存储器写入操作命令；所述操作命令至少包括地址信息；所述地址信息包括数据地址和补偿特征值；所述闪存存储器包括外围电路和存储单元阵列；所述外围电路根据所述补偿特征值调节数据操作参数并对所述存储单元阵列中所述数据地址处的数据执行所述数据操作。本发明在对闪存存储器进行数据操作时,将补偿特征值设置于地址信息中,无需额外引入特征值设置序列,从而大幅节省了闪存存储器数据操作时间,提升了器件性能。(The invention provides an operation method and a device of a flash memory, and the operation method is characterized in that: writing an operation command into the flash memory when performing data operation on the flash memory; the operation command at least comprises address information; the address information comprises a data address and a compensation characteristic value; the flash memory includes a peripheral circuit and a memory cell array; the peripheral circuit adjusts a data operation parameter according to the compensation characteristic value and performs the data operation on the data at the data address in the memory cell array. When the data operation is carried out on the flash memory, the compensation characteristic value is set in the address information, and a characteristic value setting sequence is not required to be additionally introduced, so that the data operation time of the flash memory is greatly saved, and the device performance is improved.)

1. An operating method of a flash memory, comprising:

writing an operation command into the flash memory when performing data operation on the flash memory; the operation command at least comprises address information; the address information comprises a data address and a compensation characteristic value;

the flash memory includes a peripheral circuit and a memory cell array; the peripheral circuit adjusts a data operation parameter according to the compensation characteristic value and performs the data operation on the data at the data address in the memory cell array.

2. The method of operating a flash memory according to claim 1, wherein: the data operation includes data reading, data writing or data erasing.

3. The method of operating a flash memory according to claim 2, wherein: when the data operation is data reading, the compensation characteristic value comprises a reading compensation characteristic value, and the data operation parameters comprise a reading level, resolution and scanning range thereof.

4. The method of claim 3, wherein: the memory cells in the memory cell array comprise single-level cells and three-level cells; the three-level unit comprises a lower-layer page storage unit, a middle-layer page storage unit and an upper-layer page storage unit.

5. The method of claim 4, wherein: the reading the compensation characteristic value comprises:

a single-layer read compensation characteristic value that adjusts a read data operating parameter of the single-level cell;

a first read compensation characteristic value and a fifth read compensation characteristic value which adjust read data operation parameters of the lower page memory unit;

a second read compensation characteristic value, a fourth read compensation characteristic value and a sixth read compensation characteristic value which are used for adjusting the read data operation parameters of the middle-layer page storage unit;

a third read compensation characteristic value and a seventh read compensation characteristic value that adjust the read data operating parameters of the upper page memory cells.

6. The method of claim 5, wherein: the read compensation characteristic values are sequentially arranged into a first compensation interval, a second compensation interval and a third compensation interval in an address writing period; the first compensation interval is used for writing the single-layer read compensation characteristic value, the first read compensation characteristic value, the second read compensation characteristic value and the third read compensation characteristic value; the second compensation interval is used for writing the fourth read compensation characteristic value, the fifth read compensation characteristic value and the seventh read compensation characteristic value; the third compensation interval is used for writing the sixth read compensation characteristic value.

7. The method of claim 6, wherein: and a reserved interval is also arranged behind the third compensation interval.

8. The method of operating a flash memory according to claim 1, wherein: the data address comprises a row address and a column address; in the address writing period, the sequence of the address information is sequentially arranged into a column address, a row address and a compensation characteristic value.

9. A flash memory device, comprising: a peripheral circuit and a memory cell array;

the peripheral circuitry includes a data register and a feature register;

when the flash memory carries out data operation, writing an operation command into the peripheral circuit, wherein the operation command at least comprises address information, and the address information comprises a data address and a compensation characteristic value;

the data register is used for storing the data address; the characteristic register is used for storing the compensation characteristic value;

the peripheral circuit adjusts a data operation parameter according to the compensation characteristic value and performs the data operation on the data at the data address in the memory cell array.

10. The flash memory device of claim 9, wherein: the peripheral circuit further comprises a first data selector and a second data selector;

the input end of the first data selector is connected with a data input clock signal and a characteristic value input clock signal, and the output end of the first data selector is connected with an operation command clock signal; the input end of the second data selector is connected with the data signal and the characteristic value signal, and the output end of the second data selector is connected with the operation command signal.

Technical Field

The present invention relates to the field of integrated circuit design, and in particular, to a method and apparatus for operating a flash memory.

Background

According to the difference of the number of bits that can be stored in a single cell (cell) in the NAND flash memory, the NAND flash memory can be divided into different types, such as Single Level Cell (SLC), Multi Level Cell (MLC), Triple Level Cell (TLC), or Quad Level Cell (QLC). The corresponding data operation parameters need to be adjusted for the data operations of different memory cells. For example, when a data read operation is performed on a NAND flash memory, different read offset features (read offset features) need to be selected for different types of memory cells or pages (pages) belonging to different read speeds, so as to optimize the read operation performance of the flash memory and ensure the stability of stored data.

At present, when setting characteristic values such as a read compensation characteristic value of a NAND flash memory, a characteristic value setting command can be generally written through a special characteristic value setting sequence according to a characteristic value table of an onfi4.1 protocol to change the characteristic value set in a characteristic register of the NAND flash memory, so that the NAND flash memory works in an optimal state in various data operations. For example, in a NAND flash memory having both SLC cells and TLC cells, different read compensation characteristic values are set in a characteristic value setting sequence for a page in SLC and a page in TLC at different operating speeds, respectively, so as to adjust parameters such as resolution and scanning range of a read level, thereby maintaining good read performance.

However, when the method is used to set the read compensation characteristic value and other characteristic values, an additional characteristic value setting sequence needs to be introduced, which will cause the NAND flash memory to consume additional operation time during data operation, which is not beneficial to increasing the operation speed of the device.

Therefore, it is necessary to provide a new method and apparatus for operating a flash memory to solve the above problems.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an operating method and apparatus for a flash memory, which are used to solve the problems of the prior art that an additional characteristic value setting sequence is required and additional operating time is consumed when setting characteristic values.

To achieve the above and other related objects, the present invention provides a method for operating a flash memory, comprising:

writing an operation command into the flash memory when performing data operation on the flash memory; the operation command at least comprises address information; the address information comprises a data address and a compensation characteristic value;

the flash memory includes a peripheral circuit and a memory cell array; the peripheral circuit adjusts a data operation parameter according to the compensation characteristic value and performs the data operation on the data at the data address in the memory cell array.

As an alternative of the invention, the data operation comprises a data read, a data write or a data erase.

As an alternative of the present invention, when the data operation is a data read, the compensation characteristic value includes a read compensation characteristic value, and the data operation parameter includes a read level and a resolution and a scanning range thereof.

As an alternative of the invention, the memory cells in the memory cell array comprise single-level cells and three-level cells; the three-level unit comprises a lower-layer page storage unit, a middle-layer page storage unit and an upper-layer page storage unit.

As an alternative of the present invention, the reading the compensation characteristic value includes:

a single-layer read compensation characteristic value that adjusts a read data operating parameter of the single-level cell;

a first read compensation characteristic value and a fifth read compensation characteristic value which adjust read data operation parameters of the lower page memory unit;

a second read compensation characteristic value, a fourth read compensation characteristic value and a sixth read compensation characteristic value which are used for adjusting the read data operation parameters of the middle-layer page storage unit;

a third read compensation characteristic value and a seventh read compensation characteristic value that adjust the read data operating parameters of the upper page memory cells.

As an alternative of the present invention, the read compensation characteristic values are sequentially arranged in a first compensation interval, a second compensation interval, and a third compensation interval in an address writing period; the first compensation interval is used for writing the single-layer read compensation characteristic value, the first read compensation characteristic value, the second read compensation characteristic value and the third read compensation characteristic value; the second compensation interval is used for writing the fourth read compensation characteristic value, the fifth read compensation characteristic value and the seventh read compensation characteristic value; the third compensation interval is used for writing the sixth read compensation characteristic value.

As an alternative of the present invention, a reserved interval is further provided after the third compensation interval.

As an alternative of the invention, the data address comprises a row address and a column address; in the address writing period, the sequence of the address information is sequentially arranged into a column address, a row address and a compensation characteristic value.

The present invention also provides a flash memory device, comprising: a peripheral circuit and a memory cell array;

the peripheral circuitry includes a data register and a feature register;

when the flash memory carries out data operation, writing an operation command into the peripheral circuit, wherein the operation command at least comprises address information, and the address information comprises a data address and a compensation characteristic value;

the data register is used for storing the data address; the characteristic register is used for storing the compensation characteristic value;

the peripheral circuit adjusts a data operation parameter according to the compensation characteristic value and performs the data operation on the data at the data address in the memory cell array.

As an alternative of the present invention, the peripheral circuit further includes a first data selector and a second data selector;

the input end of the first data selector is connected with a data input clock signal and a characteristic value input clock signal, and the output end of the first data selector is connected with an operation command clock signal; the input end of the second data selector is connected with the data signal and the characteristic value signal, and the output end of the second data selector is connected with the operation command signal.

As described above, the present invention provides an operating method and apparatus for a flash memory, which have the following advantages:

when the data operation is carried out on the flash memory, the compensation characteristic value is set in the address information, and a characteristic value setting sequence is not required to be additionally introduced, so that the data operation time of the flash memory is greatly saved, and the device performance is improved.

Drawings

FIG. 1 is a timing diagram illustrating an address write cycle before a read operation is performed according to one embodiment of the present invention.

FIG. 2 is a timing diagram illustrating a write-read compensation characteristic according to an embodiment of the invention.

Fig. 3 is a schematic signal connection diagram of the first data selector according to the second embodiment of the present invention.

Fig. 4 is a schematic signal connection diagram of a second data selector according to a second embodiment of the present invention.

Description of the element reference numerals

101 first data selector

102 second data selector

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Example one

Referring to fig. 1 to 2, the present embodiment provides an operating method of a flash memory, which is characterized in that:

writing an operation command into the flash memory when performing data operation on the flash memory; the operation command at least comprises address information; the address information comprises a data address and a compensation characteristic value;

the flash memory includes a peripheral circuit and a memory cell array; the peripheral circuit adjusts a data operation parameter according to the compensation characteristic value and performs the data operation on the data at the data address in the memory cell array.

In the operation method of the flash memory provided in this embodiment, when performing data operation on the flash memory, the compensation characteristic value is set in the address information, and the compensation characteristic value is written into the cache of the flash memory through the address information sequence, so that an additional characteristic value setting sequence is not required to be introduced. Therefore, the data operation time of the flash memory is greatly saved, and the performance of the device is improved.

The data operation includes, by way of example, a data read, a data write, or a data erase. In the present embodiment, the data operation is data reading, that is, when a host (host) connected to the flash memory issues a read command to the flash memory, peripheral circuits of the flash memory read data from the memory cell array by applying a read level. The compensation feature value comprises a read offset feature value and the data operation parameters comprise a read level and its resolution (resolution) and a scan range (scan range). By reading the variation of the compensation characteristic value in the characteristic register (feature register) of the flash memory, the data operation parameter for reading data from the memory cell array is adjusted to a proper value through compensation, thereby increasing the success rate of reading operation and ensuring that the memory maintains better reading operation performance.

As an example, in the present embodiment, the memory cells in the memory cell array include Single Level Cells (SLC) and Triple Level Cells (TLC); the three-level unit comprises a lower-layer page (lower page) storage unit, a middle page (middle page) storage unit and an upper page (upper page) storage unit. The NAND flash memory adopting the three-level unit as the storage unit has the advantages of small volume and low price, but has the disadvantage of slow read-write speed. On the contrary, the single-stage unit has the characteristics of fast read-write speed, large volume and high cost. In the conventional NAND flash memory, a three-level cell is generally used as a main memory cell, and a part of single-level cells are arranged as a buffer memory, so as to improve the short-time burst write speed. Therefore, the conventional NAND flash memory generally has a single level cell and a three level cell, and it is necessary to adjust data operation parameters such as read level according to different types of memory cells. Alternatively, to further reduce the size and cost of the NAND flash memory, the level three cells can be replaced by level four cells (QLC), and the memory cells in such a memory cell array will include both single level cells and level four cells.

In the three-level cell, a single memory cell needs to store 3-bit data, binary information of the single memory cell corresponds to 8 states, 7 reference voltages (respectively denoted as P1 to P7) are needed to separate and distinguish the 8 states, and the single memory cell will change in the 8 states when performing data operation. According to the speed of different storage units during data operation, the three-level unit can be further divided into a lower page (lower page) storage unit, a middle page (middle page) storage unit and an upper page (upper page) storage unit. Wherein, the speed of the storage unit of the lower page (lower page) is the fastest, the speed of the storage unit of the middle page (middle page) is the next lowest, and the speed of the storage unit of the upper page (upper page) is the slowest. In addition, when the three-level cell is replaced with a four-level cell storing 4-bit data, the binary information corresponds to 16 states, and the reference voltage and the number of pages will also change accordingly.

As an example, as shown in fig. 1, in the present embodiment, the reading of the compensation characteristic value includes:

a single-level read compensation characteristic (SLC level) that adjusts a read data operating parameter of the single-level cell;

a first read compensation characteristic (P1offset) and a fifth read compensation characteristic (P5 offset) that adjust a data operating parameter of a read of the lower page memory cells;

a second read compensation characteristic value (P2offset), a fourth read compensation characteristic value (P4 offset), and a sixth read compensation characteristic value (P6offset) that adjust a data operating parameter of a read of the middle page memory cells;

a third read compensation characteristic (P3offset) and a seventh read compensation characteristic (P7 offset) that adjust a data operating parameter of a read of the upper page memory cells.

When the flash memory reads data, the host writes the address of the read data into the peripheral circuit and sets the read compensation characteristic value. As shown in fig. 1, it is a timing diagram of an address write cycle before a read operation is performed in the present embodiment. The flash memory performs address write operations in a plurality of clock intervals between 00h and 30 h. In fig. 1, in a section a1, writing of a Column Address (CA) is to be performed; in section A2, the write of Row Address (RA); at interval a3, a write of the read compensation characteristic value will be performed. The data addresses and the compensation characteristic values are sequentially written into the peripheral circuit buffer in the order of a1 to A3. Specifically, in the a3 interval, the read compensation characteristic values are arranged in the order of the first compensation interval (offset1), the second compensation interval (offset2), and the third compensation interval (offset3) in the address write cycle. As shown in the table in fig. 1, the first compensation interval (offset1) is used for writing the single-layer read compensation characteristic value (SLC level), the first read compensation characteristic value (P1offset), the second read compensation characteristic value (P2offset), and the third read compensation characteristic value (P3 offset); the second compensation interval (offset2) is used for writing the fourth read compensation characteristic value (P4 offset), the fifth read compensation characteristic value (P5 offset), and the seventh read compensation characteristic value (P7 offset); the third compensation interval (offset3) is used for writing the sixth read compensation characteristic value (P6 offset). In addition, in fig. 1, the read compensation feature value corresponding to the feature register address can be adjusted by the Feature Address (FA), for example, A0h to A3 h. Since the storage units in different areas and types in the flash memory can share the read compensation characteristic value setting in the characteristic register when performing read data operation, the occupation of system resources by the operation method provided by the embodiment can be controlled at a lower level.

As an example, a reserved interval (reserved) is further provided after the third compensation interval (offset 3). Since the embodiment uses the three-level cell as the main storage cell, three compensation intervals of offsets 1-3 are sufficient to accommodate all the read compensation characteristic values, and unused space (NU) is left in the table.

In addition, when the subsequent product is replaced by the four-level cell, 16 states exist in a single memory cell, and the corresponding reference voltages are 15, then the three compensation intervals and the reserved interval (reserved) of the offsets 1-3 set by the embodiment are also enough to accommodate the writing of the read compensation characteristic value of the four-level cell. By analogy, if a five-layer memory cell (FLC) or more layers of memory cells are further adopted to replace a four-level cell in a newly developed flash memory, the number of reserved intervals (reserved) can be correspondingly increased.

FIG. 2 is a timing diagram of writing and reading the compensation characteristic values. In fig. 2, the DQ signal represents an input/output signal; R/B represents a ready/busy signal, and the peripheral circuit writes data into the memory cell in a low level stage thereof; the three signals, roic _ offset1[7:0], roic _ offset2[7:0], and roic _ offset3[7:0], are read compensation characteristic data that are input and written to the characteristic register at the OA1, OA2, and OA3 stages of the DQ signal, respectively. The OA1, OA2 and OA3 phases of the DQ signal correspond to the intervals of offset1, offset2 and offset3 in fig. 1, respectively. 8' h0 in roic _ offset1[7:0], roic _ offset2[7:0] and roic _ offset3[7:0] represents no data, while OA1, OA2 and OA3 represent read compensation characteristic data of OA1, OA2 and OA3, respectively, in the input DQ signal. The wefeat _ clk _ sw signal represents the clock signal used to synchronize the three-way signal writing to the feature register. In the interval of OA 3-30 h of DQ signal, with Wefeat _ clk _ sw signal as clock signal, three signals such as simultaneous roic _ offset1[7:0], roic _ offset2[7:0] and roic _ offset3[7:0] are written into the feature register.

After completing the address writing operation between 00h and 30h, the peripheral circuit of the flash memory reads data from the memory cell array according to the data address, and the data operation parameter for reading the data is also adjusted according to the read compensation characteristic value.

In this embodiment, when performing data operation on the flash memory, the compensation characteristic value is set in the address information, and a characteristic value setting sequence is not required to be additionally introduced, so that data operation time of the flash memory is greatly saved, and device performance is improved.

Example two

Referring to fig. 2 to 4, the present embodiment provides a flash memory device, including: a peripheral circuit and a memory cell array; the peripheral circuitry includes a data register and a feature register.

The memory cell array comprises memory cells for storing data, and the peripheral circuit comprises a CMOS logic circuit capable of controlling the memory cell array to perform data operations such as reading, writing or erasing.

When the flash memory carries out data operation, writing an operation command into the peripheral circuit, wherein the operation command at least comprises address information, and the address information comprises a data address and a compensation characteristic value. Specifically, the operation command includes a read, write, or erase command. When the flash memory device receives the data operation command from a host (host), the peripheral circuit will perform data operations such as reading, writing or erasing to the memory cell array according to the data operation command including an address.

The peripheral circuitry includes at least a data register and a feature register. The data register is used for storing the data address, and the characteristic register is used for storing the compensation characteristic value. The peripheral circuit adjusts a data operation parameter according to the compensation characteristic value and performs the data operation on the data at the data address in the memory cell array.

As an example, as shown in fig. 3 and 4, the peripheral circuit further includes a first data selector 101 for selecting a clock signal and a second data selector 102 for selecting a data signal.

As shown in fig. 3, a signal connection diagram of the first data selector 101 is shown. The input end of the first data selector 101 is connected to the data input clock signal and the characteristic value input clock signal, and the output end is connected to the operation command clock signal. Specifically, the first data selector 101 is used for controlling the switching of different clock signals in the peripheral circuit. The address input end of the first data selector 101 is a webeat _ clk _ sw signal, the input ends are respectively a WEB clock signal and a set _ eat _ lat _ clk signal, and the output end is a webeat _ clk signal. According to the control of the wefeat _ clk _ sw signal, the we _ feat _ clk signal at the output end can select one signal from the WEB clock signal and the set _ feat _ lat _ clk signal to be output.

Fig. 4 is a schematic diagram of signal connection of the second data selector 102. The input terminal of the second data selector 102 is connected to the data signal and the characteristic value signal, and the output terminal is connected to the operation command signal. Specifically, the second data selector 102 is used for controlling the switching of different data signals in the peripheral circuit. The second data selector 102 has its address inputs coupled to the wefeat _ clk _ sw signal, inputs coupled to the roic _ offset <31:0> signal and db _ io2lg <31:0> signal, and outputs coupled to the roic _ db _ io2lg <31:0> signal. According to the control of the wefeat _ clk _ sw signal, the roic _ db _ io2lg <31:0> signal of the output end can select one signal to be output from the roic _ offset <31:0> signal and the db _ io2lg <31:0> signal.

As can be seen from fig. 2 to 4, when the wefeat _ clk _ sw signal is 1, the input terminal of the first data selector 101 is switched to the WEB clock signal, the input terminal of the second data selector 102 is switched to the roic _ offset <31:0> signal, and the peripheral circuit uses the WEB clock signal as a clock signal to write the roic _ offset <31:0> signals including the read compensation characteristic value, i.e., roic _ offsets 1[7:0], roic _ offsets 2[7:0] and roic _ offsets 3[7:0] in fig. 2 into the characteristic register.

In summary, the present invention provides an operating method and an operating device for a flash memory, wherein the operating method is characterized in that: writing an operation command into the flash memory when performing data operation on the flash memory; the operation command at least comprises address information; the address information comprises a data address and a compensation characteristic value; the flash memory includes a peripheral circuit and a memory cell array; the peripheral circuit adjusts a data operation parameter according to the compensation characteristic value and performs the data operation on the data at the data address in the memory cell array. When the data operation is carried out on the flash memory, the compensation characteristic value is set in the address information, and a characteristic value setting sequence is not required to be additionally introduced, so that the data operation time of the flash memory is greatly saved, and the device performance is improved.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.