阅读说明：本技术 一种小数分频时钟信号的获取方法及装置 (Method and device for acquiring decimal frequency division clock signal ) 是由 陈世柱 于 2021-01-06 设计创作，主要内容包括：本申请实施例提供一种小数分频时钟信号的获取方法及装置,涉及信号处理领域,该小数分频时钟信号的获取方法包括：获取随机数、频率控制字包括的整数控制字和频率控制字包括的小数控制字；根据随机数和小数控制字,生成增减脉冲样式；根据整数控制字、增减脉冲样式以及输入的时钟信号进行分频处理,得到随机化的小数分频时钟信号。可见,实施这种实施方式,能够通过随机化的小数分频时钟信号将数字电路功率谱离散化,使得功耗尖峰不会形成,从而降低对ADC芯片、DAC芯片或其他安全类芯片(如解密芯片)的干扰,进而提高芯片的安全特性,提高旁路攻击的难度。(The embodiment of the application provides a method and a device for acquiring a decimal frequency division clock signal, which relate to the field of signal processing, and the method for acquiring the decimal frequency division clock signal comprises the following steps: acquiring a random number, an integer control word included in a frequency control word and a decimal control word included in the frequency control word; generating an increasing and decreasing pulse pattern according to the random number and the decimal control number; and performing frequency division processing according to the integer control word, the increasing and decreasing pulse patterns and the input clock signal to obtain a randomized decimal frequency division clock signal. Therefore, by implementing the implementation mode, the power spectrum of the digital circuit can be discretized through the randomized decimal frequency division clock signal, so that a power consumption peak cannot be formed, the interference on an ADC (analog to digital converter) chip, a DAC (digital to analog converter) chip or other safety chips (such as a decryption chip) is reduced, the safety characteristic of the chip is improved, and the difficulty of bypass attack is improved.)

1. A method for acquiring a fractional-N clock signal, comprising:

acquiring a random number, an integer control word included in a frequency control word and a decimal control word included in the frequency control word;

generating an increasing and decreasing pulse pattern according to the random number and the small control number;

and performing frequency division processing according to the integer control word, the increasing and decreasing pulse patterns and the input clock signal to obtain a randomized decimal frequency division clock signal.

2. The method of deriving a fractional-n clock signal according to claim 1, wherein the step of deriving the random number, the integer control word comprised by the frequency control word and the fractional control word comprised by the frequency control word comprises:

upon detection of a historical divided clock signal for driving, a random number, an integer control word comprised by a frequency control word, and a fractional control word comprised by the frequency control word are acquired.

3. The method of claim 1, wherein the step of generating an increasing or decreasing pulse pattern based on the random number and the fractional control number comprises:

initializing according to the decimal control word and a preset decimal frequency division initialization mode table to obtain an initialized decimal frequency division mode;

and updating the initialized decimal frequency division pattern according to the random number to obtain an increase and decrease pulse pattern.

4. The method of claim 3, wherein the step of updating the initialized fractional division pattern according to a random number to obtain an increasing or decreasing pulse pattern comprises:

and when the random number used for driving is detected, updating the initialized fractional frequency division pattern according to the random number to obtain an increase and decrease pulse pattern.

5. The method of claim 3, wherein the initialized fractional division pattern and the increasing/decreasing pulse pattern are stored in a shift register set.

6. An apparatus for acquiring a fractional clock signal, comprising:

an acquisition unit, configured to acquire a random number, an integer control word included in a frequency control word, and a decimal control word included in the frequency control word;

a generating unit configured to generate an increasing/decreasing pulse pattern based on the random number and the fractional control number;

and the processing unit is used for carrying out frequency division processing according to the integer control word, the increasing and decreasing pulse patterns and the input clock signal to obtain a randomized decimal frequency division clock signal.

7. The apparatus according to claim 6, wherein the obtaining unit is specifically configured to obtain a random number, an integer control word included in a frequency control word, and a decimal control word included in the frequency control word when the historical divided clock signal for driving is detected.

8. The apparatus of claim 6, wherein the generating unit comprises:

the initialization subunit is used for initializing according to the decimal control number and a preset decimal frequency division initialization mode table to obtain an initialized decimal frequency division pattern;

and the generating subunit is used for updating the initialized decimal frequency division pattern according to the random number to obtain an increase and decrease pulse pattern.

9. An electronic device, characterized in that the electronic device comprises a memory for storing a computer program and a processor for executing the computer program to cause the electronic device to perform the fractional division clock signal acquisition method of any of claims 1 to 5.

10. A readable storage medium having stored therein computer program instructions which, when read and executed by a processor, perform the method of acquiring a fractional division clock signal of any of claims 1 to 5.

Technical Field

The present invention relates to the field of signal processing, and in particular, to a method and an apparatus for acquiring a fractional frequency division clock signal.

Background

With the advent of various electronic products, the electronic circuits inherent therein have also begun to become very diverse. The use of integrated circuits such as single-chip microcomputers and FPGAs is becoming more and more common. However, whatever circuit typically includes a clock circuit, it is of great concern to the skilled artisan how to design the clock. However, in practice, it is found that the current fractional clock signal acquisition method interferes with the operation of some high-performance ADC chips or DAC chips through the power supply path or chip substrate, thereby causing the overall circuit performance to be degraded.

Disclosure of Invention

An object of the embodiments of the present application is to provide a method and an apparatus for acquiring a fractional frequency division clock signal, which can avoid interference to the operation of a high-performance ADC chip or DAC chip, so as to improve the performance of an overall circuit.

A first aspect of the embodiments of the present application provides a method for acquiring a fractional division clock signal, including:

acquiring a random number, an integer control word included in a frequency control word and a decimal control word included in the frequency control word;

generating an increasing and decreasing pulse pattern according to the random number and the small control number;

and performing frequency division processing according to the integer control word, the increasing and decreasing pulse patterns and the input clock signal to obtain a randomized decimal frequency division clock signal.

In the implementation process, the method may preferentially generate a random number by a pseudo-random number generator, and then generate a frequency control word by a clock frequency controller, wherein the frequency control word includes an integer control word and a decimal control word; then, the method internally adjusts the random number and the decimal control number according to a decimal frequency division pulse controller to generate an increasing and decreasing pulse pattern; and generating a randomized fractional-N clock signal by the clock divider for the increasing or decreasing pulse pattern, the integer control word, and the input clock. Therefore, by implementing the implementation mode, the cost of the randomization circuit can be reduced through the circuit structure conforming to the flow, and the dynamic adjustment of the clock frequency and the control of the refined power are realized, so that the normal work of high-performance chips such as ADC (analog-to-digital converter) chips or DAC (digital-to-analog converter) chips is ensured to a certain extent, and the safety characteristic of the chips can be improved.

Further, the step of obtaining the random number, the integer control word included in the frequency control word, and the decimal control word included in the frequency control word includes:

upon detection of a historical divided clock signal for driving, a random number, an integer control word comprised by a frequency control word, and a fractional control word comprised by the frequency control word are acquired.

In the implementation process, in the process of acquiring the random number, the integer control word included in the frequency control word, and the decimal control word included in the frequency control word, the method may specifically acquire the random number, the integer control word included in the frequency control word, and the decimal control word included in the frequency control word when the historical frequency division clock signal for driving is detected. It can be seen that, by implementing this embodiment, the divided clock signal can be used as a generation signal for random number generation, so that the method can specify the cycle of the fractional division flow according to the generation cycle of the divided clock signal, thereby improving the stability of the whole fractional division clock signal acquisition.

Further, the step of generating an increasing and decreasing pulse pattern according to the random number and the small control number comprises:

initializing according to the decimal control word and a preset decimal frequency division initialization mode table to obtain an initialized decimal frequency division mode;

and updating the initialized decimal frequency division pattern according to the random number to obtain an increase and decrease pulse pattern.

In the implementation process, the method can be initialized preferentially according to the decimal control number and a preset decimal frequency division initialization mode table in the process of generating the increasing and decreasing pulse patterns according to the random number and the decimal control number to obtain an initialized decimal frequency division pattern; and then updating the initialized fractional frequency division pattern according to the random number to obtain an increase and decrease pulse pattern. Therefore, by implementing the embodiment, the fractional frequency division pattern can be initialized according to the fractional control word, and then the initialized fractional frequency division pattern is updated according to the random number to obtain the increasing and decreasing pulse pattern, so that the obtaining of the randomized increasing and decreasing pulse pattern is realized, and the generation of the randomized fractional frequency division constant signal is facilitated.

Further, the step of updating the initialized fractional frequency division pattern according to the random number to obtain an increase/decrease pulse pattern includes:

and when the random number used for driving is detected, updating the initialized fractional frequency division pattern according to the random number to obtain an increase and decrease pulse pattern.

In the implementation process, the method specifically updates the initialized fractional frequency division pattern according to the random number to obtain the increase and decrease pulse pattern when the random number used for driving is detected in the process of updating the initialized fractional frequency division pattern according to the random number to obtain the increase and decrease pulse pattern. Therefore, by implementing the implementation mode, the shift register set storing the initialized fractional frequency division pattern can be updated by the register update controller at a specified time, so that a stable and ordered self-control flow is realized.

Further, the initialized fractional division pattern and the increasing and decreasing pulse pattern are both stored in a shift register set.

In the above implementation process, the initialized fractional division pattern and the increasing and decreasing pulse pattern are both stored in the shift register set, wherein the difference is that the increasing and decreasing pulse pattern can be obtained after the initialized fractional division pattern is updated in the shift register set.

A second aspect of the embodiments of the present application provides an apparatus for acquiring a fractional division clock signal, including:

an acquisition unit, configured to acquire a random number, an integer control word included in a frequency control word, and a decimal control word included in the frequency control word;

a generating unit configured to generate an increasing/decreasing pulse pattern based on the random number and the fractional control number;

and the processing unit is used for carrying out frequency division processing according to the integer control word, the increasing and decreasing pulse patterns and the input clock signal to obtain a randomized decimal frequency division clock signal.

In the implementation process, the apparatus for acquiring fractional-n clock signals may acquire a random number, an integer control word included in a frequency control word, and a fractional control word included in the frequency control word through an acquisition unit; generating, by a generating unit, an increasing/decreasing pulse pattern from the random number and the fractional control word; and performing frequency division processing by a processing unit according to the integer control word, the increasing and decreasing pulse patterns and the input clock signal to obtain a randomized fractional frequency division clock signal. Therefore, by implementing the implementation mode, the cost of the randomization circuit can be reduced through the circuit structure conforming to the flow, and the dynamic adjustment of the clock frequency and the control of the refined power are realized, so that the normal work of high-performance chips such as ADC (analog-to-digital converter) chips or DAC (digital-to-analog converter) chips is ensured to a certain extent, and the safety characteristic of the chips can be improved.

Further, the obtaining unit is specifically configured to obtain the random number, the integer control word included in the frequency control word, and the decimal control word included in the frequency control word when the historical divided clock signal for driving is detected.

In the implementation process, the apparatus for acquiring a fractional-n clock signal may specifically acquire, by the acquisition unit, the random number, the integer control word included in the frequency control word, and the fractional control word included in the frequency control word when the historical fractional-n clock signal for driving is detected. It can be seen that, by implementing this embodiment, the divided clock signal can be used as a generation signal for random number generation, so that the method can specify the cycle of the fractional division flow according to the generation cycle of the divided clock signal, thereby improving the stability of the whole fractional division clock signal acquisition.

Further, the generation unit includes:

the initialization subunit is used for initializing according to the decimal control number and a preset decimal frequency division initialization mode table to obtain an initialized decimal frequency division pattern;

and the generating subunit is used for updating the initialized decimal frequency division pattern according to the random number to obtain an increase and decrease pulse pattern.

In the implementation process, the generation unit can initialize according to the decimal control word and a preset decimal frequency division initialization mode table through the initialization subunit to obtain an initialized decimal frequency division mode; and updating the initialized fractional frequency division pattern according to a random number through a generation subunit to obtain an increase and decrease pulse pattern. Therefore, by implementing the embodiment, the fractional frequency division pattern can be initialized according to the fractional control word, and then the initialized fractional frequency division pattern is updated according to the random number to obtain the increasing and decreasing pulse pattern, so that the obtaining of the randomized increasing and decreasing pulse pattern is realized, and the generation of the randomized fractional frequency division constant signal is facilitated.

A third aspect of the embodiments of the present application provides an electronic device, including a memory and a processor, where the memory is used to store a computer program, and the processor runs the computer program to make the electronic device execute the method for acquiring a fractional-n clock signal according to any one of the first aspect of the embodiments of the present application.

A fourth aspect of the embodiments of the present application provides a computer-readable storage medium, which stores computer program instructions, and when the computer program instructions are read and executed by a processor, the method for acquiring a fractional-n clock signal according to any one of the first aspect of the embodiments of the present application is performed.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic flowchart of a method for acquiring a fractional division clock signal according to an embodiment of the present disclosure;

fig. 2 is a schematic flowchart of another fractional-n clock signal acquisition method according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of an apparatus for acquiring a fractional-n clock signal according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another apparatus for acquiring a fractional-n clock signal according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram illustrating an example of an apparatus for acquiring a fractional-n clock signal according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram illustrating a detailed example of a part of another apparatus for acquiring a fractional-n clock signal according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Example 1

Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for acquiring a fractional division clock signal according to an embodiment of the present disclosure. The method can be used in the generation process of the decimal frequency division clock signal, and particularly, the method can be applied to the design flow of the randomized decimal frequency division circuit, so that the randomized decimal frequency division circuit can carry out corresponding circuit design according to the method. The method for acquiring the fractional frequency division clock signal comprises the following steps:

s101, acquiring a random number, an integer control word included in a frequency control word and a decimal control word included in the frequency control word.

In this embodiment, the random number is a pseudo-random number generated by a pseudo-random number generator.

And S102, generating an increasing and decreasing pulse pattern according to the random number and the decimal control number.

In this embodiment, the initialized fractional frequency division pattern and the increasing/decreasing pulse pattern are both stored in the shift register set.

And S103, performing frequency division processing according to the integer control word, the increasing and decreasing pulse patterns and the input clock signal to obtain a randomized decimal frequency division clock signal.

In the embodiment, in each operation cycle, the method can not only realize fractional division by instructing the clock frequency divider to increase the counting clock pulse through the control signal generated by the fractional division clock pulse controller; fractional division can also be achieved by reducing the count clock pulses.

In the embodiment of the present application, the execution subject of the method may be a computing device such as a computer and a server, and is not limited in this embodiment.

In this embodiment, an execution subject of the method may also be an intelligent device such as a smart phone and a tablet computer, which is not limited in this embodiment.

It can be seen that, in the implementation of the fractional division clock signal obtaining method described in this embodiment, the pseudo-random number generator can preferentially generate a random number, and the clock frequency controller can generate a frequency control word, where the frequency control word includes an integer control word and a fractional control word; then, the method internally adjusts the random number and the decimal control number according to a decimal frequency division pulse controller to generate an increasing and decreasing pulse pattern; and generating a randomized fractional-N clock signal by the clock divider for the increasing or decreasing pulse pattern, the integer control word, and the input clock. Therefore, by implementing the implementation mode, the cost of the randomization circuit can be reduced through the circuit structure conforming to the flow, and the dynamic adjustment of the clock frequency and the control of the refined power are realized, so that the normal work of high-performance chips such as ADC (analog-to-digital converter) chips or DAC (digital-to-analog converter) chips is ensured to a certain extent, and the safety characteristic of the chips can be improved.

Example 2

Referring to fig. 2, fig. 2 is a schematic flow chart of a method for acquiring a fractional division clock signal according to an embodiment of the present disclosure. As shown in fig. 2, the method for acquiring the fractional division clock signal includes:

s201, when a historical frequency division clock signal used for driving is detected, a random number, an integer control word included in a frequency control word and a decimal control word included in the frequency control word are obtained.

S202, initializing according to the decimal control number and a preset decimal frequency division initialization mode table to obtain an initialized decimal frequency division mode.

In this embodiment, the fractional division initialization mode table may be in any form under the requirement of satisfying the fractional division ratio.

In this embodiment, this step may be implemented by a linear feedback shift register, or may be implemented by table lookup or the like.

And S203, when the random number used for driving is detected, updating the initialized fractional frequency division pattern according to the random number to obtain an increasing and decreasing pulse pattern.

In this embodiment, the random number may be constructed according to different irreducible polynomials. In the process of generating the pseudo random number by the pseudo random number generator, the pseudo random number generator can adjust the word length of an output vector according to requirements so as to meet the decimal frequency division requirements of different systems.

In this embodiment, the initialized fractional frequency division pattern and the increasing/decreasing pulse pattern are both stored in the shift register set.

And S204, performing frequency division processing according to the integer control word, the increasing and decreasing pulse patterns and the input clock signal to obtain a randomized decimal frequency division clock signal.

It can be seen that, by implementing the method for acquiring fractional frequency division clock signals described in this embodiment, the cost of the randomizing circuit can be reduced through the circuit structure conforming to this flow, and dynamic adjustment of the clock frequency and control of the refined power are realized, so that normal operation of high-performance chips such as an ADC chip or a DAC chip is ensured to a certain extent, and further, the safety characteristics of the chips can be improved.

Example 3

Please refer to fig. 3, fig. 3 is a schematic structural diagram of an apparatus for acquiring a fractional-n clock signal according to an embodiment of the present disclosure. As shown in fig. 3, the apparatus for acquiring a fractional division clock signal includes:

an obtaining unit 310, configured to obtain a random number, an integer control word included in a frequency control word, and a decimal control word included in the frequency control word;

a generating unit 320 for generating an increasing/decreasing pulse pattern according to the random number and the fractional control number;

the processing unit 330 is configured to perform frequency division processing according to the integer control word, the increasing/decreasing pulse pattern, and the input clock signal to obtain a randomized fractional frequency division clock signal.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating an example of an apparatus for acquiring a fractional-n clock signal according to an embodiment of the present disclosure. The apparatus for acquiring the fractional-n clock signal may specifically include a pseudo-random number generator, a fractional-n pulse controller, a clock frequency control word generator, and a time divider. Specific acquisition units 310 may include a pseudo-random number generator, a fractional divider pulse controller, generation unit 320 may include a clock frequency control word generator, and processing unit 330 may include.

In this embodiment, the fractional division clock signal obtaining apparatus is a randomized fractional divider. Fig. 5 is a block diagram of a randomized fractional divider.

For example, the pseudo random number generator generates a random number a and outputs the random number a to the decimal frequency division pulse controller when detecting the historical frequency division clock signal g output by the time frequency divider in the last cycle (i.e. each operation period, the operation period depends on whether a decimal frequency division mode is adopted, such as decimal or hexadecimal or other decimal frequency division);

the clock frequency control word generator outputs a decimal part b of the clock frequency control word to the decimal frequency division pulse controller and outputs an integer part c of the clock frequency control word to the time frequency divider;

when a decimal frequency dividing pulse controller detects a historical frequency dividing clock signal g output by a time frequency divider in the last cycle, an increasing and decreasing pulse pattern d is generated according to a received random number a and a decimal part b of a clock frequency control word;

the time divider receives the integer part c of the clock frequency control word, the increasing and decreasing pulse patterns d and the input clock signal e, and generates a randomized fractional-N clock signal f according to the integer part c of the clock frequency control word, the increasing and decreasing pulse patterns d and the input clock signal e.

In this embodiment, the pseudo-random generator is generally implemented by a Linear Feedback Shift Register (LFSR) constructed by irreducible polynomials, and it is assumed that the maximum polynomial degree of the irreducible polynomial is N, i.e. the cycle period of the LFSR is 2^ N-1. For a power format with decimal fraction divisor of 2 (e.g. 2^ M), we only need to select M bits in N taps at a time (or construct an irreducible polynomial with a shift register directly selecting M bits), but if the decimal fraction divisor is not a power format of 2 (2^ M) but an N (N is not a power of 2), then assuming that the power value of 2 slightly larger than N is 2^ N0, we can select N0 register structures and an irreducible polynomial of the highest degree of N0 to construct a linear feedback shift register whose period should be 2^ N0-1, and if the output N0 bit value (assumed as M0) is larger than N-1 at every random number output update, the output value needs to be added with 2^ N0-N, so that the output random value is M0+2^ N2-N (82923), if M0 is less than or equal to n-1, then M0 is directly output.

In this embodiment, the clock frequency control word is divided into two parts, one part is a fractional part b and is input to the fractional clock divider, the other part is an integer part c and is input to the clock divider, and the two parts of the divider controller can be a direct control word (i.e. without decoding conversion, i.e. in the format of x.y) or an indirect control word (i.e. in the format of f (x) f (y), i.e. requiring decoding conversion).

In this embodiment, the fractional division pulse controller is an important part of the whole circuit structure, and this circuit stores the pattern of increasing and decreasing pulses required for fractional division, such as the 16-ary 3.2 division format, and we perform fractional division clock generation by increasing pulses, so the stored increasing and decreasing pulse pattern may be 16' b0001_0100_0000_0000, and the output clock is used as a clock drive, the pattern information above is cyclically shifted within an operation period (i.e. within 16 output clocks), and the randomized increasing and decreasing pulse pattern d is output to the clock divider, thereby controlling the frequency dividing circuit to perform fractional division. By increasing or decreasing the pulse pattern d as described above, the pattern randomization process is controlled by the random number generated by the pseudo-random generator every operation period after the reset initialization.

In this embodiment, the clock divider receives the integer frequency dividing part c to generate the basic frequency dividing circuit, and increasing or decreasing the pulse pattern d controls the frequency dividing circuit to increase or decrease the counting pulse of the input clock in the corresponding output clock period, thereby achieving the purpose of fractional frequency division.

In this embodiment, the feedback source may select one source register to update to the first register according to the random number, or may select to update to any one register. Furthermore, the feedback source can also select a plurality of source registers according to random numbers and update the source registers to any plurality of registers.

In this embodiment, the register update controller may control one of the registers as the feedback source according to the random number, and may also control a plurality of registers as the feedback source according to the random number.

In the embodiment of the present application, for the explanation of the apparatus for acquiring a fractional-n clock signal, reference may be made to the description in embodiment 1 or embodiment 2, and details are not repeated in this embodiment.

It can be seen that, the apparatus for acquiring fractional frequency division clock signals described in this embodiment can reduce the cost of the randomizing circuit through the circuit structure conforming to this flow, and implement dynamic adjustment of the clock frequency and control of the refined power, thereby ensuring normal operation of high-performance chips such as ADC chips or DAC chips to a certain extent, and further improving the safety characteristics of the chips.

Example 4

Referring to fig. 4, fig. 4 is a schematic structural diagram of an apparatus for acquiring a fractional-n clock signal according to an embodiment of the present disclosure. The fractional-n clock signal acquisition apparatus shown in fig. 4 is optimized by the fractional-n clock signal acquisition apparatus shown in fig. 3. As shown in fig. 4, the obtaining unit 310 is specifically configured to obtain a random number, an integer control word included in a frequency control word, and a decimal control word included in the frequency control word when the historical divided clock signal for driving is detected.

As an optional implementation, the generating unit 320 includes:

the initialization subunit 321 is configured to initialize according to the fractional control number and a preset fractional frequency division initialization mode table to obtain an initialized fractional frequency division pattern;

and a generation subunit 322, configured to update the initialized fractional frequency division pattern according to the random number, so as to obtain an increase/decrease pulse pattern.

As an alternative embodiment, the generating subunit 322 is specifically configured to, when a random number for driving is detected, update the initialized fractional division pattern according to the random number, so as to obtain an increasing/decreasing pulse pattern.

In this embodiment, the process of updating the fractional division pattern occurs every integer number of cycles. For example, when counting 16 decimal fractions, the clock cycle is after 16 frequency divisions; when the counting number is 10 decimal fractions, the counting number is 10 clock cycles after frequency division; the initialized fractional frequency division pattern is updated only for the first time, each subsequent update is continuously updated on the basis of the previous frequency division pattern, and meanwhile, due to the periodic relation, the method cannot cause errors in fractional frequency division.

As an alternative embodiment, the initialized fractional division pattern and the increasing and decreasing pulse pattern are both stored in the shift register set.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating a partial detailed example of another apparatus for acquiring a fractional-n clock signal according to an embodiment of the present application. In the apparatus for acquiring a fractional division clock signal, the fractional division pulse controller may specifically include a fractional division initialization pattern table, a shift register set, a register update controller, and a feedback selector.

For example, each entry in the fractional division initialization pattern table in fig. 6 represents a different fractional division pattern for fractional division of the 16-ary pattern, and for 16-ary, 16 entries are included, and the number of "1" in each entry represents the division value of fractional division, so as to ensure the looseness of the "1" distribution when setting.

In this embodiment, at the beginning of the initialization of the system operation, the system may load the corresponding initialization fractional division pattern h into the shift register set according to the fractional part b of the clock frequency control word. The shift register set is used for storing the initialized decimal frequency division pattern h and updating the initialized decimal frequency division pattern h at the starting moment of each operation cycle. That is, the first register in the shift register set is updated to the register value selected by the random number a, the registers before the selected register (except the first register) are still sequentially shifted and assigned, the registers after the selected register are kept unchanged, except the time of starting the operation cycle, all registers are kept in cyclic shift operation at the time of each operation cycle, the total length of the shift registers is determined by the decimal system, and if the total length is 16, 16 shift registers are provided.

In this embodiment, the feedback selector may select the feedback value i fed back to the first shift register according to the random number a at the start time of each operation cycle; during each operation cycle, the shift register always selects the value of the last shift register.

In this embodiment, the register update controller is mainly used to control updating of the shift register, and when the system is initialized, the fractional frequency division pattern h is loaded into the shift register set, and at the beginning of each operation cycle, the register before the register selected by the input random number a is controlled to keep an updated state through the register update signal j, while the register after the selected register keeps unchanged, and in each operation cycle, the updated states of all registers are kept.

In this embodiment, the feedback selector may be controlled by a random number, and select a value of a corresponding register as a feedback source according to the random number. The register updating controller can control the corresponding shift register to update according to the input random number; the update may be controlled by clock gating, or may be selectively controlled according to input data.

In the embodiment of the present application, for the explanation of the apparatus for acquiring a fractional-n clock signal, reference may be made to the description in embodiment 1 or embodiment 2, and details are not repeated in this embodiment.

It can be seen that, the apparatus for acquiring fractional frequency division clock signals described in this embodiment can reduce the cost of the randomizing circuit through the circuit structure conforming to this flow, and implement dynamic adjustment of the clock frequency and control of the refined power, thereby ensuring normal operation of high-performance chips such as ADC chips or DAC chips to a certain extent, and further improving the safety characteristics of the chips.

An embodiment of the present application provides an electronic device, including a memory and a processor, where the memory is used to store a computer program, and the processor runs the computer program to make the electronic device execute the method for acquiring a fractional division clock signal in embodiment 1 or embodiment 2 of the present application.

An embodiment of the present application provides a computer-readable storage medium, which stores computer program instructions, and when the computer program instructions are read and executed by a processor, the computer program instructions perform the method for acquiring a fractional division clock signal according to any one of embodiment 1 or embodiment 2 of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.