阅读说明：本技术 低功耗触发器 (Low-power consumption trigger ) 是由 侯佳鑫 邹景 苗林 杨林 于 2020-12-31 设计创作，主要内容包括：本公开提供了一种低功耗触发器,其包括时钟脉冲生成模块和触发器模块,其中,时钟脉冲生成模块可配置成接收第一时钟信号和数据信号,并基于数据信号和低功耗触发器的第一输出信号的电平水平,生成时钟脉冲信号；以及触发器模块可配置成响应于时钟脉冲生成模块所生成的时钟脉冲信号的输入,对数据信号进行采样并锁存,以至于生成第一输出信号和第二输出信号,第二输出信号为第一输出信号的反相信号。根据本公开的实施方式的低功耗触发器在开关活动率为50％或更低时,可显著降低功耗,并具有小的延迟。(The present disclosure provides a low power consumption flip-flop, comprising a clock pulse generation module and a flip-flop module, wherein the clock pulse generation module is configurable to receive a first clock signal and a data signal and to generate a clock pulse signal based on the data signal and a level of a first output signal of the low power consumption flip-flop; and the flip-flop module may be configured to sample and latch the data signal in response to an input of the clock pulse signal generated by the clock pulse generation module so as to generate a first output signal and a second output signal, the second output signal being an inverted signal of the first output signal. The low power consumption flip-flop according to the embodiment of the present disclosure can significantly reduce power consumption with a small delay when the switching activity rate is 50% or less.)

1. A flip-flop, comprising:

a clock pulse generation module configured to receive a first clock signal and a data signal and generate a clock pulse signal based on the data signal and a level of a first output signal of the flip-flop; and

a flip-flop module configured to sample and latch the data signal in response to an input of the clock pulse signal generated by the clock pulse generation module so as to generate the first output signal and a second output signal, wherein the second output signal is an inverted signal of the first output signal.

2. The flip-flop according to claim 1, wherein said clock pulse generation module comprises:

a first clock pulse generating section configured to generate a determination signal indicating whether or not level levels of the data signal and the first output signal are the same, based on the level levels of the data signal and the first output signal;

a second clock pulse generating section configured to convert the first clock signal into a second clock signal that is an inverted signal of the first clock signal and has a delay with respect to the first clock signal; and

a third clock generation section configured to generate a clock signal based on the first clock signal, the second clock signal, and the determination signal.

3. The flip-flop according to claim 2, wherein when the data signal and the first output signal have the same level, the determination signal has a first level, and the clock pulse signal generated by the clock pulse generation module has correspondingly no trigger pulse.

4. The flip-flop according to claim 3, wherein when said data signal and said first output signal have different level levels, said determination signal has a second level different from said first level, and said clock pulse signal generated by said clock pulse generating module correspondingly has a trigger pulse.

5. The flip-flop according to claim 2, wherein the first clock pulse generating section includes a first transmission gate and a second transmission gate, first control terminals of the first transmission gate and the second transmission gate receiving the first output signal, and second control terminals of the first transmission gate and the second transmission gate receiving the second output signal;

wherein the data signal is transmitted through the first transmission gate when the first output signal has a first level; and

when the first output signal has a second level, the data signal is transmitted through the second transmission gate.

6. The flip-flop according to claim 5, wherein said first clock pulse generating section further comprises:

a first inverter having an input terminal receiving the data signal and an output terminal connected to the input terminal of the first transmission gate; and

and a second inverter having an input terminal connected to the output terminal of the first transmission gate and the output terminal of the second transmission gate, and an output terminal connected to the third clock pulse generating section.

7. The flip-flop of claim 5, wherein the first transmission gate comprises a first PMOS transistor and a first NMOS transistor;

the drain electrode of the first PMOS transistor is connected with the drain electrode of the first NMOS transistor to form the input end of the first transmission gate;

the source electrode of the first PMOS transistor is connected with the source electrode of the first NMOS transistor to form the output end of the first transmission gate;

the gate of the first PMOS transistor receives the second output signal; and

the gate of the first NMOS transistor receives the first output signal.

8. The flip-flop of claim 5, wherein the second transmission gate comprises a second PMOS transistor and a second NMOS transistor,

the drain electrode of the second PMOS transistor is connected with the drain electrode of the second NMOS transistor to form the input end of the second transmission gate;

the source electrode of the second PMOS transistor is connected with the source electrode of the second NMOS transistor to form the output end of the second transmission gate;

a gate of the second PMOS transistor receives the first output signal; and

a gate of the second NMOS transistor receives the second output signal.

9. The flip-flop according to any one of claims 2 to 8, wherein the second clock pulse generating section includes an inverter circuit unit including a third inverter, a fourth inverter, and a fifth inverter,

the input end of the third inverter receives the clock signal, and the output end of the third inverter is connected to the input end of the fourth inverter;

the output end of the fourth inverter is connected to the input end of the fifth inverter; and

an output end of the fifth inverter is connected to the third clock generation unit.

10. The flip-flop according to claim 9, wherein said third clock pulse generating section includes a clock circuit unit and an OR-NOT gate,

wherein the clock circuit unit receives the first clock signal and the second clock signal, generates a third clock signal, which is a nand signal of the first clock signal and the second clock signal, an

The judgment signal and the third clock signal are input to the NOR gate to generate the clock pulse signal.

11. The flip-flop according to claim 10, wherein when the data signal and the first output signal have different levels, the determination signal has a second level, and the clock pulse signal generated by the clock pulse generation module is an inverted signal of the third clock signal.

12. The flip-flop of claim 10, wherein the clock circuit unit comprises a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, wherein,

the grid electrode of the third PMOS transistor is connected to the first clock signal, the drain electrode of the third PMOS transistor is connected with the drain electrodes of the third NMOS transistor and the fourth PMOS transistor, and the source electrode of the third PMOS transistor is connected with a system voltage source;

the grid electrode of the fourth PMOS transistor receives the second clock signal, and the source electrode of the fourth PMOS transistor is connected to the system voltage source;

a gate of the third NMOS transistor receives the first clock signal, and a source is connected to a drain of the fourth NMOS transistor; and

the gate of the fourth NMOS transistor receives the second clock signal and the source is grounded.

13. The flip-flop of claim 1, wherein the flip-flop module is further configured to sample the data signal and latch the data signal on a rising edge of the clock pulse signal such that the first output signal is the same as the data signal.

14. The flip-flop of claim 13, wherein the flip-flop module comprises a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor,

wherein a gate of the fifth PMOS transistor receives the clock signal, a drain is connected to a drain of the fifth NMOS transistor, and a source is connected to a system voltage source;

a gate of a sixth PMOS transistor is connected to a drain of the fifth PMOS transistor and a drain of the fifth NMOS transistor, a drain is connected to a source of an eighth NMOS transistor, and a source is connected to the system voltage source;

the grid electrode of the fifth NMOS transistor receives the data signal, and the source electrode of the fifth NMOS transistor is connected to the drain electrode of the sixth NMOS transistor;

a gate of the sixth NMOS transistor receives the second output signal and a source is connected to a drain of the seventh NMOS transistor;

the grid electrode of the seventh NMOS transistor receives the clock pulse signal, and the source electrode of the seventh NMOS transistor is grounded;

the gate of the eighth NMOS transistor receives the clock signal and the drain receives the data signal.

15. The flip-flop of claim 14, wherein the flip-flop module further comprises a sixth inverter and a seventh inverter forming an inverter loop, the inverter loop receiving the first output signal and outputting the second output signal,

wherein an input terminal of the sixth inverter receives the first output signal and is connected to an output terminal of the seventh inverter, and an output terminal is connected to an input terminal of the seventh inverter.

16. The flip-flop according to claim 4 or 5, wherein said first level is a high level and said second level is a low level.

17. The flip-flop of claim 1, wherein said flip-flop operates at a clock frequency of 250 MHz.

Technical Field

The application relates to the technical field of electronic circuits, in particular to a low-power-consumption trigger.

Background

Flip-flops are widely used in current Circuit designs, particularly Integrated Circuit (IC) designs. In very large scale integrated circuits, how to reduce power consumption is a direct goal of low power designs, and the main reason for power consumption is the constant transition between high frequencies 0 and 1; the rest energy consumption is composed of dynamic state and static state according to different circuit characteristics, wherein the dynamic circuit consumes energy by pre-charging a circuit node capacitor, and the static circuit mainly consumes energy in a dummy region leakage current mode. Thus, the clock network consisting of sequential cells (flip-flops and latches) is a major source of energy consumption in large scale integrated circuit systems. In a typical IC design, about 30% to 60% of the energy is consumed in the clock network. The energy consumption of the whole system is directly reduced by reducing the energy consumption of the trigger, and meanwhile, the performance improvement of the trigger directly reduces the distribution constraint of a clock network and improves the performance of the whole system. Therefore, the proper design and selection of the flip-flop has a significant impact on the performance and energy consumption of the overall system.

However, the conventional flip-flop still has a large power consumption under the condition of a low data flip-over rate, which affects the performance of the whole system. It is desirable to provide a low power consumption flip-flop, especially one with low power consumption and small delay at low data flip rates.

It should be appreciated that this background section is intended in part to provide a useful background for understanding the technology. This background section, however, may also include views, concepts or insights that are part of what is not known or understood by those of ordinary skill in the relevant art prior to the corresponding effective application date of the subject matter disclosed herein.

Disclosure of Invention

The present disclosure provides a low power flip-flop that may solve, at least in part, the above-mentioned problems in the prior art.

Embodiments of the present disclosure are directed to a low power consumption flip-flop including a clock pulse generation module and a flip-flop module, wherein the clock pulse generation module may be configured to receive a first clock signal and a data signal and generate a clock pulse signal based on the data signal and a level of a first output signal of the low power consumption flip-flop; and the flip-flop module may be configured to sample and latch the data signal in response to an input of the clock pulse signal generated by the clock pulse generation module so as to generate a first output signal and a second output signal, the second output signal being an inverted signal of the first output signal.

In an exemplary embodiment, the clock pulse generating module may include: a first clock pulse generating section configured to generate a determination signal indicating whether or not the level levels of the data signal and the first output signal are the same, based on the level levels of the data signal and the first output signal; a second clock pulse generating section configured to convert the first clock signal into a second clock signal which is an inverted signal of the first clock signal and has a delay with respect to the first clock signal; and a third clock pulse generating section configured to generate a clock pulse signal based on the first clock signal, the second clock signal, and the determination signal.

In an exemplary embodiment, the determination signal may have a first level when the data signal and the first output signal have the same level, and the clock pulse signal generated by the clock pulse generation module has correspondingly no trigger pulse.

In an exemplary embodiment, when the data signal and the first output signal have different level levels, the determination signal may have a second level different from the first level, and the clock pulse signal generated by the clock pulse generation module may have a trigger pulse.

In an exemplary embodiment, the first clock pulse generating part may include a first transmission gate and a second transmission gate. First control terminals of the first and second transmission gates receive the first output signal, and second control terminals of the first and second transmission gates receive the second output signal. When the first output signal has a first level, the data signal may be transmitted through the first transmission gate; and when the first output signal has a second level, the data signal may be transmitted through the second transmission gate.

In an exemplary embodiment, the first clock pulse generating part may further include: a first inverter, the input end of which receives the data signal and the output end of which is connected to the input end of the first transmission gate; and a second inverter having an input terminal connected to the output terminal of the first transmission gate and the output terminal of the second transmission gate, and an output terminal connected to the third clock pulse generating section.

In an exemplary embodiment, the first transmission gate may include a first PMOS transistor and a first NMOS transistor. The drain electrode of the first PMOS transistor is connected with the drain electrode of the first NMOS transistor to form the input end of the first transmission gate. The source of the first PMOS transistor is connected to the source of the first NMOS transistor to form the output of the first transmission gate. The gate of the first PMOS transistor receives the second output signal and the gate of the first NMOS transistor receives the first output signal.

In an exemplary embodiment, the second transmission gate may include a second PMOS transistor and a second NMOS transistor. And the drain electrode of the second PMOS transistor is connected with the drain electrode of the second NMOS transistor to form the input end of the second transmission gate. The source of the second PMOS transistor is connected to the source of the second NMOS transistor to form the output of the second transmission gate. The gate of the second PMOS transistor receives the first output signal and the gate of the second NMOS transistor receives the second output signal.

In an exemplary embodiment, the second clock pulse generating part may include an inverter circuit unit including a third inverter, a fourth inverter, and a fifth inverter. The input end of the third inverter receives a clock signal, and the output end of the third inverter is connected to the input end of the fourth inverter; the output end of the fourth inverter is connected to the input end of the fifth inverter; and the output end of the fifth inverter is connected with the third clock pulse generating part.

In an exemplary embodiment, the third clock pulse generating section may include a clock circuit unit receiving the first clock signal and the second clock signal, generating a third clock signal, which is a nand signal of the first clock signal and the second clock signal, and the determination signal and the third clock signal are input to the nor gate, generating the clock pulse signal.

In an exemplary embodiment, the determination signal may have a second level when the data signal and the first output signal have different level levels, and the clock pulse signal generated by the clock pulse generating module is an inverted signal of the third clock signal.

In an exemplary embodiment, the determination signal may have the first level when the data signal and the first output signal have the same level, and the clock pulse signal generated by the clock pulse generation module does not have the trigger pulse.

In an exemplary embodiment, the clock circuit unit may include a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The grid electrode of the third PMOS transistor is connected to the first clock signal, the drain electrode of the third PMOS transistor is connected with the drain electrodes of the third NMOS transistor and the fourth PMOS transistor, and the source electrode of the third PMOS transistor is connected with the system voltage source. The gate of the fourth PMOS transistor receives the second clock signal and the source is connected to the system voltage source. The gate of the third NMOS transistor receives the first clock signal and the source is connected to the drain of the fourth NMOS transistor. The gate of the fourth NMOS transistor receives the second clock signal and the source is grounded.

In an exemplary embodiment, the flip-flop module may sample and latch the data signal at a rising edge of the clock pulse signal such that the first output signal is the same as the data signal.

In an exemplary embodiment, the flip-flop module may include a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor. The gate of the fifth PMOS transistor receives a clock signal, the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor, and the source of the fifth PMOS transistor is connected to a system voltage source. The gate of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor and the drain of the fifth NMOS transistor, the drain is connected to the source of the eighth NMOS transistor, and the source is connected to the system voltage source. The gate of the fifth NMOS transistor receives the data signal and the source is connected to the drain of the sixth NMOS transistor. The gate of the sixth NMOS transistor receives the second output signal and the source is connected to the drain of the seventh NMOS transistor. The gate of the seventh NMOS transistor receives the clock signal and the source is grounded. The gate of the eighth NMOS transistor receives the clock signal and the drain receives the data signal.

In an exemplary embodiment, the flip-flop module may further include a sixth inverter and a seventh inverter constituting an inverter loop, the inverter loop receiving the first output signal and outputting the second output signal. The input end of the sixth inverter receives the first output signal and is connected to the output end of the seventh inverter, and the output end of the sixth inverter is connected to the input end of the seventh inverter.

In an exemplary embodiment, the first level may be a high level, and the second level may be a low level.

In an exemplary embodiment, the low power flip-flop operates at a clock frequency of about 250 MHz.

Compared with the prior art, the beneficial effects of the embodiment of the present disclosure are mainly reflected in: when the data rate is low, the low power consumption trigger according to the present disclosure not only can reduce power consumption, but also has small D-Q delay, and can significantly improve the performance of the integrated circuit.

Drawings

The above and other advantages and features of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a block diagram illustrating a low power consumption flip-flop according to an embodiment of the present application;

fig. 2A to 2C are circuit diagrams illustrating a clock generation module of a low power consumption flip-flop according to an embodiment of the present application;

FIG. 3 is a circuit diagram illustrating a flip-flop module of a low power flip-flop according to an embodiment of the present application;

FIG. 4 is a timing diagram illustrating low power consumption flip-flop operation according to an embodiment of the present application;

fig. 5 is a circuit diagram showing an EP-DCO flip-flop as comparative example 1 of the present application;

fig. 6 is a circuit diagram showing a CDFF flip-flop which is comparative example 2 of the present application; and

fig. 7 is a circuit diagram showing an SCDFF flip-flop as comparative example 3 of the present application.

Detailed Description

Exemplary embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Like reference numerals refer to like elements throughout the specification. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In order to provide a thorough understanding of the present disclosure, a detailed structure will be set forth in the following description in order to explain the technical solutions proposed by the present disclosure. The following detailed description of preferred embodiments of the disclosure, however, the disclosure may have other embodiments in addition to those detailed.

A low power consumption flip-flop according to an embodiment of the present application is described in detail below with reference to fig. 1.

Fig. 1 is a block diagram illustrating a low power consumption flip-flop 100 according to an embodiment of the present application.

Referring to fig. 1, the low power consumption flip-flop 100 may include a clock pulse generation module CLK _ GEN and a flip-flop module DFF. The clock pulse generation module CLK _ GEN may receive the clock signal CLK and the data signal D, and generate and output the clock pulse signal CLK _ pulse to the flip-flop module DFF based on the data signal D and the level of the first output signal Q of the low power consumption flip-flop 100. The flip-flop module DFF may be configured to sample and latch the received data signal D under a timing effect of the clock pulse signal clk _ pulse in response to an input of the generated clock pulse signal clk _ pulse, and generate the output signal Q and the inverted output signal QB. According to an exemplary embodiment, a low power flip-flop according to embodiments of the present application operates at a clock frequency of 250 MHz.

Fig. 2A to 2C are detailed circuit diagrams illustrating the clock pulse generation module CLK _ GEN of the low power consumption flip-flop 100 according to an embodiment of the present application. Fig. 2A to 2C respectively show specific circuit structures of three parts CLK _ GEN1, CLK _ GEN2, and CLK _ GEN3 of the clock pulse generation module CLK _ GEN. Specifically, the clock pulse generation module CLK _ GEN may include: a first clock pulse generating section CLK _ GEN1 configured to generate a determination signal YB indicating whether or not the level levels of the data signal D and the first output signal Q are the same, based on the level levels of the data signal D and the first output signal Q; a second clock pulse generation section CLK _ GEN2 configured to convert the first clock signal CLK into a second clock signal CLK3, the second clock signal CLK3 being an inverted signal of the first clock signal CLK and having a delay with respect to the first clock signal CLK; and a third clock pulse generating unit CLK _ GEN3 configured to generate a clock pulse signal CLK _ pulse based on the first clock signal CLK, the second clock signal CLK3, and the determination signal YB.

As shown in fig. 2A to 2C, the clock pulse generation module CLK _ GEN may include five inverters for generating inverted signals of the clock signal CLK and the data signal D and one nor gate for generating the clock pulse signal CLK _ pulse based on the clock signal CLK and the data signal D and the inverted signals of the clock signal CLK3 and the data signal D.

Referring to fig. 2A, the first clock pulse generating part CLK _ GEN1 may include a first transmission gate G1 and a second transmission gate G2. First control terminals of the first and second transmission gates G1, G2 receive the first output signal Q, and second control terminals of the first and second transmission gates G1, G2 receive the second output signal QB. Wherein, when the first output signal Q has a first level (e.g., a high level), the data signal Q is transmitted through the first transmission gate G1. And when the first output signal Q has a second level (e.g., a low level), the data signal D is transmitted through the second transmission gate G2.

The first clock pulse generating part CLK _ GEN1 may further include a first inverter I1 and a second inverter I2. The input terminal of the first inverter I1 receives the data signal D, and the output terminal thereof is connected to the input terminal IN of the first transmission gate G1. The second inverter I2 has an input terminal connected to the output terminal OUT of the first transmission gate G1 and the output terminal OUT of the second transmission gate G2, and an output terminal connected to the third clock pulse generating section CLK _ GEN 3.

The first transmission gate may include a first PMOS transistor P1 and a first NMOS transistor N1. The drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1, forming the input of the first transmission gate. The source of the first PMOS transistor P1 is connected to the source of the first NMOS transistor N1, forming the output of the first transmission gate G1. The gate of the first PMOS transistor P1 receives the second output signal QB, and the gate of the first NMOS transistor N1 receives the first output signal Q.

The second transmission gate may include a second PMOS transistor P2 and a second NMOS transistor N2. The drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2, forming the input terminal of the second transmission gate G2. The source of the second PMOS transistor P2 is connected to the source of the second NMOS transistor N2, forming the output of the second transmission gate G2. The gate of the second PMOS transistor P2 receives the first output signal Q and the gate of the second NMOS transistor N2 receives the second output signal QB.

In an embodiment, when the data signal D and the first output signal Q have the same level, the determination signal YB may have a first level (e.g., a high level) without a trigger pulse in the clock pulse signal CLK _ pulse generated by the clock pulse generation module CLK _ GEN. When the data signal D and the first output signal Q have different level levels, the determination signal YB may have a second level (e.g., a low level) different from the first level, and the clock pulse signal CLK _ pulse generated by the clock pulse generation module CLK _ GEN has a trigger pulse.

Referring to fig. 2B, the second clock pulse generating section CLK _ GEN2 may include an inverter circuit unit inv _ c including a third inverter I3, a fourth inverter I4, and a fifth inverter I5. The input end of the third inverter I3 receives the clock signal clk, and the output end is connected to the input end of the fourth inverter I4; the output end of the fourth inverter I4 is connected to the input end of the fifth inverter I5; and an output terminal of the fifth inverter I5 is connected to the third clock pulse generating section CLK _ GEN 3.

In the second clock generation section CLK _ GEN2, the inverter circuit unit inv _ c is composed of three inverters I3, I4, and I5, and a delayed inverted clock signal can be generated. Fig. 2B is a clock chain diagram, and as shown in fig. 2B, the input clock signal clk may be converted into a clock signal clk1 by a third inverter I3, further into a clock signal clk2 by a fourth inverter I4, and further into a clock signal clk3 by a fifth inverter I5.

Referring to fig. 2C, the third clock pulse generation part CLK _ GEN3 may include a clock circuit unit CLK _ C and an NOR gate NOR. The clock circuit unit clk _ c may receive the first clock signal clk and the second clock signal clk3, and generate the third clock signal E. The third clock signal E is a nand signal of the first clock signal clk and the second clock signal clk 3. The generated third clock signal E and the determination signal YB generated by the first clock pulse generating unit CLK _ GEN1 are input to the NOR gate NOR, and the clock pulse signal CLK _ pulse can be generated.

The clock circuit unit clk _ c may include a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3, and a fourth NMOS transistor N4. The gate of the third PMOS transistor P3 is connected to the first clock signal clk, the drain is connected to the drains of the third NMOS transistor N3 and the fourth PMOS transistor P4, and the source is connected to the system voltage source vdd. The gate of the fourth PMOS transistor P4 receives the second clock signal clk3, and the source is connected to the system voltage source vdd. The gate of the third NMOS transistor N3 receives the first clock signal clk, and the source is connected to the drain of the fourth NMOS transistor N4. The gate of the fourth NMOS transistor N4 receives the second clock signal clk3 and the source is grounded.

In an embodiment, when the data signal D and the first output signal Q have different level levels, the determination signal YB may have a second level (e.g., a low level), and the clock pulse signal CLK _ pulse generated by the clock pulse generation module CLK _ GEN may be an inverted signal of the third clock signal E. When the data signal D and the first output signal Q have the same level, the determination signal YB may have a first level (e.g., a high level), and the clock pulse signal CLK _ pulse generated by the clock pulse generation module CLK _ GEN may not have a trigger pulse therein.

In the third clock pulse generating module portion CLK _ GEN3, the clock signals CLK and CLK3 may generate the third clock signal E through a nand gate composed of the third NMOS transistor N3, the fourth NMOS transistor N4, the third PMOS transistor P3, and the fourth PMOS transistor P4, and the determination signal YB may generate the clock pulse signal CLK _ pulse through a NOR gate NOR. Waveforms of the clock signals clk, clk3 and the generated clock pulse signal clk _ pulse are shown in fig. 4.

It will be appreciated by those skilled in the art that the NMOS and PMOS transistors described above are merely exemplary and not limiting, and that other devices having similar functions may be substituted.

Referring to fig. 2A to 2C and 4, the clock pulse generating module CLK _ GEN may have the following operating states (it should be understood that logic 0 represents a low state and logic 1 represents a high state) according to the logic states (high or low) that the data signal D, the output signal Q and the inverted output signal QB have:

(1) when the data signal D is 0, the output signal Q is 0, and the inverted output signal QB is 1, the first PMOS transistor P1 and the first NMOS transistor N1 are turned off, the second PMOS transistor P2 and the second NMOS transistor N2 are turned on, the data signal D reaches the node Y through a transmission gate formed by the second PMOS transistor P2 and the second NMOS transistor N2, at this time, Y is 0, YB is 1, and the generated clock pulse signal clk _ pulse does not have a trigger pulse.

(2) When the data signal D is 0, the output signal Q is 1, and the inverted output signal QB is 0, the first PMOS transistor P1 and the first NMOS transistor N1 are turned on, the second PMOS transistor P2 and the second NMOS transistor N2 are turned off, the data signal D reaches the node Y through a transmission gate formed by the first inverter I1, the first PMOS transistor P1 and the first NMOS transistor N1, and when Y is 1 and YB is 0, the clock pulse signal clk _ pulse can be generated, and the clock pulse signal clk _ pulse has a high-level narrow trigger pulse.

(3) When the data signal D is 1, the output signal Q is 0, and the inverted output signal QB is 1, the first PMOS transistor P1 and the first NMOS transistor N1 are turned off, the second PMOS transistor P2 and the second NMOS transistor N2 are turned on, the data signal D reaches the node Y through a transmission gate formed by the second PMOS transistor P2 and the second NMOS transistor N2, and when Y is 1 and YB is 0, the clock pulse signal clk _ pulse can be generated, and the clock pulse signal clk _ pulse has a high-level narrow trigger pulse.

(4) When the data signal D is 1, the output signal Q is 1, and the inverted output signal QB is 0, the first PMOS transistor P1 and the first NMOS transistor N1 are turned on, the second PMOS transistor P2 and the second NMOS transistor N2 are turned off, the data signal D reaches the node Y through a transmission gate formed by the first inverter I1, the first PMOS transistor P1 and the first NMOS transistor N1, Y is 0, YB is 1, and the generated clock pulse signal clk _ pulse does not have a trigger pulse.

Table 1 also lists the state relationships of the intermediate signal Y, YB and the finally generated clock pulse signal CLK _ pulse in the clock pulse generation module CLK _ GEN with the input data signal D and the output signal Q.

TABLE 1

	Y	YB	clk_pulse
				D＝Q	0	1	0
D≠Q	1	0	1

Therefore, when the data signal D and the data signal Q in the previous period have different levels, i.e., D ≠ Q, the clock pulse generation module CLK _ GEN can generate the clock pulse signal CLK _ pulse.

When the data signal CLK _ pulse has the same level as the data signal Q of the previous period, i.e., D is Q, the clock pulse generating module CLK _ GEN does not generate the clock pulse signal CLK _ pulse.

Fig. 3 is a detailed circuit diagram illustrating a flip-flop module DFF of a low power consumption flip-flop according to an embodiment of the present application.

Referring to fig. 3, the flip-flop module DFF may include a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, and an eighth NMOS transistor N8. The gate of the fifth PMOS transistor P5 receives the clock signal clk _ pulse, the drain is connected to the drain of the fifth NMOS transistor N5, and the source is connected to the system voltage source vdd. The gate of the sixth PMOS transistor P6 is connected to the drain of the fifth PMOS transistor P5 and the drain of the fifth NMOS transistor N5, the drain is connected to the source of the eighth NMOS transistor N8, and the source is connected to the system voltage source vdd. The gate of the fifth NMOS transistor N5 receives the data signal D, and the source is connected to the drain of the sixth NMOS transistor N6. The gate of the sixth NMOS transistor N6 receives the second output signal QB, and the source is connected to the drain of the seventh NMOS transistor N7. The gate of the seventh NMOS transistor N7 receives the clock pulse signal clk _ pulse, and the source is grounded. The gate of the eighth NMOS transistor N8 receives the clock signal clk _ pulse, and the drain receives the data signal D.

The flip-flop module DFF may further include a sixth inverter I6 and a seventh inverter I7 constituting an inverter loop. The inverter loop may receive the first output signal Q and output a second output signal QB, wherein an input of the sixth inverter I6 receives the first output signal Q and is connected to an output of the seventh inverter I7, and an output is connected to an input of the seventh inverter I7.

The flip-flop module DFF may sample the data signal D at a rising edge of the clock pulse signal clk _ pulse and latch the data signal D, such that the first output signal Q is the same as the data signal D.

The clock signal clk _ pulse may control the fifth PMOS transistor P5, the seventh NMOS transistor N7, and the eighth NMOS transistor N8, the data signal D may control the fifth NMOS transistor N5, the output signal QB may control the sixth NMOS transistor N6, and the dynamic node X may control the sixth PMOS transistor P6.

Fig. 4 is a timing diagram illustrating the operation of the low power flip-flop 100 according to an embodiment of the present application. Referring to fig. 1 to 4, the clock pulse generation module CLK _ GEN may generate a clock pulse signal CLK _ pulse in response to an input clock signal CLK and a data signal D; and the flip-flop module DFF may sample and latch the data signal D based on the generated clock pulse signal clk _ pulse, generating the first output signal Q and the second inverted output signal QB.

According to the logic states (high level or low level) of the data signal D, the output signal Q and the inverted output signal QB, the low power consumption flip-flop 100 according to the present application may have the following operation states:

(1) when the data signal D is 0, the output signal Q is 0, and the inverted output signal QB is 1, the output of the clock pulse generating module CLK _ GEN is Y is 0, YB is 1, which keeps the clock pulse generating module CLK _ GEN in an off state, and the clock pulse generating module CLK _ GEN outputs logic 0, so that the generated clock pulse signal CLK _ pulse has no trigger pulse.

At this time, the clock pulse signal clk _ pulse is equal to 0, the fifth PMOS transistor P5 is turned on, and the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned off;

the data signal D is equal to 0, and the fifth NMOS transistor N5 is turned off;

the inverted output signal QB is 1, and the sixth NMOS transistor N6 is turned on;

the fifth PMOS transistor is turned on, the dynamic node X is charged by the voltage source vdd, and since the pull-down channels (the fifth NMOS transistor N5, the sixth NMOS transistor N6, and the seventh NMOS transistor N7) are not all turned on and have no discharge path, the dynamic node X is charged to high level 1 by the voltage source vdd, so that the sixth PMOS transistor P6 is turned off, and therefore Q continues to maintain the previous output 0 through the loop of the sixth inverter I6 and the seventh inverter I7, and the low power consumption flip-flop 100 completes the transmission of the input to the output.

(2) When the data signal D is equal to 0, the output signal Q is equal to 1, and the inverted output signal QB is equal to 0, the output of the clock pulse generating module CLK _ GEN is equal to 1, and YB is equal to 0. This will turn on the clock pulse generation module CLK GEN. The clock pulse generating module CLK _ GEN outputs logic 1, and may generate the clock pulse signal CLK _ pulse with a high-level narrow trigger pulse, that is, the clock pulse signal CLK _ pulse is equal to 1.

At this time, the clock pulse signal clk _ pulse is equal to 1, the fifth PMOS transistor P5 is turned off, and the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned on;

the data signal D is equal to 0, and the fifth NMOS transistor N5 is turned off;

the inverted output signal QB is equal to 0, and the sixth NMOS transistor N6 is turned off;

since the pull-down channels (the fifth NMOS transistor N5, the sixth NMOS transistor N6, and the seventh NMOS transistor N7) are not all turned on and have no pull-down path, the data signal D is transmitted to the output terminal Q through the single-transistor pass gate of the eighth NMOS transistor N8 (the single-transistor pass gate of the NMOS has no threshold loss when transmitting a low level), and the output terminal Q outputs a logic 0 through the loop positive feedback of the sixth inverter I6 and the seventh inverter I7.

(3) When the data signal D is equal to 1, the output signal Q is equal to 0, and the inverted output signal QB is equal to 1, the output of the clock pulse generating module CLK _ GEN is equal to 1, and YB is equal to 0. This will turn on the clock pulse generation module CLK GEN. The clock pulse generating module CLK _ GEN outputs logic 1, and may generate the clock pulse signal CLK _ pulse with a high-level narrow trigger pulse, that is, the clock pulse signal CLK _ pulse is equal to 1.

At this time, the clock pulse signal clk _ pulse is equal to 1, the fifth PMOS transistor P5 is turned off, and the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned on;

the data signal D is 1, and the fifth NMOS transistor N5 is turned on;

the inverted output signal QB is 1, and the sixth NMOS transistor N6 is turned on;

the fifth PMOS transistor P5 is turned off, and since the pull-down channels (the fifth NMOS transistor N5, the sixth NMOS transistor N6, and the seventh NMOS transistor N7) are all turned on, the dynamic node X is discharged to the low level 0, so that the sixth PMOS transistor P6 is turned on, and the output terminal Q is charged to the high level 1 by the voltage source vdd. Q is added to keep output logic 1 through the loop positive feedback of the sixth inverter I6 and the seventh inverter I7.

(4) When the data signal D is equal to 1, the output signal Q is equal to 1, and the inverted output signal QB is equal to 0, then the output of the clock pulse generating module CLK _ GEN is Y equal to 0, YB equal to 1, which causes the clock pulse generating module CLK _ GEN to keep the off state, and the clock pulse generating module CLK _ GEN outputs logic 0, therefore, the generated clock pulse signal CLK _ pulse has no trigger pulse.

At this time, the clock pulse signal clk _ pulse is equal to 0, the fifth PMOS transistor P5 is turned on, and the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned off;

the data signal D is 1, and the fifth NMOS transistor N5 is turned on;

the inverted output signal QB is 1, and the sixth NMOS transistor N6 is turned on;

the fifth PMOS transistor P5 is turned on, the dynamic node X is charged by the voltage source vdd, and since the pull-down channels (the fifth NMOS transistor N5, the sixth NMOS transistor N6, and the seventh NMOS transistor N7) are not all turned on and have no discharge channel, the dynamic node X is charged to high level 1 by the voltage source vdd, so that the sixth PMOS transistor P6 is turned off, so Q continues to hold the previous output 1 through the sixth inverter I6 and the seventh inverter I7, and the low power consumption flip-flop 100 completes the transmission of the input to the output.

Therefore, the low power consumption flip-flop 100 can sample the input signal D through one branch, remove the internal node (e.g., dynamic node X) from the pre-charging process with the clock signal period, and introduce the inverted output signal QB into the input terminal (connected to the gate of the sixth NMOS transistor N6), thereby reducing the redundant switching process of the dynamic node X, eliminating the redundant triggering activity of the low power consumption flip-flop 100, and reducing the dynamic power consumption. In addition, only the input signal D is required in the low power consumption flip-flop 100, and the inverse signal of the data signal D does not need to be input, so that an inverter for generating the inverse signal of the data signal D is eliminated, and the circuit structure is simpler.

For comparison, fig. 5 to 7 show the structures of three types of flip-flops as three comparative examples of the present application.

Fig. 5 shows a circuit diagram of an explicit data-pulse-to-output (EP-DCO) flip-flop. Fig. 6 shows a circuit diagram of a Flip-Flop CDFF (Conditional Discharge Flip-Flop). Fig. 7 shows a circuit diagram of a Static output-controlled discharge flip-flop (Static output-controlled discharge flip-flop).

The EP-DCO is an explicit pulse trigger, which is one of the fastest pulse triggers, has a dynamic structure and small delay, and can be applied to a critical path. However, when the input data signal D is continuously at a high level, the internal dynamic node X has redundant switching activity, and is charged and discharged when the rising edge of each clock Pulse CLK-Pulse arrives, which brings extra dynamic power consumption to the circuit. And the capacitance load of the dynamic node X is larger, thus reducing the performance of the circuit.

CDFF employs a conditional discharge technique to remove redundant switching activity of internal dynamic nodes. When CLK-Pulse is high and the input data signal D changes from logic 0 to logic 1, transistors N1, N2, and N5 are turned on, the dynamic node X is discharged through transistors N1, N2, and N5, so that transistor P2 is turned on, the output signal Q is pulled up to high, and the inverted output signal QB changes to low. When the input data signal D remains at the high level, the inverted output signal QB is equal to 1, so that the transistor N5 is turned off, the discharge path of the dynamic node X is cut off, the transistor P2 is turned off, and the output signal Q remains at the high level. In the whole process, compared with an EP-DCO trigger, the internal dynamic node is charged and discharged only once, so that redundant switch conversion activities are removed, and dynamic power consumption caused by the redundant conversion activities is saved.

Unlike CDFF, the SCDFF does not need to be precharged every clock cycle, and the switching activity of the SCDFF depends on the data switching activity, which is often much smaller than the clock switching activity. Furthermore, the SCDFF can reduce the load on the dual pulse generator output from three transistors per flip-flop to two transistors (transistor M2 and transistor M6).

We compare the performance of the four flip-flops mentioned herein. The minimum D-Q delay, average power consumption at different switching probabilities, power consumption delay product (PDP), etc. comparison results for the four flip-flops are shown in table 2. As can be seen from table 2, a significant advantage is observed at a switching activity rate of 50% or less, and the low power flip-flop 100 according to the embodiment of the present application has an average power consumption of 27.49 μ W at a switching activity rate of 50%, a minimum D-Q delay of 125psec, and a PDP of 3.43. At a switching activity rate of 50%, the redundant clock pulses are stopped by the additional circuit, and thus power consumption can be reduced. Therefore, among the four flip-flops listed in the table, the low power flip-flop 100 according to an embodiment of the present application has the lowest minimum D-Q delay, the smallest PDP, and the average power consumption of the low power flip-flop 100 is significantly reduced compared to the remaining three flip-flops at a switching activity rate of 50% or less. Therefore, when the data rate is low, the low power consumption flip-flop 100 according to the embodiment of the present disclosure not only can reduce power consumption, but also has a small D-Q delay, which can significantly improve the performance of an integrated circuit.

TABLE 2

Although the foregoing example embodiments have been described with reference to the accompanying drawings, it should be understood that the foregoing example embodiments are merely illustrative and are not intended to limit the scope of the present disclosure thereto. And that various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present disclosure. All such changes and modifications are intended to be included within the scope of the present invention as set forth in the appended claims.

Those of ordinary skill in the art will appreciate that the modules described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various aspects of the disclosure. However, this disclosure should not be construed to reflect the intent: this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where such features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than others, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

The above description is only for the specific embodiment of the present invention or the description thereof, and the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope disclosed in the present application, and shall be covered by the protection scope of the present invention. The protection scope of the present application shall be subject to the protection scope of the claims.