阅读说明：本技术 施密特触发器电压比较器 (Schmitt trigger voltage comparator ) 是由 沃尔特·特尔卡里奥 迈克尔·斯图肯博姆 吉萨纳德·阿萨姆 于 2020-11-18 设计创作，主要内容包括：本公开涉及一种施密特触发器电压比较器电路,其包括：电压参考输入端；电流源,其具有连接到电压参考输入端的第一电压控制的电流源和连接到信号输入端的第二电压控制的电流源,以用于将信号输入转换为输入电流并将电压参考输入转换为参考电流；电流镜,其输入端连接到第一电压控制的电流源的输出端,以被配置和布置为使第一电流的方向反向,并且电流镜的输出端连接到第二电压控制的电流源的输出端；以及时序控制器,其用于生成数字信号以控制第一多个开关和第二多个开关,其中,第一多个开关控制第一电压控制的电流源和第二电压控制的电流源,并且第二多个开关控制电流镜。(The present disclosure relates to a schmitt trigger voltage comparator circuit, which includes: a voltage reference input; a current source having a first voltage controlled current source connected to the voltage reference input and a second voltage controlled current source connected to the signal input for converting the signal input to an input current and converting the voltage reference input to a reference current; a current mirror having an input connected to the output of the first voltage controlled current source so as to be configured and arranged to reverse the direction of the first current, and an output connected to the output of the second voltage controlled current source; and a timing controller for generating digital signals to control the first and second plurality of switches, wherein the first plurality of switches control the first and second voltage controlled current sources and the second plurality of switches control the current mirror.)

1. A schmitt trigger voltage comparator circuit (200), comprising:

a voltage reference input (208);

a current source (202) having a first voltage controlled current source (M1) connected to the voltage reference input and a second voltage controlled current source (M2) connected to the signal input for converting the signal input to an input current (Iin) and converting the voltage reference input to a reference current (Iref);

a current mirror (204) having an input connected to the output of the first voltage controlled current source (M1) to be configured and arranged to reverse the direction of the first current (Iref), and an output of the current mirror (206) connected to the output of the second voltage controlled current source (M2); and

a timing controller (206) for generating digital signals to control a first plurality of switches and a second plurality of switches (Ms2-Ms9), wherein the first plurality of switches control the first voltage controlled current source and the second voltage controlled current source, and the second plurality of switches control the current mirror.

2. The schmitt trigger voltage comparator circuit according to claim 1, wherein the timing controller (206) comprises:

a first buffer (201) and a second buffer (203);

the first buffer is configured and arranged to control the current mirror (204) and a first voltage controlled current source, and

the second buffer is configured and arranged to control the current mirror (204) and the second voltage controlled current source.

3. The Schmitt trigger voltage comparator circuit as recited in claim 2, wherein,

the first buffer (201) is connected to a first current mirror enable switch (Ms7) and a first voltage controlled current source enable switch (Ms2), and

the second buffer (203) is connected to a second current mirror enable switch (Ms8) and a second voltage controlled current source enable switch (Ms 6).

4. The Schmitt trigger voltage comparator circuit according to claims 2-3, wherein the first buffer (201) comprises two inverters (I1, I2) and the second buffer comprises two inverters (I3, I4).

5. The schmitt trigger voltage comparator circuit as recited in claim 1, further comprising: a reference voltage circuit connected to the voltage reference input (208).

6. The Schmitt trigger voltage comparator circuit of claim 5, wherein said voltage reference circuit is a resistive voltage divider comprising a first control switch (Ms1) and a second control switch (Ms4), and wherein said first control switch (Ms1) controls said voltage reference based on said input signal and said second control switch (Ms4) controls said voltage reference based on a signal from said timing controller (206).

7. A schmitt trigger voltage comparator circuit according to any of the preceding claims, configured and arranged such that when the input signal is at a zero level or a maximum level, at a maximum supply voltage or a minimum supply voltage, the DC current consumption is zero.

8. A logic circuit, comprising: the first schmitt trigger voltage comparator circuit as recited in claims 1 to 7 and the schmitt trigger voltage comparator circuit as recited in claims 1 to 7, wherein the first voltage comparator is a high-to-low voltage comparator and the second voltage comparator is a low-to-high voltage comparator.

9. The logic circuit of claim 8, wherein the level of the voltage reference is in the range of 5% to 95% of the supply voltage.

10. A logic circuit according to claims 8 to 9, wherein the level of the voltage reference for the high-to-low voltage comparator is 50% to 95% of the supply Voltage (VDD).

11. A logic circuit according to claims 8 to 9, wherein the level of the voltage reference for the low to high voltage comparator is 5 to 50% of the supply Voltage (VDD).

12. The logic circuit of claims 8 to 11, wherein the first schmitt trigger voltage comparator circuit is configured and arranged to detect a low voltage to high voltage transition over a range, and the second schmitt trigger voltage comparator circuit is configured and arranged to detect a high voltage to low voltage transition.

13. The logic circuit of claim 8, further comprising a latch (306) for receiving the outputs of the first schmitt trigger voltage comparator circuit (OUT SH) and the second schmitt trigger voltage comparator circuit (OUT SL), the latch including an output, wherein the output (OUT ST) is enabled when the output of the first schmitt trigger voltage comparator circuit (OUT SH) is high and the output of the second schmitt trigger voltage comparator circuit (OUT SL) is low.

14. The logic circuit of claims 8 to 13, wherein the latch is a set-reset latch 308.

Technical Field

The present disclosure relates to a voltage comparator. In particular, the present disclosure relates to a schmitt trigger voltage comparator, and more particularly, to an integrated circuit including such a schmitt trigger voltage comparator.

Background

Schmitt trigger (Schmitt trigger) is a common electronic circuit used for various applications such as analog-to-digital conversion and level detection in the field of integrated circuits.

Schmitt triggers are electronic circuits with positive feedback. Taking an inverted schmitt trigger as an example, when the input voltage of the inverted schmitt trigger rises, the output level remains high until the input signal exceeds a high threshold voltage VT + (also referred to as Vih). When the input voltage of the inverted schmitt trigger drops, the output level remains low until the input signal exceeds the low threshold voltage VT- (also known as Vil). The difference between the threshold voltages VT + (or Vih) and VT- (or Vil) is referred to as the hysteresis voltage. Generally, known Schmitt trigger circuits include an inverter function and a threshold setting function for setting respective threshold voltages VT-and VT +. However, the known schmitt trigger has the following problems: they do not have reference inputs, which makes it difficult to set the respective threshold voltages VT-and VT +. The threshold voltage is determined by the dimensions and (process variations used to manufacture components) that make up the schmitt trigger architecture, and these variations can result in indeterminate and undesirable variations in threshold voltage, as the threshold voltage can vary widely with process, voltage, temperature (PVT). Furthermore, the known schmitt trigger suffers from the following problems: the ratio of the threshold voltages VT + and VT-to-supply voltage may be unstable when the supply voltage varies. The hysteresis generated by such schmitt triggers is not very precise, since the threshold voltages VT + and VT-depend entirely on the supply voltage VDD and the transistor threshold voltage Vth, and can cause PVT variations, in particular when the threshold voltage is spread, i.e. when VT + increases from 50% of VDD to e.g. 80% of VDD. Likewise, the same disadvantage occurs when VT-is reduced from 50% to, for example, 20% of VDD.

There are several topologies that include a schmitt trigger function that use one or more voltage comparators. The advantage of using a voltage comparator is that the threshold voltage can be set independently of the process, voltage, temperature (PVT) issues described above. For example, a very accurate external reference may be connected, e.g. a voltage divider may be used.

However, a disadvantage of topologies using voltage comparators is that they consume DC current. Generally, any analog circuit consumes current (from a few nA to mA), with greater current meaning higher precision and higher accuracy, and likewise, smaller current, lower precision and lower accuracy. The challenge is how to develop high precision and high accuracy analog circuits with zero current consumption.

Furthermore, resistive voltage dividers have the disadvantage of setting the threshold voltage relative to the power supply, which is also a continuous DC current consumption.

Disclosure of Invention

Various example embodiments address issues such as those described above and/or other issues that will become apparent from the following disclosure of a voltage comparator that is capable of operating within a wide range of supply voltages VDD and that has no DC current consumption when the input voltage is at a maximum or zero VDD. This results in a voltage comparator capable of ultra-low power operation and high precision operation. Additionally, in certain example embodiments, aspects of the present disclosure also relate to a variable threshold voltage VT +, VT-voltage comparator. In the context of the present disclosure, no DC current consumption means zero quiescent current, i.e. 0 Amps.

According to an embodiment, there is provided a schmitt trigger voltage comparator circuit including: a voltage reference input; a current source having a first voltage controlled current source connected to the voltage reference input and a second voltage controlled current source connected to the signal input for converting the signal input to an input current and converting the voltage reference input to a reference current; a current mirror having an input connected to the output of the first voltage controlled current source so as to be configured and arranged to reverse the direction of the first current, and an output connected to the output of the second voltage controlled current source; and a timing controller for generating digital signals to control the first and second plurality of switches, wherein the first plurality of switches control the first and second voltage controlled current sources and the second plurality of switches control the current mirror.

The timing controller may include: a first buffer and a second buffer; the first buffer is configured and arranged to control the current mirror and the first voltage controlled current source, and the second buffer is configured and arranged to control the current mirror and the second voltage controlled current source.

The first buffer is connected to the first current mirror enable switch and the first voltage controlled current source enable switch, and the second buffer is connected to the second current mirror enable switch and the second voltage controlled current source enable switch.

The first buffer may include two inverters, and the second buffer may include two inverters.

The schmitt trigger voltage comparator may further include a reference voltage circuit coupled to the voltage reference input.

The voltage reference circuit may be a resistive voltage divider including a first control switch and a second control switch, and wherein the first control switch controls the voltage reference based on the input signal and the second control switch controls the voltage reference based on a signal from the timing controller.

The schmitt trigger voltage comparator circuit may be configured and arranged such that when the input signal is at a zero level or a maximum level, the DC current consumption is zero at a maximum supply voltage or a minimum supply voltage.

According to an embodiment, there is also provided a logic circuit including: the first schmitt trigger voltage comparator circuit and the schmitt trigger voltage comparator circuit of claim, wherein the first voltage comparator is a high-to-low voltage comparator and the second voltage comparator is a low-to-high voltage comparator.

The level of the voltage reference is in the range of 5% to 95% of the supply voltage. The level of the voltage reference for the high-to-low voltage comparator is 50% to 95% of the supply voltage. The level of the voltage reference for the low-to-high voltage comparator is 5% to 50% of the supply voltage.

The first schmitt trigger voltage comparator circuit is configured and arranged to detect a low-voltage to high-voltage transition over a range, and the second schmitt trigger voltage comparator circuit is configured and arranged to detect a high-voltage to low-voltage transition.

The logic circuit may further comprise a latch to receive the outputs of the first schmitt trigger voltage comparator circuit and the second schmitt trigger voltage comparator circuit, the latch comprising an output, wherein the output is enabled when the output of the first schmitt trigger voltage comparator circuit is high and the output of the second schmitt trigger voltage comparator circuit is low. The latch may be a set-reset latch.

Drawings

So that the manner in which the features of the disclosure can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments and are therefore not to be considered limiting of its scope. The drawings are intended to facilitate an understanding of the present disclosure and are not necessarily drawn to scale. Advantages of the claimed subject matter will become apparent to those skilled in the art upon reading the specification in conjunction with the drawings in which like reference numerals are used to designate like elements, and in which:

fig. 1a shows a functional block diagram of a schmitt trigger circuit according to an embodiment;

FIG. 1b shows a circuit diagram of a high-to-low Schmitt trigger circuit according to the block diagram of FIG. 1 a;

FIG. 1c shows a circuit diagram of a low-to-high Schmitt trigger circuit according to the block diagram of FIG. 1 a;

FIGS. 2 a-2 h illustrate operating waveforms for the high-to-low Schmitt trigger circuit of FIG. 1 b;

FIG. 3a shows a block diagram of a voltage comparator circuit for a Schmitt trigger circuit including the Schmitt trigger circuits of FIGS. 1b and 1c, according to an embodiment; and

fig. 3b shows operating waveforms for the voltage comparator circuit of fig. 3 a.

Detailed Description

In the following description, like reference numerals correspond to like features. In particular, voltage nodes having a common name will be understood to be at the same potential.

Fig. 1a shows a functional block diagram of a schmitt trigger voltage comparator circuit 200 according to an embodiment of the present disclosure. Schmitt trigger circuit 200 includes a voltage controlled current source 202, a current mirror 204, a timing controller 206, and a voltage reference input 208.

The current source 202 includes an input IN of the schmitt trigger voltage comparator circuit 200. The current mirror 204 includes the output OUT of the schmitt trigger voltage comparator circuit 200 and is also connected to the current source 202. The current source 202 is coupled to one of a plurality of voltage reference inputs 208, the timing controller 206, and the current mirror 204. The timing controller is coupled to another input of the plurality of voltage reference inputs 208.

The voltage reference input 208 is used to set either Vih (that is, it is the minimum voltage above which the input is considered high) or Vil (that is, it is the maximum voltage below which the input is considered low) at a particular fraction of the supply voltage VDD. In the case of Vih, the voltage reference input 208 is used to set Vih by biasing the voltage controlled current source 202, as discussed in more detail below with reference to fig. 1 b. In the case of Vil, the voltage reference input 208 is used to set Vil by biasing the voltage controlled current source 202, as discussed in more detail below with reference to FIG. 1 c. In the present example, Vih is set to 85% of the supply voltage VDD, however, the skilled person will appreciate that Vih may be any suitable fraction of VDD between 51% and 91%, or Vil may be any suitable fraction of VDD between 10% and 50%. In this manner, the arrangement of fig. 1a may be configured and arranged as a low-to-high schmitt trigger or a high-to-low schmitt trigger, as discussed in more detail below.

The current mirror 204 is connected to the voltage controlled current source 202. The voltage controlled current source 202 is used to convert the input voltage signal IN (IN this example, the reference voltage input 208 is 85% of VDD and the input voltage signal IN voltage is a variable voltage input) into a current mode. Specifically, the voltage controlled current source 202 converts the reference voltage input 208 to a reference current, and the reference current is then mirrored by a current mirror. The voltage controlled current source 202 also converts the input voltage signal IN to a current that flows through the current mirror 204.

The timing controller 206 is connected to the voltage controlled current source 202 and the current mirror 204 to ensure that each operates at the correct time to ensure interference free operation of the schmitt trigger circuit 200. In addition, the timing controller 206 also controls the mode of the schmitt trigger circuit 200 to switch between an on comparison mode or an off comparison mode, and controls the output state between on or off.

The schmitt trigger circuit 200 of fig. 1b implements the functional block diagram of fig. 1 a. The schmitt trigger circuit of fig. 1b is a low to high trigger circuit. The current mirror 204 is formed by a first current mirror transistor M3 and a second current mirror transistor M4, and the voltage controlled current source 202 is formed by a first current source transistor M1 and a second current source transistor M2. The compare function is implemented using transistors M1-M4, where M1 and M2 convert the reference voltage and input voltage into currents, and the currents are compared at node SENSEOUT using a mirror formed by M3 and M4. The current source 202 is biased by a voltage reference input 208, in this example the voltage reference input 208 comprises respective voltage divider resistors R1, R2, however, the skilled person will appreciate that any suitable voltage reference may be used. In this example, the voltage divider resistors R1 and R2 are connected in series such that the reference voltage REF is selected to be 85% of VDD. However, the skilled person will understand that the reference voltage may be any value from 0V to VDD based on the following expression:

(voltage reference) REF ═ VDD (R2/(R1+ R2))

The timing controller 206 includes a first buffer 201 having a pair of inverters I1, I2. The first inverter I1 is connected to the SENSEOUT node for driving the SENSEOUT node to the output node OUT at the input of the second inverter I2. The output node OUT is connected to a voltage controlled current source 202 through a transistor M1 for converting the voltage input IN to a current signal i2 and a transistor M4 of a current mirror 204. The current signal i1, which is the reference current converted from M3 and mirrored by transistor M4 of current mirror 204, is lower than the current signal i2, and the SENSEOUT voltage node is pulled down to the GND voltage by the current source transistor M1 of the voltage controlled current source 202. Similarly, when the current signal i2 is greater than the current signal i1, the SENSEAUT voltage node is pulled up to VDD by the current mirror transistor M4. The OUT voltage is driven by the first and second inverters I2, the output node OUTb is pulled up to VDD, thereby keeping the transistors Ms4 and Ms5 in strong inversion when the current signal I1 is greater than I2, and the current source transistor M1 enters the cutoff region. IN other words, the voltage of the input signal IN applied to the current source transistor M1 of the voltage controlled current source is lower than the reference voltage REF applied across the current source transistor M2.

However, if the output node OUTb of the second inverter I2 is pulled down to the GND voltage, when the current signal I1 is smaller than the current signal I2, the transistors Ms4 and Ms5 remain in the cut-off region, and the current source transistor M1 operates in strong inversion. IN other words, the input signal voltage IN applied to the current source transistor M1 is higher than the reference voltage REF applied to the current source transistor M2.

The function of the second buffer 203 is to delay the IN2 voltage transition so that the voltage OUT node remains connected to VDD as long as possible, since Ms7 releases the node when the input signal voltage IN exceeds the threshold voltage Vth of Ms 2. This strategy is used to avoid possible glitches on the voltage OUT node, as discussed in more detail below.

The OUTb node is at VDD during ramp up due to the OUT node voltage state and will serve to turn off current consumption when the OUT voltage is pulled down by transistor M1 and the input voltage signal IN is greater than 85% of VDD.

When the input signal voltage IN is lower than the second buffer 203 including the first inverter I3 and the second inverter I4, the transistor Ms6 is held IN the off region, and the transistor Ms7 is biased by the second inverter I2 output voltage IN a strong inversion phase. When the input voltage signal IN is lower than the REF voltage, transistor Ms7 is biased to operate strongly inverted and transistor Ms6 is biased to operate IN off, since the OUT voltage node driven by the first inverter I1 must be connected to GND.

Thus, the timing controller 206 is used for pre-charging and avoids glitches on the SENSEOUT node. That is, the current signal i1 must be ready and the current signal i1 must be greater than the current signal i2 in order to avoid the SENSEOUT node being pulled down to GND by any inherent capacitance, which would occur in the current source transistor M1 and would result in a correct voltage comparison.

Fig. 1c shows a schmitt trigger circuit 200' that also implements the functional block diagram of fig. 1 a. The schmitt trigger circuit 200' of fig. 1c is a high-to-low triggered circuit, wherein like reference numerals correspond to like features of fig. 1b and includes a voltage controlled current source 202, a current mirror 204, a timing controller 206 and a voltage reference input 208 consistent with the embodiments described above.

For example, NMOS transistors M1, M2 may be used to implement the voltage controlled current source 202 of the high-to-low schmitt trigger circuit 200', whereas PMOS transistors M1, M2 may be used to implement the voltage controlled current source for the low-to-high schmitt trigger circuit 200 topology. Similarly, the same criteria apply for the remaining transistors, i.e. the NMOS transistor will be replaced by a PMOS transistor and the PMOS transistor will be replaced by an NMOS transistor.

The function of the schmitt trigger circuit 200 of fig. 1b can be better understood with reference to the waveforms of fig. 2 a-2 h, which illustrate the operational waveforms presented at the various nodes of the schmitt trigger circuit 200 with respect to time t.

The waveform IN of fig. 2a is the input signal voltage expressed by a percentage of VDD at the input node IN of the first schmitt trigger circuit 200. The input voltage waveform IN is shown as a triangular wave only for simplifying the explanation. However, the skilled person will understand that any sinusoidal or non-sinusoidal input voltage waveform may be used. Waveform IN the waveform represents the input signal at the input node IN of fig. 1b during rising and falling events. The waveform IN is divided into six events tr1 to tr3 and tf1 to tf3 over time t. Events tr 1-tr 3 represent ramp-up, and events tf 1-tf 3 represent ramp-down. The first event tr1 depicts the waveform IN signal rising from 0V to the threshold voltage Vth of the switching transistor Ms 1. The second event tr2 represents 50% of the supply Voltage (VDD), and the third event tr3 represents 85% of the supply Voltage (VDD). The fourth event tf1 represents 85% of VDD as the waveform IN falls. The fifth event tf2 represents 50% of VDD when the waveform IN falls, and the sixth point event tf3 is the threshold voltage Vth when the waveform IN falls.

When the input signal voltage rises to reach Vth at time tr1, where Vth is the threshold voltage of the switching transistor Ms2 and the threshold voltage of the switching transistor Ms1, the threshold voltage of the switching transistor Ms2 controls the turning on and off of the voltage-controlled current source transistor M2, and the threshold voltage of the switching transistor Ms1 controls the turning on and off of the voltage reference.

Fig. 2b shows waveforms representing the behavior of node INb of fig. 1b during ramp up and ramp down events of waveform IN. The signal at node INb represents the voltage behavior at the output of inverter I3 of buffer 203 shown in fig. 1 b. During the ramp up of waveform IN, INb is connected to VDD from 0V to 50% of VDD as event tr2, since inverter I3 has not yet scanned as a logic function. The signal at node INb will be connected to 0v (gnd) until event tf2, since the voltage at waveform IN is higher than 50% of VDD. When the waveform IN voltage is between tf2 and 0V during a fall event, the voltage at node INb will be connected to VDD because the voltage at waveform IN is below 50% of VDD after the inverter logic gate behavior.

The INb control signal keeps the PMOS transistor Ma of fig. 1b off (where INb is connected to VDD) until event tr 2. This strategy is used in order to ensure that the voltage at node BIAS of fig. 1b is forced to 0V before transistor Ms7 turns off and transistor Ms6 turns on. Thus, transistor Ms4 will have the largest possible gate-source Voltage (VGS), i.e., VGS — VDD, and thus current mirror transistor M4 will be turned on to the maximum possible.

The waveforms of fig. 2c represent the behavior of the control signal IN2 of fig. 1b during ramp up and ramp down events, which the skilled person will see is an inverted form of the behavior of the node INb.

When the voltage of the waveform IN is greater than 50% of VDD, the control signal IN2 controls the turn-on of the transistor Ms6 and the turn-off of the transistor Ms 7. Likewise, when the voltage of the waveform IN is below 50% of VDD, the transistor Ms6 is turned off and the transistor Ms7 is turned on. However, when the BIAS voltage is stabilized to the diode voltage, i.e., when the drain voltage is equal to the gate voltage and the transistor Ms6 is turned on and the transistor Ms7 is turned off, the control signal IN2 represents the comparison phase initialization.

The waveform of fig. 2d represents the BIAS voltage behavior during ramp up and ramp down events. From 0V to event tr2 during ramp up, the BIAS voltage is connected to GND. From event tr2 to event tr3, the BIAS voltage level will be determined by the current through the current mirror transistor M3 connected as a diode mode transistor. The current mirror transistor M3 is biased in the saturation region, and the BIAS voltage follows the square root law between the gate-source Voltage (VGS) and the drain-source current (Id). The BIAS level voltage will be between 0V and VDD and will replicate and mirror the reference current i1 converted by transistors M2-M4. When the voltage of waveform IN is higher than the REF voltage, the BIAS level will be fixed between tr2 and tr3, so current i2 will be higher than the fixed current i 1. Since transistor M1 is turned on by signal OUTb, the BIAS voltage will then be connected to VDD. When the voltage of waveform IN exceeds 85% of VV ═ DD at event tf2 during the fall event, the BIAS voltage will switch to GND through transistor Ms5 IN series with transistor Ms 2.

There are two voltages that the BIAS voltage node must BIAS. The biased first BIAS voltage is the GND voltage. When the IN2 voltage driven by inverters I3 and I4 is 0v (gnd) and transistor Ma operates IN the off region, the voltage is set during ramp up when the IN voltage is between 0v (gnd) and about 50% VDD. The second possible BIAS voltage is a voltage at which the input voltage IN is between 50% VDD to 85% VDD as determined by current i1 when transistor M3 is connected IN DIODE mode.

The waveforms of fig. 2e represent the behavior of current IR1 during ramp up and ramp down events. The current IR1 is the current flowing through the reference 208, the reference 208 consisting of a ladder of resistors R1, R2 and two switching transistors Ms1 and Ms 4.

When the input voltage IN is between 0V to Vth at event tr1 and the transistor Ms1 is turned off, the current IR1 is 0A. When the input voltage IN is higher than the threshold voltage Vth and the transistor Ms1 is turned on, the current of the current IR1 starts to flow and will remain constant until 85% of VDD is reached at event tr 3.

When transistor Ms4 is turned off, between events tr3 and tf2, the current IR1 will be 0A between 85% of VDD. When the transistor Ms4 is turned on by the voltage of node OUTb, the current IR1 will be turned on again between events tf2 and tf3, and when the transistor Ms1 is turned off, the current IR1 will be turned off after the event tf3 point.

The waveform of fig. 2f represents the current behavior IMs5 during ramp up and ramp down events. The current behavior IMs5 is a non-zero current through the switching transistor Ms5 when the switching transistor Ma is turned on. However, this current is non-zero between 50% and 85% of VDD only during ramp up events at events tr2 and tr3, respectively. In the interval between events tf1 and tf2, no current flows through Ms5 because the OUTb signal is connected to GND, and at event tf2, the signals at nodes OUTb and INb are connected to VDD, turning on transistor Ms5 and turning off the current in transistor Ma at the same time.

The waveforms of fig. 2g represent the current behavior IMs6 during ramp up and ramp down events. The current behavior IMs6 is that the current through the switching transistor Ms6 is non-zero between events tr2 and tr3, where at event Ms6, M1(202) and M4(204) turn on and transistor M1 converts the IN voltage to current i 2. The current IMs6 is proportional to the IN voltage, and when the current IMs6 reaches the value of the current i1 (i.e., converts the reference voltage to the current i1), SENSEOUT switches to GND, thus turning on transistor M1 at event tr3, and the current IMs6 will become zero.

The waveforms of fig. 2h represent the output terminal OUT voltage behavior during ramp up and ramp down events. The output OUT signal voltage sense voltage comparison occurs when the input voltage signal IN reaches 85% of VDD at event tr3 (i.e., the input voltage signal IN equals the REF voltage and the current i1 equals the current i 2). When the input voltage signal IN is higher than the REF voltage, the output OUT voltage signal will increase to VDD. IN addition, the output OUT signal turns off the DC current consumption between events tr3 and tf2 between 85% of VDD and 50% of VDD, where it is pulled down by the buffer 203, i.e., the buffer 203 pulls down the node IN2 when the input voltage signal IN is less than 50% of the VDD trip point of the inverter I3.

The node INb connected to the gate terminal of the transistor Ma controls the switching of the transistor Ma during the comparison sequence. When the input voltage signal IN is 0V, the NMOS transistor Ma is turned off because the gate-source Voltage (VGS) is equal to VDD, so that no current will flow through Ma. When the input voltage IN is greater than the threshold voltage Vth of the transistor Ms2, the BIAS voltage is pulled down immediately. As a result, the destination current i1 (reference current) is higher than the current i2, thereby avoiding glitches in operation.

Fig. 3a shows a general functional block diagram of a voltage comparator circuit 300, the voltage comparator circuit 300 utilizing a high-to-low schmitt trigger circuit 200 and a low-to-high trigger circuit 200' of the type described above, and the output of each circuit 310, 312 being connected to a latch 306. The latch 306 may be an SR (set reset latch). The schmitt trigger circuits 200, 200' are connected to the common input terminal 308 to receive the common signal input IN. An output 310 of the first schmitt trigger circuit 200 is connected to a first input SET of the latch 306 and an output 312 of the second schmitt trigger circuit 200' is connected to a second input RESET of the latch 306. The output 314 of the voltage comparator circuit 300 is provided at the output OUT ST 314 of the latch 306.

The first schmitt trigger circuit 200 of the above-described type according to the embodiment is configured and arranged such that VT-is set and fixed at 50% of VDD and VT + is adjustable between 51% and 90% of VDD. The second schmitt trigger circuit 200' is configured and arranged such that VT-is set to 50% of VDD and VT + is set to 10% of VDD. However, the skilled person will understand that VT + can reach 94% of VDD and VT-can reach 7% of VDD. In applications, VDD may vary, for example, between 1.2 volts to 5.5 volts.

Fig. 3b shows operating waveforms representing voltages at various nodes of the voltage comparator circuit 300 of fig. 3a with respect to time t. The first waveform IN is the input signal voltage expressed as a percentage of VDD at the respective inputs 308 of the first and second schmitt trigger circuits 200, 200'. For purposes of simplifying the explanation only, the input voltage waveform IN is shown as a triangular wave, however, the skilled person will appreciate that any sinusoidal or non-sinusoidal input voltage waveform may be used. The second waveform OUT _ SH is the output of the first schmitt trigger circuit 200, and the third waveform OUT _ SL is the output of the second schmitt trigger circuit 200'. The fourth waveform OUT _ ST is the output of the latch 306. The output OUT SL 310 of the first schmitt trigger circuit 200 is typically high, while the output OUT SH of the second schmitt trigger circuit 200' is typically low.

Referring again to the input voltage waveform IN, and IN particular the rising edge of the waveform IN, as the voltage level rises over time to a time t1 corresponding to 50% of VDD, the output of the second schmitt trigger circuit 200' is triggered to fall from a high level to a low level. The rising edge (OUT SL) is used to RESET the SET RESET latch 308, which occurs when the input voltage waveform IN voltage goes from high negative VDD to GND (or low) beyond the second schmitt trigger circuit 200' VT-trip point. The output of OUT _ ST consists of a first Schmitt trigger circuit 200 and a second Schmitt trigger circuit 200'. As the voltage level of the input voltage waveform IN continues to rise to 80% of VDD at time t2, the output of the first schmitt trigger circuit 200 is triggered to rise from a low level to a high level, and the output voltage waveform rises from a low level to a high level by the operation of the latch 306. The input voltage waveform IN may continue to rise to a level near or equal to VDD or may begin to fall. As shown IN fig. 3b, the input voltage waveform IN drops over time to time t3, time t3 corresponding to a voltage level of 50% of VDD, at which point the output OUT _ SH of the first voltage sensor 302 drops from high to low. As the input voltage waveform IN continues to drop to 15% of VDD at time t4, the output of the second voltage sensor 304 rises from a low level to a high level, and the output OUT _ ST of the latch 306 drops from a high level to a low level.

Particular and preferred aspects of the invention are set out in the accompanying independent claims. Combinations of features from dependent claims and/or independent claims may be combined as appropriate and not merely as set out in the claims.

The scope of the present disclosure includes any novel feature or combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the claimed invention or mitigates any or all of the problems addressed by the present invention. The applicants hereby give notice that new claims may be formulated to such features during the prosecution of the present application or of any such further application derived therefrom. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the claims.

Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. The term "comprising" does not exclude other elements or steps and the terms "a" or "an" do not exclude a plurality. Reference signs in the claims shall not be construed as limiting their scope.