阅读说明：本技术 检测装置、半导体装置 (Detection device and semiconductor device ) 是由 原田伸太郎 池田隆之 于 2019-10-17 设计创作，主要内容包括：降低半导体装置的功耗。半导体装置包括由动态电路构成的锁存电路。锁存电路包括具有译码功能的第一电路、多个电容器、多个时钟输入端子、信号输入端子、第一输出端子及第二输出端子。在第一时钟信号为“H”信号的期间,第一电容器的电位根据第一电路的译码结果而被刷新。在第二时钟信号为“H”信号的期间,第二电容器的电位根据第一电容器的电位而被刷新,第一输出端子接收第二电容器的电位作为第一输出信号。在第三时钟信号为“H”信号的期间,第三电容器的电位根据第二电容器的电位而被刷新,第二输出端子接收第三电容器的电位作为第二输出信号。(The power consumption of the semiconductor device is reduced. The semiconductor device includes a latch circuit formed of a dynamic circuit. The latch circuit includes a first circuit having a decoding function, a plurality of capacitors, a plurality of clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. During a period in which the first clock signal is an "H" signal, the potential of the first capacitor is refreshed in accordance with a decoding result of the first circuit. During a period in which the second clock signal is an "H" signal, the potential of the second capacitor is refreshed in accordance with the potential of the first capacitor, and the first output terminal receives the potential of the second capacitor as the first output signal. During a period in which the third clock signal is an "H" signal, the potential of the third capacitor is refreshed in accordance with the potential of the second capacitor, and the second output terminal receives the potential of the third capacitor as the second output signal.)