阅读说明：本技术 一种半导体封装结构及其制造方法 (Semiconductor packaging structure and manufacturing method thereof ) 是由 王国军 曹立强 严阳阳 于 2020-12-31 设计创作，主要内容包括：本发明提供一种半导体封装结构,包括：第一互联结构层；第一芯片层,第一芯片层位于第一互联结构层一侧表面,第一芯片层包括多个第一芯片,第一芯片层中的第一芯片均正面朝向第一互联结构层且与第一互联结构层电性连接；第二芯片层,第二芯片层位于第一互联结构层背向第一芯片层一侧表面,第二芯片层包括多个第二芯片,第二芯片层中的第二芯片均正面朝向第一互联结构层且与第一互联结构层电性连接。第一芯片层和第二芯片层中的第二芯片均正面朝向第一互联结构层,通过第一互联结构层实现对面焊接。需要对接的芯片对面直接焊接,可有效减少线路传输损耗,相比于锡球焊接,芯片之间的第一互联结构层的厚度相对较薄,可以有效降低封装结构的整体厚度。(The invention provides a semiconductor packaging structure, comprising: a first interconnect structure layer; the first chip layer is positioned on one side surface of the first interconnection structure layer and comprises a plurality of first chips, and the front surfaces of the first chips in the first chip layer face the first interconnection structure layer and are electrically connected with the first interconnection structure layer; the second chip layer is arranged on one side surface, back to the first chip layer, of the first interconnection structure layer and comprises a plurality of second chips, and the second chips in the second chip layer face the first interconnection structure layer and are electrically connected with the first interconnection structure layer. And the second chips in the first chip layer and the second chip layer face to the first interconnection structure layer, and the opposite welding is realized through the first interconnection structure layer. The opposite surfaces of the chips needing butt joint are directly welded, so that the transmission loss of a circuit can be effectively reduced, and compared with tin ball welding, the thickness of the first interconnection structure layer between the chips is relatively thin, so that the whole thickness of the packaging structure can be effectively reduced.)

1. A semiconductor package structure, comprising:

a first interconnect structure layer;

the first chip layer is positioned on one side surface of the first interconnection structure layer and comprises a plurality of first chips, and the front surfaces of the first chips in the first chip layer face the first interconnection structure layer and are electrically connected with the first interconnection structure layer;

the second chip layer is located the first interconnection structure layer is in the back of the first chip layer side surface, the second chip layer comprises a plurality of second chips, and the second chips in the second chip layer face towards the first interconnection structure layer and are electrically connected with the first interconnection structure layer.

2. The semiconductor package structure of claim 1,

two or more first chips in the first chip layer are electrically connected through the first interconnection structure layer.

3. The semiconductor package structure of claim 1,

two or more second chips in the second chip layer are electrically connected through the first interconnection structure layer.

4. The semiconductor package structure of claim 1,

the number of the plurality of first chips in the first chip layer is the same as the number of the plurality of second chips in the second chip layer, and each first chip in the first chip layer and each second chip in the second chip layer are arranged in a mirror image mode about the first interconnection structure layer.

5. The semiconductor package structure of any one of claims 1-4,

first chip layer is still including the plastic envelope layer that is located first interconnection structure layer side surface, the cladding of plastic envelope layer each first chip in the first chip layer, the plastic envelope layer deviates from the surface of first interconnection structure layer one side with the back parallel and level of each second chip in the first chip layer.

6. The semiconductor package structure of any one of claims 1-4,

the second chip layer further comprises a second insulating medium layer positioned on the surface of one side, back to the first chip layer, of the first interconnection structure layer, the second insulating medium layer wraps the second chips in the second chip layer, and the surface, back to the first interconnection structure layer, of the second insulating medium layer is flush with the back of each second chip in the second chip layer;

preferably, the second insulating medium layer is a silicon medium layer.

7. The semiconductor package structure of claim 5,

the first chip layer further includes: the plastic packaging layer is arranged on the first interconnection structure layer, and the surface of the other end of the plastic packaging layer is parallel to the surface of the plastic packaging layer on the side away from the first interconnection structure layer;

the semiconductor packaging structure further comprises a second first interconnection structure layer, the second first interconnection structure layer is located on the surface of the first chip layer, which is deviated from one side of the first interconnection structure layer, and the second first interconnection structure layer is electrically connected with the plurality of conductive columns.

8. The semiconductor package structure of claim 6,

the second chip layer further includes: a plurality of conductive columns penetrating through the second insulating medium layer, wherein one end of each conductive column is electrically connected with the first interconnection structure layer, and the surface of the other end of each conductive column is flush with the surface of one side, away from the first interconnection structure layer, of the second insulating medium layer;

the semiconductor packaging structure further comprises a second first interconnection structure layer, the second first interconnection structure layer is located on the surface of the second chip layer, which is far away from one side of the first interconnection structure layer, and the second first interconnection structure layer is electrically connected with the plurality of conductive columns.

9. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:

forming a first interconnection structure layer;

forming a first chip layer, wherein the first chip layer is formed on one side surface of the first interconnection structure layer, the first chip layer comprises a plurality of first chips, and the front surfaces of the first chips in the first chip layer face the first interconnection structure layer and are electrically connected with the first interconnection structure layer;

and forming a second chip layer, wherein the second chip layer is formed on the first interconnection structure layer back to one side surface of the first chip layer and comprises a plurality of second chips, and the chips in the second chip layer face to the first interconnection structure layer and are electrically connected with the first interconnection structure layer.

10. The method of manufacturing a semiconductor package according to claim 9,

the step of forming a first chip layer includes:

attaching a plurality of first chips to one side surface of the first interconnection structure layer;

forming a plastic package layer, wherein the plastic package layer is formed on the surface of one side on which the first chips are attached, and the plastic package layer coats each first chip in the first chip layer; thinning the plastic packaging layer until the surface of one side of the plastic packaging layer, which is far away from the first interconnection structure layer, is flush with the back surface of each first chip in the first chip layer;

the step of forming a second chip layer includes:

forming a second insulating medium layer, wherein the second insulating medium layer is positioned on the surface of one side, back to the first chip layer, of the first interconnection structure layer; embedding a plurality of second chips into the second insulating medium layer, and filling gaps between the plurality of second chips and the second insulating medium layer; thinning the second insulating medium layer until the surface of one side of the second insulating medium layer, which is far away from the first interconnection structure layer, is flush with the back of each second chip in the second chip layer;

the manufacturing method of the semiconductor packaging structure further comprises the following steps: forming a plurality of conductive columns, wherein the plurality of conductive columns are formed on the first chip layer and penetrate through the plastic packaging layer, and the plurality of conductive columns are electrically connected with the first interconnection structure layer; forming a second first interconnection structure layer, wherein the second first interconnection structure layer is formed on the surface of the first chip layer, which is far away from one side of the first interconnection structure layer, and the second first interconnection structure layer is electrically connected with the plurality of conductive columns;

or, the plurality of conductive pillars are formed on the second chip layer and penetrate through the second insulating medium layer, and the plurality of conductive pillars are electrically connected with the first interconnection structure layer; forming a second first interconnection structure layer, wherein the second first interconnection structure layer is formed on the surface of the first chip layer, which is far away from one side of the first interconnection structure layer, and the second first interconnection structure layer is electrically connected with the plurality of conductive columns;

preferably, the step of forming the plurality of conductive pillars is performed before the step of forming the molding layer;

preferably, the step of forming the second insulating medium layer is: providing a silicon slide; and the step of forming a first interconnect structure layer is performed on the silicon wafer.

Technical Field

The invention relates to the technical field of semiconductor chip interconnection, in particular to a semiconductor packaging structure and a manufacturing method thereof.

Background

In a semiconductor package structure, the front surfaces of the opposite chips are usually butted by using solder balls. In the packaging structure butted by the solder balls, the solder balls are generally large in volume due to the process, so that the size of the part between the butted chips is thick, and the thinning of the whole packaging structure is influenced. And because the solder ball is bigger, the circuit between the butted chips is longer, and the circuit loss is also bigger.

Disclosure of Invention

The invention provides a semiconductor packaging structure and a manufacturing method thereof, which aim to solve the problems that the semiconductor packaging structure of a front-side butted chip is thick in size and the circuit loss of the butted chip is large.

The invention provides a semiconductor packaging structure, comprising: a first interconnect structure layer; the first chip layer is positioned on one side surface of the first interconnection structure layer and comprises a plurality of first chips, and the front surfaces of the first chips in the first chip layer face the first interconnection structure layer and are electrically connected with the first interconnection structure layer; the second chip layer is located the first interconnection structure layer is in the back of the first chip layer side surface, the second chip layer comprises a plurality of second chips, and the second chips in the second chip layer face towards the first interconnection structure layer and are electrically connected with the first interconnection structure layer.

Optionally, two or more first chips in the first chip layer are electrically connected through the first interconnect structure layer.

Optionally, two or more second chips in the second chip layer are electrically connected through the first interconnection structure layer.

Optionally, the number of the plurality of first chips in the first chip layer is the same as the number of the plurality of second chips in the second chip layer, and each first chip in the first chip layer and each second chip in the second chip layer are arranged in a mirror image manner with respect to the first interconnect structure layer.

Optionally, the first chip layer further includes a mold layer located on a side surface of the first interconnect structure layer, the mold layer covers each first chip in the first chip layer, and the mold layer deviates from the surface on one side of the first interconnect structure layer and the back side of each first chip in the first chip layer.

Optionally, the second chip layer further includes a second insulating medium layer located on the surface of the first interconnection structure layer opposite to the surface of one side of the first chip layer, the second insulating medium layer covers each second chip in the second chip layer, and the surface of one side of the second insulating medium layer, which is opposite to the first interconnection structure layer, is flush with the back surface of each second chip in the second chip layer.

Optionally, the second insulating dielectric layer is a silicon dielectric layer.

Optionally, the first chip layer further includes: the plastic packaging layer is arranged on the first interconnection structure layer, and the surface of the other end of the plastic packaging layer is parallel to the surface of the plastic packaging layer on the side away from the first interconnection structure layer; the semiconductor packaging structure further comprises a second first interconnection structure layer, the second first interconnection structure layer is positioned on the surface of the first chip layer, which is far away from one side of the first interconnection structure layer, and the second first interconnection structure layer is electrically connected with the plurality of conductive columns;

optionally, the second chip layer further includes: a plurality of conductive columns penetrating through the second insulating medium layer, wherein one end of each conductive column is electrically connected with the first interconnection structure layer, and the surface of the other end of each conductive column is flush with the surface of one side, away from the first interconnection structure layer, of the second insulating medium layer; the semiconductor packaging structure further comprises a second first interconnection structure layer, the second first interconnection structure layer is located on the surface of the second chip layer, which is far away from one side of the first interconnection structure layer, and the second first interconnection structure layer is electrically connected with the plurality of conductive columns.

The invention also provides a manufacturing method of the semiconductor packaging structure, which comprises the following steps: forming a first interconnection structure layer; the step of forming the first chip layer includes: attaching a plurality of first chips to one side surface of the first interconnection structure layer; forming a plastic package layer, wherein the plastic package layer is formed on the surface of one side on which a first chip is attached, the first chip layer comprises a plurality of first chips, and the front surfaces of the first chips in the first chip layer face the first interconnection structure layer and are electrically connected with the first interconnection structure layer; and forming a second chip layer, wherein the second chip layer is formed on the first interconnection structure layer back to one side surface of the first chip layer and comprises a plurality of second chips, and the second chips in the second chip layer face to the first interconnection structure layer and are electrically connected with the first interconnection structure layer.

Optionally, the step of forming the first chip layer includes: forming a plastic package layer, wherein the plastic package layer is formed on the surface of one side of the first interconnection structure layer and wraps each first chip in the first chip layer; thinning the plastic packaging layer until the surface of one side of the plastic packaging layer, which is far away from the first interconnection structure layer, is flush with the back surface of each first chip in the first chip layer; the step of forming a second chip layer includes: forming a second insulating medium layer, wherein the second insulating medium layer is positioned on the surface of one side, back to the first chip layer, of the first interconnection structure layer; embedding a plurality of second chips into the second insulating medium layer, and filling gaps between the plurality of second chips and the second insulating medium layer; thinning the second insulating medium layer until the surface of one side of the second insulating medium layer, which is far away from the first interconnection structure layer, is flush with the back of each second chip in the second chip layer; the semiconductor package structure manufacturing method further includes: forming a plurality of conductive columns, wherein the plurality of conductive columns are formed on the first chip layer and penetrate through the plastic packaging layer, and the plurality of conductive columns are electrically connected with the first interconnection structure layer; and forming a second first interconnection structure layer, wherein the second first interconnection structure layer is formed on the surface of one side of the first chip layer, which is deviated from the first interconnection structure layer, and the second first interconnection structure layer is electrically connected with the plurality of conductive columns. Or, the plurality of conductive pillars are formed on the second chip layer and penetrate through the second insulating medium layer, and the plurality of conductive pillars are electrically connected with the first interconnection structure layer; and forming a second first interconnection structure layer, wherein the second first interconnection structure layer is formed on the surface of one side of the first chip layer, which is deviated from the first interconnection structure layer, and the second first interconnection structure layer is electrically connected with the plurality of conductive columns.

Optionally, the step of forming the plurality of conductive pillars is performed before the step of forming the molding layer;

optionally, the step of forming the second insulating medium layer includes: providing a silicon slide; and the step of forming a first interconnect structure layer is performed on the silicon wafer.

The technical scheme of the invention has the following advantages:

1. the semiconductor packaging structure comprises a plurality of first chips in a first chip layer and a plurality of second chips in a second chip layer, wherein the front surfaces of the chips in the first chip layer and the second chip layer face a first interconnection structure layer, and the opposite welding can be realized through the first interconnection structure layer. The opposite surfaces of the chips needing butt joint are directly welded, so that the transmission loss of a circuit can be effectively reduced, and compared with tin ball welding, the thickness of the first interconnection structure layer between the chips is relatively thin through welding of the first interconnection structure layer, so that the whole thickness of the packaging structure can be effectively reduced. Meanwhile, the first interconnection structure layer is thin, so that the distance between chips is shorter, routing is shorter, and the line loss is lower. And the first interconnection structure layer between the first chip layer and the second chip layer can be manufactured in advance before embedding or mounting the chip, and the line width and the line distance can reach 200nm/200nm through the first interconnection structure layer. The front surface of the chips is butted by a solder ball, and the pitch between the chips butted on the front surface is usually about 200 μm. In the semiconductor packaging structure of the embodiment, the first interconnection structure layer is manufactured in advance through a back-end process, so that the distance between the first chip in the first chip layer and the second chip in the second chip layer can be reduced to 40-80 μm, the upper chip and the lower chip are closer, and the thickness of the whole packaging product is thinner.

2. According to the semiconductor packaging structure, the connecting structure between the first chip layer and the second chip layer is the first interconnection structure layer, so that the first chip in the first chip layer can be interconnected through the first interconnection structure layer and then connected with the chip on the opposite side of the first interconnection structure layer; the second chips in the second chip layer are also interconnected through the first interconnection structure layer, and the chips on the opposite side of the first interconnection structure layer are connected; in addition, under the condition that the number of chips in the first chip layer is the same as that of the chips in the second chip layer, the chips are respectively interconnected with the chips on the opposite side; so that there are many options for the second chip interconnection form in the first chip layer and the second chip layer.

3. According to the semiconductor packaging structure, the first chip in the first chip layer and the second chip in the second chip layer can be electrically connected to the second first interconnection structure layer through the plurality of conductive columns, and the second first interconnection structure layer is welded with an external device. The plurality of conductive pillars may be disposed in the molding compound layer of the first chip layer or in the second insulating dielectric layer of the second chip layer. When the conductive post is arranged on the plastic packaging layer, the conductive post can be formed in advance by a Damascus process before the plastic packaging layer is formed, the line width and the line distance of 200/200nm can be realized at most, and compared with the method that the conductive post is formed after the plastic packaging layer is formed, the I/O wiring density is higher.

4. In the semiconductor package structure of the invention, the second insulating medium layer in the second chip layer can be, for example, a silicon chip, and the second chip is embedded in the silicon chip to form the second chip layer. By carrying out the manufacturing process on the silicon slide, the warping degree and the warping risk of the product can be effectively reduced.

5. The packaging structure manufactured by the manufacturing method of the semiconductor packaging structure comprises a plurality of first chips in a first chip layer and a plurality of second chips in a second chip layer, wherein the front surfaces of the chips in the first chip layer and the second chip layer face the first interconnection structure layer, and the opposite welding can be realized through the first interconnection structure layer. The opposite surfaces of the chips needing butt joint are directly welded, so that the transmission loss of a circuit can be effectively reduced, and compared with tin ball welding, the thickness of the first interconnection structure layer between the chips is relatively thin through welding of the first interconnection structure layer, so that the whole thickness of the packaging structure can be effectively reduced. Meanwhile, the first interconnection structure layer is thin, so that the distance between chips is shorter, routing is shorter, and the line loss is lower. And the first interconnection structure layer between the first chip layer and the second chip layer can be manufactured in advance before embedding or mounting the chip, and the line width and the line distance can reach 200nm/200nm through the first interconnection structure layer. The front surface of the chips is butted by a solder ball, and the pitch between the chips butted on the front surface is usually about 200 μm. In the semiconductor packaging structure of the embodiment, the first interconnection structure layer is manufactured in advance through a back-end process, so that the distance between the first chip in the first chip layer and the second chip in the second chip layer can be reduced to 40-80 μm, the upper chip and the lower chip are closer, and the thickness of the whole packaging product is thinner.

6. According to the manufacturing method of the semiconductor packaging structure, the conductive posts can be formed in advance before the plastic packaging layer is formed through the Damascus process, the line width and the line distance of 200/200nm can be achieved at most, and compared with the method that the plastic packaging layer is formed first and then the conductive posts are formed, the I/O wiring density is higher.

7. The manufacturing method of the semiconductor packaging structure can be used for manufacturing a silicon carrier, for example, and the silicon carrier is used as a second insulating layer of the second chip layer and is embedded into the second chip to form the second chip layer. The warping degree and warping risk of the product can be effectively reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1-10 are schematic views of a semiconductor package structure in various states during a manufacturing process according to an embodiment of the invention;

fig. 10 is a schematic view of a semiconductor package structure according to an embodiment of the invention;

fig. 11 is a schematic view of a semiconductor package structure according to another embodiment of the invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

Example 1

Referring to fig. 1 to 10, the present embodiment provides a semiconductor package structure, including:

a first interconnect structure layer 300.

The first chip layer is positioned on one side surface of the first interconnection structure layer 300 and comprises a plurality of first chips 100, and the first chips 100 in the first chip layer face the first interconnection structure layer 300 and are electrically connected with the first interconnection structure layer 300;

and the second chip layer is positioned on the surface of the first interconnection structure layer 300 on the side opposite to the first chip layer, the second chip layer comprises a plurality of second chips 200, and the second chips 200 in the second chip layer are all arranged in a manner that the front surfaces of the second chips 200 face the first interconnection structure layer 300 and are electrically connected with the first interconnection structure layer 300.

In the semiconductor package structure of the present embodiment, the first chip 100 in the first chip layer and the second chip 200 in the second chip layer can be bonded to each other through the first interconnect structure layer 300. The front sides of the chips needing butt joint are directly butt-jointed for welding, so that the transmission loss of a circuit can be effectively reduced, and compared with the tin ball welding, the thickness of the first interconnection structure layer 300 between the chips is thinner than that of the tin ball through the welding of the first interconnection structure layer 300, so that the whole thickness of the packaging structure can be effectively reduced. Meanwhile, the first interconnection structure layer 300 is thinner, so that the distance between chips is shorter, the routing is shorter, and the line loss is lower. Moreover, the first interconnection structure layer 300 between the first chip layer and the second chip layer can be manufactured before embedding or mounting the chip, and the line width and the line distance can reach 200nm/200nm through the first interconnection structure layer. The front surface of the chips is butted by a solder ball, and the pitch between the chips butted on the front surface is usually about 200 μm. In the semiconductor package structure of this embodiment, the first interconnect structure layer 300 may be fabricated in advance through a back-end process, so that the distance between the first chip in the first chip layer and the second chip in the second chip layer may be reduced to 40 μm to 80 μm, the upper and lower chips are closer, and the thickness of the whole package product is thinner.

In the present embodiment, two or more first chips 100 in the first chip layer may be electrically connected through the first interconnect structure layer 300.

In the present embodiment, two or more second chips 200 in the second chip layer can be electrically connected through the first interconnect structure layer 300.

In the present embodiment, the number of the plurality of first chips 100 in the first chip layer may be the same as the number of the plurality of second chips 200 in the second chip layer, and when both are the same, each first chip 100 in the first chip layer and each second chip 200 in the second chip layer are arranged in a mirror image with respect to the first interconnect structure layer.

In the semiconductor package structure of the present embodiment, since the connection structure between the first chip layer and the second chip layer is the first interconnection structure layer 300, the first chips 100 in the first chip layer may be interconnected through the first interconnection structure layer 300, and then connected to the second chip 200 at the opposite side of the first interconnection structure layer 300; the second chips 200 in the second chip layer are also interconnected through the first interconnection structure layer 300, and then connected with the first chip 100 on the opposite side of the first interconnection structure layer 300; in addition, under the condition that the number of chips in the first chip layer is the same as that of the chips in the second chip layer, the chips are respectively interconnected with the chips on the opposite side; so that there are many options for the form of chip interconnection in the first chip layer and the second chip layer.

In this embodiment, the first chip layer further includes a molding compound layer 110 located on a surface of one side of the first interconnect structure layer 300, the molding compound layer 110 encapsulates each first chip 100 in the first chip layer, and a surface of the molding compound layer 110 facing away from the first interconnect structure layer 300 is flush with a back surface of each first chip 100 in the first chip layer.

The second chip layer further includes a second insulating medium layer 210 located on a surface of the first interconnection structure layer 300 opposite to the first chip layer, the second insulating medium layer 210 covers each second chip 200 in the second chip layer, and a surface of the second insulating medium layer 210 opposite to the first interconnection structure layer 300 is flush with a back surface of each second chip 200 in the second chip layer. Specifically, the second insulating dielectric layer 210 may be a silicon dielectric layer, and may be formed by a silicon chip.

The first chip layer further includes: a plurality of conductive pillars 400 penetrating the plastic package layer 110, one end of each conductive pillar 400 is electrically connected to the first interconnect structure layer 300, and the surface of the other end is flush with the surface of the plastic package layer 110 on the side departing from the first interconnect structure layer 300.

The semiconductor package structure further includes a second interconnect structure layer 500, the second interconnect structure layer 500 is located on a surface of the first chip layer facing away from the first interconnect structure layer 300, and the second interconnect structure layer is electrically connected to the plurality of conductive pillars 400.

It should be noted that, the specific form of the metal layer traces in each interconnect structure layer may be selected by those skilled in the art, which is not explicitly shown for the purpose of simplifying the illustration, and the form of the traces may be selected by those skilled in the art according to actual needs.

The first chip 100 in the first chip layer and the second chip 200 in the second chip layer may be electrically connected to the second interconnect structure layer through a plurality of conductive pillars 400. When the conductive pillars 400 are disposed on the plastic package layer 110, they may be formed in advance by a damascene process before the plastic package layer 110 is formed, and the line width and line distance of 200/200nm may be realized at most, which is higher in I/O wiring density than the case where the conductive pillars are formed after the plastic package layer 110 is formed.

The semiconductor package structure of the present embodiment further includes a filling package layer 600, wherein the filling package layer 600 is located on a side of the first interconnect structure layer 300 facing away from the first chip layer, fills a gap between the second chip 200 and the second insulating medium layer 210, and covers a back surface of the second chip 200 and a surface of the second insulating medium layer 210 facing away from the first interconnect structure layer 300.

Example 2

Referring to fig. 11, the present embodiment provides another semiconductor package structure. The difference from the above example 1 is that:

the second chip layer further includes: a plurality of conductive pillars 400 'penetrating through the second insulating dielectric layer 210, one end of each conductive pillar 400' is electrically connected to the first interconnect structure layer 300, and the surface of the other end is flush with the surface of the second insulating dielectric layer 210 on the side away from the first interconnect structure layer 300.

The semiconductor package structure further includes a second interconnect structure layer 500 ', the second interconnect structure layer 500' is located on a surface of the second chip layer facing away from the first interconnect structure layer 300, and the second interconnect structure layer 500 'is electrically connected to the plurality of conductive pillars 400';

in the semiconductor package structure of this embodiment, the second insulating dielectric layer 210 in the second chip layer may be, for example, a silicon dielectric layer, and may be formed by a silicon chip, and the second chip 200 is embedded in the silicon chip to form the second chip layer. By carrying out the manufacturing process on the silicon slide, the warping degree and the warping risk of the product can be effectively reduced.

It should be particularly noted that, the specific form of the traces in the metal layers in each interconnection structure layer can be selected by those skilled in the art, which is not shown for the purpose of simplifying the illustration, and the form of the traces can be selected by those skilled in the art according to actual needs.

Example 3

Referring to fig. 1 to 10, the present embodiment provides a method for manufacturing a semiconductor package structure, including the steps of:

a first interconnect structure layer 300 is formed.

Forming a first chip layer formed on a side surface of the first interconnect structure layer 300, where the first chip layer includes a plurality of first chips 100, and the first chips 100 in the first chip layer are all faced toward the first interconnect structure layer 300 and electrically connected to the first interconnect structure layer 300.

And forming a second chip layer, wherein the second chip layer is formed on the surface of the first interconnection structure layer 300, which is opposite to the first chip layer, the second chip layer comprises a plurality of second chips 200, and the second chips 200 in the second chip layer are all arranged in the manner that the front surfaces of the second chips 200 face the first interconnection structure layer 300 and are electrically connected with the first interconnection structure layer 300.

The package structure manufactured by the manufacturing method of the semiconductor package structure of the embodiment includes a plurality of first chips 100 in a first chip layer and a plurality of second chips 200 in a second chip layer, wherein the chips in the first chip layer and the second chip layer are both faced to the first interconnect structure layer 300, and the facing bonding can be realized through the first interconnect structure layer 300. The opposite surfaces of the chips needing butt joint are directly welded, so that the transmission loss of a circuit can be effectively reduced, and compared with the tin ball welding, the thickness of the first interconnection structure layer 300 between the chips is relatively thin through the welding of the first interconnection structure layer 300, so that the whole thickness of the packaging structure can be effectively reduced. Meanwhile, the first interconnection structure layer 300 is thinner, so that the distance between chips is shorter, the routing is shorter, and the line loss is lower. In addition, the first interconnection structure layer 300 between the first chip layer and the second chip layer can be manufactured before embedding or mounting the chip, so that the line width and the line distance can reach 200nm/200 nm. The front surface of the chips is butted by a solder ball, and the pitch between the chips butted on the front surface is usually about 200 μm. In the semiconductor package structure of the present embodiment, the first interconnect structure layer 300 is fabricated in advance through a back-end process, so that the distance between the first chip 100 in the first chip layer and the second chip 200 in the second chip layer can be reduced to 40 μm to 80 μm, the upper and lower chips are closer, and the thickness of the whole package product is thinner.

Furthermore, in the method for manufacturing a semiconductor package structure of the present embodiment,

the step of forming the first chip layer includes:

referring to fig. 3, a plurality of first chips 100 are mounted on a side surface of a first interconnect structure layer 300;

referring to fig. 4, a molding compound layer 110 is formed, the molding compound layer 110 is formed on a side surface of the first interconnect structure layer 300 where the first chips 100 are attached, and the molding compound layer 110 covers each first chip in the first chip layer; and thinning the plastic packaging layer 110 until the surface of the plastic packaging layer on the side departing from the first interconnection structure layer 300 is flush with the back surface of each first chip 100 in the first chip layer.

The step of forming the second chip layer includes:

forming a second insulating dielectric layer 210, wherein the second insulating dielectric layer 210 is positioned on the surface of the first interconnection structure layer 300, which is opposite to the first chip layer; burying a plurality of second chips 200 in a second insulating dielectric layer 210; and thinning the second insulating medium layer 210 until the surface of the second insulating medium layer 210 on the side departing from the first interconnection structure layer 300 is flush with the back surface of each second chip 200 in the second chip layer.

Specifically, referring to fig. 1, 6, 7, and 8, the step of forming the second insulating dielectric layer 210 may be: providing a silicon slide 001; and the step of forming the first interconnect structure layer 300 is performed on the silicon wafer 001. The manufacturing process is performed on the silicon carrier 001, and the silicon carrier 011 is used as the second insulating layer 210 of the second chip layer and is embedded into the second chip 200 to form the second chip layer. The warping degree and warping risk of the product can be effectively reduced.

The method for manufacturing the semiconductor package structure of the embodiment further comprises the following steps: the filling packaging layer 600 is formed by film injection, the filling packaging layer 600 is formed on the side of the first interconnection structure layer 300, which is opposite to the first chip layer, fills the gap between the second chip 200 and the second insulating medium layer 210, and covers the back surface of the second chip 200 and the surface of the second insulating medium layer 210, which is opposite to the first interconnection structure layer 300.

The method for manufacturing the semiconductor package structure of the embodiment further comprises the following steps:

referring to fig. 1, fig. 2 and fig. 10, a plurality of conductive pillars 400 are formed, the plurality of conductive pillars 400 are formed on the first chip layer and penetrate through the molding compound layer 110, and the plurality of conductive pillars 400 are electrically connected to the first interconnect structure layer 300.

A second interconnect structure layer 500 is formed, the second interconnect structure layer 500 is formed on the surface of the first chip layer facing away from the first interconnect structure layer 300, and the second interconnect structure layer 500 is electrically connected to the plurality of conductive pillars 400.

Specifically, referring to fig. 2 to 4, the step of forming the plurality of conductive pillars 400 may be performed before the step of forming the molding layer 110. The conductive pillars 400 can be formed by a damascene process before the formation of the plastic package layer, and the line width and line distance of 200/200nm can be realized at most, so that the I/O wiring density is higher compared with the case that the conductive pillars 400 are formed after the plastic package layer 110 is formed.

Alternatively, referring to fig. 11, in some other embodiments, the method for manufacturing a semiconductor package structure further includes: a plurality of conductive pillars 400 'are formed, the plurality of conductive pillars 400' are formed on the second chip layer and penetrate through the second insulating dielectric layer 210, and the plurality of conductive pillars 210 are electrically connected to the first interconnect structure layer 300.

Forming a second interconnect structure layer 500 ', wherein the second interconnect structure layer 500' is formed on a surface of the first chip layer facing away from the first interconnect structure layer 300, and the second interconnect structure layer 500 'is electrically connected to the plurality of conductive pillars 400'.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.